Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'phy-fixes-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy
Pull phy fixes from Vinod Koul:
- Qualcomm QMP X1E80100 PCIe Gen4 PHY initialisation fix
- Freescale imx8mq tuning parameter name fix
- Samsung exynos5 fir for error code in probe()
- Xilinx Zynqmp SGMII linkup failure fix
* tag 'phy-fixes-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy:
phy: xilinx: phy-zynqmp: Fix SGMII linkup failure on resume
phy: exynos5-usbdrd: fix error code in probe()
phy: fsl-imx8mq-usb: fix tuning parameter name
phy: qcom: qmp-pcie: Fix X1E80100 PCIe Gen4 PHY initialisation
+74
-9
+1
-1
drivers/phy/freescale/phy-fsl-imx8mq-usb.c
+1
-1
drivers/phy/freescale/phy-fsl-imx8mq-usb.c
···
176
176
imx_phy->comp_dis_tune =
177
177
phy_comp_dis_tune_from_property(imx_phy->comp_dis_tune);
178
178
179
-
if (device_property_read_u32(dev, "fsl,pcs-tx-deemph-3p5db-attenuation-db",
179
+
if (device_property_read_u32(dev, "fsl,phy-pcs-tx-deemph-3p5db-attenuation-db",
180
180
&imx_phy->pcs_tx_deemph_3p5db))
181
181
imx_phy->pcs_tx_deemph_3p5db = PHY_TUNE_DEFAULT;
182
182
else
+16
-7
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+16
-7
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
···
1245
1245
static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl[] = {
1246
1246
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL, 0x01),
1247
1247
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1, 0x88),
1248
-
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x00),
1249
-
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x1f),
1248
+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x02),
1249
+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x0d),
1250
1250
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0, 0xd4),
1251
1251
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1, 0x12),
1252
1252
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2, 0xdb),
···
1263
1263
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
1264
1264
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
1265
1265
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
1266
+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_SUMMER_CAL_SPD_MODE, 0x5b),
1266
1267
};
1267
1268
1268
1269
static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_tx_tbl[] = {
···
1287
1286
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_1, 0x01),
1288
1287
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_2, 0x01),
1289
1288
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x45),
1290
-
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0b),
1289
+
QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0a, 1),
1290
+
QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0b, 2),
1291
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_VGA_CAL_CNTRL1, 0x00),
1291
1292
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d),
1292
1293
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
1293
1294
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c),
1294
1295
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20),
1295
-
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1296
+
QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x3a, 1),
1297
+
QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38, 2),
1296
1298
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x39),
1297
1299
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0x14),
1298
1300
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0xb3),
···
1311
1307
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x4b),
1312
1308
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76),
1313
1309
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff),
1310
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_TX_ADPT_CTRL, 0x10),
1314
1311
};
1315
1312
1316
1313
static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_pcs_tbl[] = {
···
1319
1314
QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_RX_SIGDET_LVL, 0xcc),
1320
1315
QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG4, 0x00),
1321
1316
QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG5, 0x22),
1317
+
QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG1, 0x04),
1318
+
QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG2, 0x02),
1322
1319
};
1323
1320
1324
1321
static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
···
1331
1324
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN, 0x2e),
1332
1325
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1, 0x03),
1333
1326
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG3, 0x28),
1327
+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_RXEQEVAL_TIME, 0x27),
1328
+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_RXEQEVAL_TIME, 0x27),
1334
1329
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG, 0xc0),
1335
1330
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2, 0x1d),
1336
-
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5, 0x0f),
1337
-
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_FOM_EQ_CONFIG5, 0xf2),
1338
-
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5, 0xf2),
1331
+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5, 0x18),
1332
+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_FOM_EQ_CONFIG5, 0x7a),
1333
+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5, 0x8a),
1339
1334
};
1340
1335
1341
1336
static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = {
+1
-1
drivers/phy/samsung/phy-exynos5-usbdrd.c
+1
-1
drivers/phy/samsung/phy-exynos5-usbdrd.c
+56
drivers/phy/xilinx/phy-zynqmp.c
+56
drivers/phy/xilinx/phy-zynqmp.c
···
160
160
/* Timeout values */
161
161
#define TIMEOUT_US 1000
162
162
163
+
/* Lane 0/1/2/3 offset */
164
+
#define DIG_8(n) ((0x4000 * (n)) + 0x1074)
165
+
#define ILL13(n) ((0x4000 * (n)) + 0x1994)
166
+
#define DIG_10(n) ((0x4000 * (n)) + 0x107c)
167
+
#define RST_DLY(n) ((0x4000 * (n)) + 0x19a4)
168
+
#define BYP_15(n) ((0x4000 * (n)) + 0x1038)
169
+
#define BYP_12(n) ((0x4000 * (n)) + 0x102c)
170
+
#define MISC3(n) ((0x4000 * (n)) + 0x19ac)
171
+
#define EQ11(n) ((0x4000 * (n)) + 0x1978)
172
+
173
+
static u32 save_reg_address[] = {
174
+
/* Lane 0/1/2/3 Register */
175
+
DIG_8(0), ILL13(0), DIG_10(0), RST_DLY(0), BYP_15(0), BYP_12(0), MISC3(0), EQ11(0),
176
+
DIG_8(1), ILL13(1), DIG_10(1), RST_DLY(1), BYP_15(1), BYP_12(1), MISC3(1), EQ11(1),
177
+
DIG_8(2), ILL13(2), DIG_10(2), RST_DLY(2), BYP_15(2), BYP_12(2), MISC3(2), EQ11(2),
178
+
DIG_8(3), ILL13(3), DIG_10(3), RST_DLY(3), BYP_15(3), BYP_12(3), MISC3(3), EQ11(3),
179
+
};
180
+
163
181
struct xpsgtr_dev;
164
182
165
183
/**
···
227
209
* @tx_term_fix: fix for GT issue
228
210
* @saved_icm_cfg0: stored value of ICM CFG0 register
229
211
* @saved_icm_cfg1: stored value of ICM CFG1 register
212
+
* @saved_regs: registers to be saved/restored during suspend/resume
230
213
*/
231
214
struct xpsgtr_dev {
232
215
struct device *dev;
···
240
221
bool tx_term_fix;
241
222
unsigned int saved_icm_cfg0;
242
223
unsigned int saved_icm_cfg1;
224
+
u32 *saved_regs;
243
225
};
244
226
245
227
/*
···
312
292
+ gtr_phy->lane * PHY_REG_OFFSET + reg;
313
293
314
294
writel((readl(addr) & ~clr) | set, addr);
295
+
}
296
+
297
+
/**
298
+
* xpsgtr_save_lane_regs - Saves registers on suspend
299
+
* @gtr_dev: pointer to phy controller context structure
300
+
*/
301
+
static void xpsgtr_save_lane_regs(struct xpsgtr_dev *gtr_dev)
302
+
{
303
+
int i;
304
+
305
+
for (i = 0; i < ARRAY_SIZE(save_reg_address); i++)
306
+
gtr_dev->saved_regs[i] = xpsgtr_read(gtr_dev,
307
+
save_reg_address[i]);
308
+
}
309
+
310
+
/**
311
+
* xpsgtr_restore_lane_regs - Restores registers on resume
312
+
* @gtr_dev: pointer to phy controller context structure
313
+
*/
314
+
static void xpsgtr_restore_lane_regs(struct xpsgtr_dev *gtr_dev)
315
+
{
316
+
int i;
317
+
318
+
for (i = 0; i < ARRAY_SIZE(save_reg_address); i++)
319
+
xpsgtr_write(gtr_dev, save_reg_address[i],
320
+
gtr_dev->saved_regs[i]);
315
321
}
316
322
317
323
/*
···
883
837
gtr_dev->saved_icm_cfg0 = xpsgtr_read(gtr_dev, ICM_CFG0);
884
838
gtr_dev->saved_icm_cfg1 = xpsgtr_read(gtr_dev, ICM_CFG1);
885
839
840
+
xpsgtr_save_lane_regs(gtr_dev);
841
+
886
842
return 0;
887
843
}
888
844
···
894
846
unsigned int icm_cfg0, icm_cfg1;
895
847
unsigned int i;
896
848
bool skip_phy_init;
849
+
850
+
xpsgtr_restore_lane_regs(gtr_dev);
897
851
898
852
icm_cfg0 = xpsgtr_read(gtr_dev, ICM_CFG0);
899
853
icm_cfg1 = xpsgtr_read(gtr_dev, ICM_CFG1);
···
1043
993
pm_runtime_disable(gtr_dev->dev);
1044
994
return ret;
1045
995
}
996
+
997
+
gtr_dev->saved_regs = devm_kmalloc(gtr_dev->dev,
998
+
sizeof(save_reg_address),
999
+
GFP_KERNEL);
1000
+
if (!gtr_dev->saved_regs)
1001
+
return -ENOMEM;
1046
1002
1047
1003
return 0;
1048
1004
}