Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Documentation/gpu: Add an explanation about the DCN pipeline
In the DCN code, we constantly talk about hardware pipeline, pipeline,
or even just pipes, which is a concept that is not obvious to everyone.
For this reason, this commit expands the DCN overview explanation by
adding a new section that describes what a pipeline is from the DCN
perspective.
Changes since V1:
- Rewrite the first paragraph that describes AMD hardware pipeline.
Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Cc: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Cc: Hersen Wu <hersenxs.wu@amd.com>
Cc: Alex Hung <alex.hung@amd.com>
Cc: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Cc: Leo Li <sunpeng.li@amd.com>
Cc: Simon Ser <contact@emersion.fr>
Cc: Pekka Paalanen <pekka.paalanen@collabora.com>
Cc: Sean Paul <seanpaul@chromium.org>
Cc: Mark Yacoub <markyacoub@chromium.org>
Cc: Pierre-Loup <pgriffais@valvesoftware.com>
Cc: Michel Dänzer <michel.daenzer@mailbox.org>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Rodrigo Siqueira
and committed by
Alex Deucher
330d6da3
9d9b217d
+2079
+59
Documentation/gpu/amdgpu/display/dcn-overview.rst
+59
Documentation/gpu/amdgpu/display/dcn-overview.rst
···
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also apply a regamma function to introduce the gamma removed earlier back.
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Eventually, we output data in integer format at DIO.
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AMD Hardware Pipeline
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---------------------
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When discussing graphics on Linux, the **pipeline** term can sometimes be
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overloaded with multiple meanings, so it is important to define what we mean
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when we say **pipeline**. In the DCN driver, we use the term **hardware
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pipeline** or **pipeline** or just **pipe** as an abstraction to indicate a
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sequence of DCN blocks instantiated to address some specific configuration. DC
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core treats DCN blocks as individual resources, meaning we can build a pipeline
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by taking resources for all individual hardware blocks to compose one pipeline.
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In actuality, we can't connect an arbitrary block from one pipe to a block from
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another pipe; they are routed linearly, except for DSC, which can be
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arbitrarily assigned as needed. We have this pipeline concept for trying to
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optimize bandwidth utilization.
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.. kernel-figure:: pipeline_4k_no_split.svg
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Additionally, let's take a look at parts of the DTN log (see
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'Documentation/gpu/amdgpu/display/dc-debug.rst' for more information) since
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this log can help us to see part of this pipeline behavior in real-time::
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HUBP: format addr_hi width height ...
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[ 0]: 8h 81h 3840 2160
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[ 1]: 0h 0h 0 0
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[ 2]: 0h 0h 0 0
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[ 3]: 0h 0h 0 0
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[ 4]: 0h 0h 0 0
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...
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MPCC: OPP DPP ...
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[ 0]: 0h 0h ...
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The first thing to notice from the diagram and DTN log it is the fact that we
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have different clock domains for each part of the DCN blocks. In this example,
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we have just a single **pipeline** where the data flows from DCHUB to DIO, as
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we intuitively expect. Nonetheless, DCN is flexible, as mentioned before, and
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we can split this single pipe differently, as described in the below diagram:
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.. kernel-figure:: pipeline_4k_split.svg
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Now, if we inspect the DTN log again we can see some interesting changes::
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HUBP: format addr_hi width height ...
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[ 0]: 8h 81h 1920 2160 ...
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...
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[ 4]: 0h 0h 0 0 ...
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[ 5]: 8h 81h 1920 2160 ...
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...
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MPCC: OPP DPP ...
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[ 0]: 0h 0h ...
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[ 5]: 0h 5h ...
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From the above example, we now split the display pipeline into two vertical
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parts of 1920x2160 (i.e., 3440x2160), and as a result, we could reduce the
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clock frequency in the DPP part. This is not only useful for saving power but
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also to better handle the required throughput. The idea to keep in mind here is
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that the pipe configuration can vary a lot according to the display
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configuration, and it is the DML's responsibility to set up all required
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configuration parameters for multiple scenarios supported by our hardware.
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Global Sync
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-----------
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+958
Documentation/gpu/amdgpu/display/pipeline_4k_no_split.svg
+958
Documentation/gpu/amdgpu/display/pipeline_4k_no_split.svg
···
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