tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

drm/xe: Remove unused "mmio_ext" code

The "mmio_ext" and 'REG_EXT" code is currently unused on any existing
platform. Going forward, this also isn't the design we want to use for
any future platforms/features either, so we should just go ahead and
remove the dead code to avoid confusion.

mmio_ext was originally added in an attempt to hack around the early
(mis)design of the Xe driver, which used xe_gt as the target for all
register MMIO access, even those completely unrelated to the GT subunit
of the hardware. With the introduction of commit 34953ee349dd ("drm/xe:
Create dedicated xe_mmio structure") and its follow-up patches, that
misdesign has been corrected and access to register MMIO regions
specific to hardware units is now done through xe_mmio structures which
encapsulate an iomap, region size, and some other metadata.

Although all of the registers used by the driver today happen to fall
within one specific PCI BAR region, and thus re-use a single device-wide
iomap, there's no requirement that this stay true for future platforms
or features. I.e., if a future platform adds a new 'foo' hardware unit
that exists at a different area in the BAR, or even in a completely
different BAR, then that would be handled by doing a separate iomap of
that unit's register region and wrapping it in its own 'struct xe_mmio
foo_regs' structure. The pointer to the new 'foo_regs' could be placed
within the xe_device, xe_tile, xe_gt, etc., according to where the new
hardware unit falls within the current hardware hierarchy.

This effectively reverts the following commits, although parts of these
commits had already vanished or changed with the earlier xe_mmio
refactor work:

- commit 399a13323f0d ("drm/xe: add 28-bit address support in struct
xe_reg")
- commit fdef72e02e20 ("drm/xe: add a flag to bypass multi-tile config
from MTCFG reg")
- commit 866b2b176434 ("drm/xe: add MMIO extension support flags")
- commit ef29b390c734 ("drm/xe: map MMIO BAR according to the num of
tiles in device desc")
- commit a4e2f3a299ea ("drm/xe: refactor xe_mmio_probe_tiles to support
MMIO extension")

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Koby Elbaz <kelbaz@habana.ai>
Acked-by: Maciej Patelczyk <maciej.patelczyk@intel.com>
Reviewed-by: Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Stuart Summers <stuart.summers@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250106234312.2986065-2-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

Matt Roper 3318ef98 d160dc6f

+1 -70
+1 -15
drivers/gpu/drm/xe/regs/xe_reg_defs.h
··· 21 21 union { 22 22 struct { 23 23 /** @addr: address */ 24 - u32 addr:28; 24 + u32 addr:22; 25 25 /** 26 26 * @masked: register is "masked", with upper 16bits used 27 27 * to identify the bits that are updated on the lower ··· 41 41 * @vf: register is accessible from the Virtual Function. 42 42 */ 43 43 u32 vf:1; 44 - /** 45 - * @ext: access MMIO extension space for current register. 46 - */ 47 - u32 ext:1; 48 44 }; 49 45 /** @raw: Raw value with both address and options */ 50 46 u32 raw; ··· 106 110 * options. 107 111 */ 108 112 #define XE_REG(r_, ...) ((const struct xe_reg)XE_REG_INITIALIZER(r_, ##__VA_ARGS__)) 109 - 110 - /** 111 - * XE_REG_EXT - Create a struct xe_reg from extension offset and additional 112 - * flags 113 - * @r_: Register extension offset 114 - * @...: Additional options like access mode. See struct xe_reg for available 115 - * options. 116 - */ 117 - #define XE_REG_EXT(r_, ...) \ 118 - ((const struct xe_reg)XE_REG_INITIALIZER(r_, ##__VA_ARGS__, .ext = 1)) 119 113 120 114 /** 121 115 * XE_REG_MCR - Create a struct xe_reg_mcr from offset and additional flags
-11
drivers/gpu/drm/xe/xe_device_types.h
··· 186 186 */ 187 187 struct xe_mmio mmio; 188 188 189 - /** 190 - * @mmio_ext: MMIO-extension info for a tile. 191 - * 192 - * Each tile has its own additional 256MB (28-bit) MMIO-extension space. 193 - */ 194 - struct xe_mmio mmio_ext; 195 - 196 189 /** @mem: memory management info for tile */ 197 190 struct { 198 191 /** ··· 256 263 const char *graphics_name; 257 264 /** @info.media_name: media IP name */ 258 265 const char *media_name; 259 - /** @info.tile_mmio_ext_size: size of MMIO extension space, per-tile */ 260 - u32 tile_mmio_ext_size; 261 266 /** @info.graphics_verx100: graphics IP version */ 262 267 u32 graphics_verx100; 263 268 /** @info.media_verx100: media IP version */ ··· 305 314 u8 has_heci_gscfi:1; 306 315 /** @info.has_llc: Device has a shared CPU+GPU last level cache */ 307 316 u8 has_llc:1; 308 - /** @info.has_mmio_ext: Device has extra MMIO address range */ 309 - u8 has_mmio_ext:1; 310 317 /** @info.has_range_tlb_invalidation: Has range based TLB invalidations */ 311 318 u8 has_range_tlb_invalidation:1; 312 319 /** @info.has_sriov: Supports SR-IOV */
-39
drivers/gpu/drm/xe/xe_mmio.c
··· 103 103 } 104 104 } 105 105 106 - /* 107 - * On top of all the multi-tile MMIO space there can be a platform-dependent 108 - * extension for each tile, resulting in a layout like below: 109 - * 110 - * .----------------------. <- ext_base + tile_count * tile_mmio_ext_size 111 - * | .... | 112 - * |----------------------| <- ext_base + 2 * tile_mmio_ext_size 113 - * | tile1->mmio_ext.regs | 114 - * |----------------------| <- ext_base + 1 * tile_mmio_ext_size 115 - * | tile0->mmio_ext.regs | 116 - * |======================| <- ext_base = tile_count * tile_mmio_size 117 - * | | 118 - * | mmio.regs | 119 - * | | 120 - * '----------------------' <- 0MB 121 - * 122 - * Set up the tile[]->mmio_ext pointers/sizes. 123 - */ 124 - static void mmio_extension_setup(struct xe_device *xe, size_t tile_mmio_size, 125 - size_t tile_mmio_ext_size) 126 - { 127 - struct xe_tile *tile; 128 - void __iomem *regs; 129 - u8 id; 130 - 131 - if (!xe->info.has_mmio_ext) 132 - return; 133 - 134 - regs = xe->mmio.regs + tile_mmio_size * xe->info.tile_count; 135 - for_each_tile(tile, xe, id) { 136 - tile->mmio_ext.regs_size = tile_mmio_ext_size; 137 - tile->mmio_ext.regs = regs; 138 - tile->mmio_ext.tile = tile; 139 - regs += tile_mmio_ext_size; 140 - } 141 - } 142 - 143 106 int xe_mmio_probe_tiles(struct xe_device *xe) 144 107 { 145 108 size_t tile_mmio_size = SZ_16M; 146 - size_t tile_mmio_ext_size = xe->info.tile_mmio_ext_size; 147 109 148 110 mmio_multi_tile_setup(xe, tile_mmio_size); 149 - mmio_extension_setup(xe, tile_mmio_size, tile_mmio_ext_size); 150 111 151 112 return devm_add_action_or_reset(xe->drm.dev, tiles_fini, xe); 152 113 }
-3
drivers/gpu/drm/xe/xe_pci.c
··· 61 61 u8 has_heci_gscfi:1; 62 62 u8 has_heci_cscfi:1; 63 63 u8 has_llc:1; 64 - u8 has_mmio_ext:1; 65 64 u8 has_sriov:1; 66 65 u8 skip_guc_pc:1; 67 66 u8 skip_mtcfg:1; ··· 616 617 xe->info.has_heci_gscfi = desc->has_heci_gscfi; 617 618 xe->info.has_heci_cscfi = desc->has_heci_cscfi; 618 619 xe->info.has_llc = desc->has_llc; 619 - xe->info.has_mmio_ext = desc->has_mmio_ext; 620 620 xe->info.has_sriov = desc->has_sriov; 621 621 xe->info.skip_guc_pc = desc->skip_guc_pc; 622 622 xe->info.skip_mtcfg = desc->skip_mtcfg; ··· 675 677 676 678 xe->info.graphics_name = graphics_desc->name; 677 679 xe->info.media_name = media_desc ? media_desc->name : "none"; 678 - xe->info.tile_mmio_ext_size = graphics_desc->tile_mmio_ext_size; 679 680 680 681 xe->info.dma_mask_size = graphics_desc->dma_mask_size; 681 682 xe->info.vram_flags = graphics_desc->vram_flags;
-2
drivers/gpu/drm/xe/xe_pci_types.h
··· 20 20 21 21 u64 hw_engine_mask; /* hardware engines provided by graphics IP */ 22 22 23 - u32 tile_mmio_ext_size; /* size of MMIO extension space, per-tile */ 24 - 25 23 u8 max_remote_tiles:2; 26 24 27 25 u8 has_asid:1;