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accel/amdxdna: Enable hardware context priority

Newer firmware supports hardware context priority. Set the priority based
on application input.

Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org>
Signed-off-by: Lizhi Hou <lizhi.hou@amd.com>
Link: https://patch.msgid.link/20251217171719.2139025-1-lizhi.hou@amd.com

Lizhi Hou 33207079 7818618a

+35 -1
+22 -1
drivers/accel/amdxdna/aie2_message.c
··· 205 205 206 206 return ret; 207 207 } 208 + 209 + static u32 aie2_get_context_priority(struct amdxdna_dev_hdl *ndev, 210 + struct amdxdna_hwctx *hwctx) 211 + { 212 + if (!AIE2_FEATURE_ON(ndev, AIE2_PREEMPT)) 213 + return PRIORITY_HIGH; 214 + 215 + switch (hwctx->qos.priority) { 216 + case AMDXDNA_QOS_REALTIME_PRIORITY: 217 + return PRIORITY_REALTIME; 218 + case AMDXDNA_QOS_HIGH_PRIORITY: 219 + return PRIORITY_HIGH; 220 + case AMDXDNA_QOS_NORMAL_PRIORITY: 221 + return PRIORITY_NORMAL; 222 + case AMDXDNA_QOS_LOW_PRIORITY: 223 + return PRIORITY_LOW; 224 + default: 225 + return PRIORITY_HIGH; 226 + } 227 + } 228 + 208 229 int aie2_create_context(struct amdxdna_dev_hdl *ndev, struct amdxdna_hwctx *hwctx) 209 230 { 210 231 DECLARE_AIE2_MSG(create_ctx, MSG_OP_CREATE_CONTEXT); ··· 242 221 req.num_unused_col = hwctx->num_unused_col; 243 222 req.num_cq_pairs_requested = 1; 244 223 req.pasid = hwctx->client->pasid; 245 - req.context_priority = 2; 224 + req.context_priority = aie2_get_context_priority(ndev, hwctx); 246 225 247 226 ret = aie2_send_mgmt_msg_wait(ndev, &msg); 248 227 if (ret)
+5
drivers/accel/amdxdna/aie2_msg_priv.h
··· 108 108 struct cq_info i2x_q; 109 109 }; 110 110 111 + #define PRIORITY_REALTIME 1 112 + #define PRIORITY_HIGH 2 113 + #define PRIORITY_NORMAL 3 114 + #define PRIORITY_LOW 4 115 + 111 116 struct create_ctx_req { 112 117 __u32 aie_type; 113 118 __u8 start_col;
+8
include/uapi/drm/amdxdna_accel.h
··· 19 19 #define AMDXDNA_INVALID_BO_HANDLE 0 20 20 #define AMDXDNA_INVALID_FENCE_HANDLE 0 21 21 22 + /* 23 + * Define hardware context priority 24 + */ 25 + #define AMDXDNA_QOS_REALTIME_PRIORITY 0x100 26 + #define AMDXDNA_QOS_HIGH_PRIORITY 0x180 27 + #define AMDXDNA_QOS_NORMAL_PRIORITY 0x200 28 + #define AMDXDNA_QOS_LOW_PRIORITY 0x280 29 + 22 30 enum amdxdna_device_type { 23 31 AMDXDNA_DEV_TYPE_UNKNOWN = -1, 24 32 AMDXDNA_DEV_TYPE_KMQ,