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net: liquidio: Remove unused cn23xx_dump_pf_initialized_regs

cn23xx_dump_pf_initialized_regs() was added in 2016's commit
72c0091293c0 ("liquidio: CN23XX device init and sriov config")

but hasn't been used.

Remove it.

Signed-off-by: Dr. David Alan Gilbert <linux@treblig.org>
Reviewed-by: Simon Horman <horms@kernel.org>
Link: https://patch.msgid.link/20241009003841.254853-1-linux@treblig.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

authored by

Dr. David Alan Gilbert and committed by
Jakub Kicinski 3325964e 652c5017

-171
-169
drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c
··· 36 36 */ 37 37 #define CN23XX_INPUT_JABBER 64600 38 38 39 - void cn23xx_dump_pf_initialized_regs(struct octeon_device *oct) 40 - { 41 - int i = 0; 42 - u32 regval = 0; 43 - struct octeon_cn23xx_pf *cn23xx = (struct octeon_cn23xx_pf *)oct->chip; 44 - 45 - /*In cn23xx_soft_reset*/ 46 - dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%llx\n", 47 - "CN23XX_WIN_WR_MASK_REG", CVM_CAST64(CN23XX_WIN_WR_MASK_REG), 48 - CVM_CAST64(octeon_read_csr64(oct, CN23XX_WIN_WR_MASK_REG))); 49 - dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n", 50 - "CN23XX_SLI_SCRATCH1", CVM_CAST64(CN23XX_SLI_SCRATCH1), 51 - CVM_CAST64(octeon_read_csr64(oct, CN23XX_SLI_SCRATCH1))); 52 - dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n", 53 - "CN23XX_RST_SOFT_RST", CN23XX_RST_SOFT_RST, 54 - lio_pci_readq(oct, CN23XX_RST_SOFT_RST)); 55 - 56 - /*In cn23xx_set_dpi_regs*/ 57 - dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n", 58 - "CN23XX_DPI_DMA_CONTROL", CN23XX_DPI_DMA_CONTROL, 59 - lio_pci_readq(oct, CN23XX_DPI_DMA_CONTROL)); 60 - 61 - for (i = 0; i < 6; i++) { 62 - dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n", 63 - "CN23XX_DPI_DMA_ENG_ENB", i, 64 - CN23XX_DPI_DMA_ENG_ENB(i), 65 - lio_pci_readq(oct, CN23XX_DPI_DMA_ENG_ENB(i))); 66 - dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n", 67 - "CN23XX_DPI_DMA_ENG_BUF", i, 68 - CN23XX_DPI_DMA_ENG_BUF(i), 69 - lio_pci_readq(oct, CN23XX_DPI_DMA_ENG_BUF(i))); 70 - } 71 - 72 - dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n", "CN23XX_DPI_CTL", 73 - CN23XX_DPI_CTL, lio_pci_readq(oct, CN23XX_DPI_CTL)); 74 - 75 - /*In cn23xx_setup_pcie_mps and cn23xx_setup_pcie_mrrs */ 76 - pci_read_config_dword(oct->pci_dev, CN23XX_CONFIG_PCIE_DEVCTL, &regval); 77 - dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n", 78 - "CN23XX_CONFIG_PCIE_DEVCTL", 79 - CVM_CAST64(CN23XX_CONFIG_PCIE_DEVCTL), CVM_CAST64(regval)); 80 - 81 - dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n", 82 - "CN23XX_DPI_SLI_PRTX_CFG", oct->pcie_port, 83 - CN23XX_DPI_SLI_PRTX_CFG(oct->pcie_port), 84 - lio_pci_readq(oct, CN23XX_DPI_SLI_PRTX_CFG(oct->pcie_port))); 85 - 86 - /*In cn23xx_specific_regs_setup */ 87 - dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n", 88 - "CN23XX_SLI_S2M_PORTX_CTL", oct->pcie_port, 89 - CVM_CAST64(CN23XX_SLI_S2M_PORTX_CTL(oct->pcie_port)), 90 - CVM_CAST64(octeon_read_csr64( 91 - oct, CN23XX_SLI_S2M_PORTX_CTL(oct->pcie_port)))); 92 - 93 - dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n", 94 - "CN23XX_SLI_RING_RST", CVM_CAST64(CN23XX_SLI_PKT_IOQ_RING_RST), 95 - (u64)octeon_read_csr64(oct, CN23XX_SLI_PKT_IOQ_RING_RST)); 96 - 97 - /*In cn23xx_setup_global_mac_regs*/ 98 - for (i = 0; i < CN23XX_MAX_MACS; i++) { 99 - dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n", 100 - "CN23XX_SLI_PKT_MAC_RINFO64", i, 101 - CVM_CAST64(CN23XX_SLI_PKT_MAC_RINFO64(i, oct->pf_num)), 102 - CVM_CAST64(octeon_read_csr64 103 - (oct, CN23XX_SLI_PKT_MAC_RINFO64 104 - (i, oct->pf_num)))); 105 - } 106 - 107 - /*In cn23xx_setup_global_input_regs*/ 108 - for (i = 0; i < CN23XX_MAX_INPUT_QUEUES; i++) { 109 - dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n", 110 - "CN23XX_SLI_IQ_PKT_CONTROL64", i, 111 - CVM_CAST64(CN23XX_SLI_IQ_PKT_CONTROL64(i)), 112 - CVM_CAST64(octeon_read_csr64 113 - (oct, CN23XX_SLI_IQ_PKT_CONTROL64(i)))); 114 - } 115 - 116 - /*In cn23xx_setup_global_output_regs*/ 117 - dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n", 118 - "CN23XX_SLI_OQ_WMARK", CVM_CAST64(CN23XX_SLI_OQ_WMARK), 119 - CVM_CAST64(octeon_read_csr64(oct, CN23XX_SLI_OQ_WMARK))); 120 - 121 - for (i = 0; i < CN23XX_MAX_OUTPUT_QUEUES; i++) { 122 - dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n", 123 - "CN23XX_SLI_OQ_PKT_CONTROL", i, 124 - CVM_CAST64(CN23XX_SLI_OQ_PKT_CONTROL(i)), 125 - CVM_CAST64(octeon_read_csr( 126 - oct, CN23XX_SLI_OQ_PKT_CONTROL(i)))); 127 - dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n", 128 - "CN23XX_SLI_OQ_PKT_INT_LEVELS", i, 129 - CVM_CAST64(CN23XX_SLI_OQ_PKT_INT_LEVELS(i)), 130 - CVM_CAST64(octeon_read_csr64( 131 - oct, CN23XX_SLI_OQ_PKT_INT_LEVELS(i)))); 132 - } 133 - 134 - /*In cn23xx_enable_interrupt and cn23xx_disable_interrupt*/ 135 - dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n", 136 - "cn23xx->intr_enb_reg64", 137 - CVM_CAST64((long)(cn23xx->intr_enb_reg64)), 138 - CVM_CAST64(readq(cn23xx->intr_enb_reg64))); 139 - 140 - dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n", 141 - "cn23xx->intr_sum_reg64", 142 - CVM_CAST64((long)(cn23xx->intr_sum_reg64)), 143 - CVM_CAST64(readq(cn23xx->intr_sum_reg64))); 144 - 145 - /*In cn23xx_setup_iq_regs*/ 146 - for (i = 0; i < CN23XX_MAX_INPUT_QUEUES; i++) { 147 - dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n", 148 - "CN23XX_SLI_IQ_BASE_ADDR64", i, 149 - CVM_CAST64(CN23XX_SLI_IQ_BASE_ADDR64(i)), 150 - CVM_CAST64(octeon_read_csr64( 151 - oct, CN23XX_SLI_IQ_BASE_ADDR64(i)))); 152 - dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n", 153 - "CN23XX_SLI_IQ_SIZE", i, 154 - CVM_CAST64(CN23XX_SLI_IQ_SIZE(i)), 155 - CVM_CAST64(octeon_read_csr 156 - (oct, CN23XX_SLI_IQ_SIZE(i)))); 157 - dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n", 158 - "CN23XX_SLI_IQ_DOORBELL", i, 159 - CVM_CAST64(CN23XX_SLI_IQ_DOORBELL(i)), 160 - CVM_CAST64(octeon_read_csr64( 161 - oct, CN23XX_SLI_IQ_DOORBELL(i)))); 162 - dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n", 163 - "CN23XX_SLI_IQ_INSTR_COUNT64", i, 164 - CVM_CAST64(CN23XX_SLI_IQ_INSTR_COUNT64(i)), 165 - CVM_CAST64(octeon_read_csr64( 166 - oct, CN23XX_SLI_IQ_INSTR_COUNT64(i)))); 167 - } 168 - 169 - /*In cn23xx_setup_oq_regs*/ 170 - for (i = 0; i < CN23XX_MAX_OUTPUT_QUEUES; i++) { 171 - dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n", 172 - "CN23XX_SLI_OQ_BASE_ADDR64", i, 173 - CVM_CAST64(CN23XX_SLI_OQ_BASE_ADDR64(i)), 174 - CVM_CAST64(octeon_read_csr64( 175 - oct, CN23XX_SLI_OQ_BASE_ADDR64(i)))); 176 - dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n", 177 - "CN23XX_SLI_OQ_SIZE", i, 178 - CVM_CAST64(CN23XX_SLI_OQ_SIZE(i)), 179 - CVM_CAST64(octeon_read_csr 180 - (oct, CN23XX_SLI_OQ_SIZE(i)))); 181 - dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n", 182 - "CN23XX_SLI_OQ_BUFF_INFO_SIZE", i, 183 - CVM_CAST64(CN23XX_SLI_OQ_BUFF_INFO_SIZE(i)), 184 - CVM_CAST64(octeon_read_csr( 185 - oct, CN23XX_SLI_OQ_BUFF_INFO_SIZE(i)))); 186 - dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n", 187 - "CN23XX_SLI_OQ_PKTS_SENT", i, 188 - CVM_CAST64(CN23XX_SLI_OQ_PKTS_SENT(i)), 189 - CVM_CAST64(octeon_read_csr64( 190 - oct, CN23XX_SLI_OQ_PKTS_SENT(i)))); 191 - dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n", 192 - "CN23XX_SLI_OQ_PKTS_CREDIT", i, 193 - CVM_CAST64(CN23XX_SLI_OQ_PKTS_CREDIT(i)), 194 - CVM_CAST64(octeon_read_csr64( 195 - oct, CN23XX_SLI_OQ_PKTS_CREDIT(i)))); 196 - } 197 - 198 - dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n", 199 - "CN23XX_SLI_PKT_TIME_INT", 200 - CVM_CAST64(CN23XX_SLI_PKT_TIME_INT), 201 - CVM_CAST64(octeon_read_csr64(oct, CN23XX_SLI_PKT_TIME_INT))); 202 - dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n", 203 - "CN23XX_SLI_PKT_CNT_INT", 204 - CVM_CAST64(CN23XX_SLI_PKT_CNT_INT), 205 - CVM_CAST64(octeon_read_csr64(oct, CN23XX_SLI_PKT_CNT_INT))); 206 - } 207 - 208 39 static int cn23xx_pf_soft_reset(struct octeon_device *oct) 209 40 { 210 41 octeon_write_csr64(oct, CN23XX_WIN_WR_MASK_REG, 0xFF);
-2
drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.h
··· 59 59 60 60 u32 cn23xx_pf_get_oq_ticks(struct octeon_device *oct, u32 time_intr_in_us); 61 61 62 - void cn23xx_dump_pf_initialized_regs(struct octeon_device *oct); 63 - 64 62 int cn23xx_sriov_config(struct octeon_device *oct); 65 63 66 64 int cn23xx_fw_loaded(struct octeon_device *oct);