Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/i915/ltphy: Enable SSC during port clock programming
We enable SSC when we program PORT_CLOCK_CTL register. We logically
determine if ssc is enabled or not while we calculate our state.
Bspec: 74492, 74667
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-12-suraj.kandpal@intel.com
+26
+26
drivers/gpu/drm/i915/display/intel_lt_phy.c
+26
drivers/gpu/drm/i915/display/intel_lt_phy.c
···
16
16
#include "intel_hdmi.h"
17
17
#include "intel_lt_phy.h"
18
18
#include "intel_lt_phy_regs.h"
19
+
#include "intel_panel.h"
19
20
#include "intel_psr.h"
20
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#include "intel_tc.h"
21
22
···
1110
1109
else
1111
1110
val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_MAXPCLK);
1112
1111
1112
+
/* DP2.0 10G and 20G rates enable MPLLA*/
1113
+
if (crtc_state->port_clock == 1000000 || crtc_state->port_clock == 2000000)
1114
+
val |= XELPDP_SSC_ENABLE_PLLA;
1115
+
else
1116
+
val |= crtc_state->dpll_hw_state.ltpll.ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
1117
+
1113
1118
intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
1114
1119
XELPDP_LANE1_PHY_CLOCK_SELECT | XELPDP_FORWARD_CLOCK_UNGATE |
1115
1120
XELPDP_DDI_CLOCK_SELECT_MASK(display) | XELPDP_SSC_ENABLE_PLLA |
···
1218
1211
return NULL;
1219
1212
}
1220
1213
1214
+
static bool
1215
+
intel_lt_phy_pll_is_ssc_enabled(struct intel_crtc_state *crtc_state,
1216
+
struct intel_encoder *encoder)
1217
+
{
1218
+
struct intel_display *display = to_intel_display(encoder);
1219
+
1220
+
if (intel_crtc_has_dp_encoder(crtc_state)) {
1221
+
if (intel_panel_use_ssc(display)) {
1222
+
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1223
+
1224
+
return (intel_dp->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5);
1225
+
}
1226
+
}
1227
+
1228
+
return false;
1229
+
}
1230
+
1221
1231
int
1222
1232
intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
1223
1233
struct intel_encoder *encoder)
···
1253
1229
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1254
1230
crtc_state->dpll_hw_state.ltpll.config[2] = 1;
1255
1231
}
1232
+
crtc_state->dpll_hw_state.ltpll.ssc_enabled =
1233
+
intel_lt_phy_pll_is_ssc_enabled(crtc_state, encoder);
1256
1234
return 0;
1257
1235
}
1258
1236
}