Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'spi-fix-v7.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
Pull spi fixes from Mark Brown:
"There are a couple of nasty issues fixed here in the axiado and
rockchip drivers. We've also got more of the fixes from Johan here,
this time for the two Cadence drivers, plus a couple of other similar
fixes from John and Felix"
* tag 'spi-fix-v7.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi:
spi: amlogic-spisg: initialize completion before requesting IRQ
spi: axiado: replace usleep_range() with udelay() in IRQ path
spi: cadence-quadspi: fix runtime pm and clock imbalance on unbind
spi: cadence-quadspi: fix unclocked access on unbind
spi: cadence-quadspi: fix clock imbalance on probe failure
spi: cadence-quadspi: fix runtime pm disable imbalance on probe failure
spi: cadence: fix clock imbalance on probe failure
spi: cadence: fix unclocked access on unbind
spi: rockchip: Drop unused and broken CR0 macros
spi: rockchip: Read ISR, not IMR, to detect cs-inactive IRQ
spi: rzv2h-rspi: Fix silent failure in clock setup error path
+36
-28
+1
-2
drivers/spi/spi-amlogic-spisg.c
+1
-2
drivers/spi/spi-amlogic-spisg.c
···
794
794
795
795
dma_set_max_seg_size(&pdev->dev, SPISG_BLOCK_MAX);
796
796
797
+
init_completion(&spisg->completion);
797
798
ret = devm_request_irq(&pdev->dev, irq, aml_spisg_irq, 0, NULL, spisg);
798
799
if (ret) {
799
800
dev_err(&pdev->dev, "irq request failed\n");
···
806
805
dev_err(&pdev->dev, "spi controller registration failed\n");
807
806
goto out_clk;
808
807
}
809
-
810
-
init_completion(&spisg->completion);
811
808
812
809
pm_runtime_put(&spisg->pdev->dev);
813
810
+1
-1
drivers/spi/spi-axiado.c
+1
-1
drivers/spi/spi-axiado.c
+18
-18
drivers/spi/spi-cadence-quadspi.c
+18
-18
drivers/spi/spi-cadence-quadspi.c
···
1860
1860
if (irq < 0)
1861
1861
return -ENXIO;
1862
1862
1863
-
ret = pm_runtime_set_active(dev);
1864
-
if (ret)
1865
-
return ret;
1866
-
1867
1863
ret = clk_bulk_prepare_enable(CLK_QSPI_NUM, cqspi->clks);
1868
1864
if (ret) {
1869
1865
dev_err(dev, "Cannot enable QSPI clocks.\n");
1870
-
goto disable_rpm;
1866
+
return ret;
1871
1867
}
1872
1868
1873
1869
/* Obtain QSPI reset control */
···
1958
1962
cqspi->sclk = 0;
1959
1963
1960
1964
if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) {
1961
-
pm_runtime_enable(dev);
1962
1965
pm_runtime_set_autosuspend_delay(dev, CQSPI_AUTOSUSPEND_TIMEOUT);
1963
1966
pm_runtime_use_autosuspend(dev);
1964
1967
pm_runtime_get_noresume(dev);
1968
+
pm_runtime_set_active(dev);
1969
+
pm_runtime_enable(dev);
1965
1970
}
1966
1971
1967
1972
host->num_chipselect = cqspi->num_chipselect;
···
1974
1977
ret = cqspi_request_mmap_dma(cqspi);
1975
1978
if (ret == -EPROBE_DEFER) {
1976
1979
dev_err_probe(&pdev->dev, ret, "Failed to request mmap DMA\n");
1977
-
goto disable_controller;
1980
+
goto disable_rpm;
1978
1981
}
1979
1982
}
1980
1983
···
1992
1995
release_dma_chan:
1993
1996
if (cqspi->rx_chan)
1994
1997
dma_release_channel(cqspi->rx_chan);
1995
-
disable_controller:
1998
+
disable_rpm:
1999
+
if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) {
2000
+
pm_runtime_disable(dev);
2001
+
pm_runtime_set_suspended(dev);
2002
+
pm_runtime_put_noidle(dev);
2003
+
pm_runtime_dont_use_autosuspend(dev);
2004
+
}
1996
2005
cqspi_controller_enable(cqspi, 0);
1997
2006
disable_clks:
1998
-
if (pm_runtime_get_sync(&pdev->dev) >= 0)
1999
-
clk_bulk_disable_unprepare(CLK_QSPI_NUM, cqspi->clks);
2000
-
disable_rpm:
2001
-
if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM)))
2002
-
pm_runtime_disable(dev);
2007
+
clk_bulk_disable_unprepare(CLK_QSPI_NUM, cqspi->clks);
2003
2008
2004
2009
return ret;
2005
2010
}
···
2025
2026
if (cqspi->rx_chan)
2026
2027
dma_release_channel(cqspi->rx_chan);
2027
2028
2028
-
cqspi_controller_enable(cqspi, 0);
2029
-
2030
-
2031
2029
if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM)))
2032
2030
ret = pm_runtime_get_sync(&pdev->dev);
2033
2031
2034
-
if (ret >= 0)
2032
+
if (ret >= 0) {
2033
+
cqspi_controller_enable(cqspi, 0);
2035
2034
clk_bulk_disable_unprepare(CLK_QSPI_NUM, cqspi->clks);
2035
+
}
2036
2036
2037
2037
if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) {
2038
-
pm_runtime_put_sync(&pdev->dev);
2039
2038
pm_runtime_disable(&pdev->dev);
2039
+
pm_runtime_set_suspended(&pdev->dev);
2040
+
pm_runtime_put_noidle(&pdev->dev);
2041
+
pm_runtime_dont_use_autosuspend(&pdev->dev);
2040
2042
}
2041
2043
}
2042
2044
+13
-2
drivers/spi/spi-cadence.c
+13
-2
drivers/spi/spi-cadence.c
···
741
741
/* Set to default valid value */
742
742
ctlr->max_speed_hz = xspi->clk_rate / 4;
743
743
xspi->speed_hz = ctlr->max_speed_hz;
744
-
pm_runtime_put_autosuspend(&pdev->dev);
745
744
} else {
746
745
ctlr->mode_bits |= SPI_NO_CS;
747
746
ctlr->target_abort = cdns_target_abort;
···
751
752
goto clk_dis_all;
752
753
}
753
754
755
+
if (!spi_controller_is_target(ctlr))
756
+
pm_runtime_put_autosuspend(&pdev->dev);
757
+
754
758
return ret;
755
759
756
760
clk_dis_all:
757
761
if (!spi_controller_is_target(ctlr)) {
758
762
pm_runtime_disable(&pdev->dev);
759
763
pm_runtime_set_suspended(&pdev->dev);
764
+
pm_runtime_put_noidle(&pdev->dev);
765
+
pm_runtime_dont_use_autosuspend(&pdev->dev);
760
766
}
761
767
remove_ctlr:
762
768
spi_controller_put(ctlr);
···
780
776
{
781
777
struct spi_controller *ctlr = platform_get_drvdata(pdev);
782
778
struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
779
+
int ret = 0;
780
+
781
+
if (!spi_controller_is_target(ctlr))
782
+
ret = pm_runtime_get_sync(&pdev->dev);
783
783
784
784
spi_controller_get(ctlr);
785
785
786
786
spi_unregister_controller(ctlr);
787
787
788
-
cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
788
+
if (ret >= 0)
789
+
cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
789
790
790
791
if (!spi_controller_is_target(ctlr)) {
791
792
pm_runtime_disable(&pdev->dev);
792
793
pm_runtime_set_suspended(&pdev->dev);
794
+
pm_runtime_put_noidle(&pdev->dev);
795
+
pm_runtime_dont_use_autosuspend(&pdev->dev);
793
796
}
794
797
795
798
spi_controller_put(ctlr);
+2
-4
drivers/spi/spi-rockchip.c
+2
-4
drivers/spi/spi-rockchip.c
···
98
98
#define CR0_FRF_MICROWIRE 0x2
99
99
100
100
#define CR0_XFM_OFFSET 18
101
-
#define CR0_XFM_MASK (0x03 << SPI_XFM_OFFSET)
102
101
#define CR0_XFM_TR 0x0
103
102
#define CR0_XFM_TO 0x1
104
103
#define CR0_XFM_RO 0x2
···
107
108
#define CR0_OPM_TARGET 0x1
108
109
109
110
#define CR0_SOI_OFFSET 23
110
-
111
-
#define CR0_MTM_OFFSET 0x21
112
111
113
112
/* Bit fields in SER, 2bit */
114
113
#define SER_MASK 0x3
···
354
357
struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
355
358
356
359
/* When int_cs_inactive comes, spi target abort */
357
-
if (rs->cs_inactive && readl_relaxed(rs->regs + ROCKCHIP_SPI_IMR) & INT_CS_INACTIVE) {
360
+
if (rs->cs_inactive &&
361
+
(readl_relaxed(rs->regs + ROCKCHIP_SPI_ISR) & INT_CS_INACTIVE)) {
358
362
ctlr->target_abort(ctlr);
359
363
writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
360
364
writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);