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drm/amd/display: Only use ODM2:1 policy for high pixel rate displays

We only gain a benefit of using the ODM2:1 dynamic policy if it allow us
to decrease DISPCLK to use the VMIN freq. If the display config can
already achieve VMIN DISPCLK freq without ODM2:1, don't apply the
policy.

This patch was reverted but that causes some IGT regressions. To
unblock, the patch is being applied again until IGT failures are
fixed.

Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>

authored by

Aurabindo Pillai and committed by
Alex Deucher 33e82119 b7588507

+2
+1
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
··· 1918 1918 context->stream_status[0].plane_count == 1 && 1919 1919 !dc_is_hdmi_signal(res_ctx->pipe_ctx[i].stream->signal) && 1920 1920 is_h_timing_divisible_by_2(res_ctx->pipe_ctx[i].stream) && 1921 + pipe->stream->timing.pix_clk_100hz * 100 > DCN3_2_VMIN_DISPCLK_HZ && 1921 1922 dc->debug.enable_single_display_2to1_odm_policy && 1922 1923 !vsr_odm_support) { //excluding 2to1 ODM combine on >= 5k vsr 1923 1924 pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_2to1;
+1
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
··· 40 40 #define DCN3_2_DCFCLK_DS_INIT_KHZ 10000 // Choose 10Mhz for init DCFCLK DS freq 41 41 #define SUBVP_HIGH_REFRESH_LIST_LEN 3 42 42 #define DCN3_2_MAX_SUBVP_PIXEL_RATE_MHZ 1800 43 + #define DCN3_2_VMIN_DISPCLK_HZ 717000000 43 44 44 45 #define TO_DCN32_RES_POOL(pool)\ 45 46 container_of(pool, struct dcn32_resource_pool, base)