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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/drzeus/mmc

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/drzeus/mmc:
sdhci-of: Fix the wrong accessor to HOSTVER register
mvsdio: fix config failure with some high speed SDHC cards
mvsdio: ignore high speed timing requests from the core
mmc/omap: Use disable_irq_nosync() from within irq handlers.
sdhci-of: Add fsl,esdhc as a valid compatible to bind against
mvsdio: allow automatic loading when modular
mxcmmc: Fix missing return value checking in DMA setup code.
mxcmmc : Reset the SDHC hardware if software timeout occurs.
omap_hsmmc: Trivial fix for a typo in comment
mxcmmc: decrease minimum frequency to make MMC cards work

+80 -15
+35
drivers/mmc/host/mvsdio.c
··· 64 64 unsigned int tmout; 65 65 int tmout_index; 66 66 67 + /* 68 + * Hardware weirdness. The FIFO_EMPTY bit of the HW_STATE 69 + * register is sometimes not set before a while when some 70 + * "unusual" data block sizes are used (such as with the SWITCH 71 + * command), even despite the fact that the XFER_DONE interrupt 72 + * was raised. And if another data transfer starts before 73 + * this bit comes to good sense (which eventually happens by 74 + * itself) then the new transfer simply fails with a timeout. 75 + */ 76 + if (!(mvsd_read(MVSD_HW_STATE) & (1 << 13))) { 77 + unsigned long t = jiffies + HZ; 78 + unsigned int hw_state, count = 0; 79 + do { 80 + if (time_after(jiffies, t)) { 81 + dev_warn(host->dev, "FIFO_EMPTY bit missing\n"); 82 + break; 83 + } 84 + hw_state = mvsd_read(MVSD_HW_STATE); 85 + count++; 86 + } while (!(hw_state & (1 << 13))); 87 + dev_dbg(host->dev, "*** wait for FIFO_EMPTY bit " 88 + "(hw=0x%04x, count=%d, jiffies=%ld)\n", 89 + hw_state, count, jiffies - (t - HZ)); 90 + } 91 + 67 92 /* If timeout=0 then maximum timeout index is used. */ 68 93 tmout = DIV_ROUND_UP(data->timeout_ns, host->ns_per_clk); 69 94 tmout += data->timeout_clks; ··· 645 620 if (ios->bus_width == MMC_BUS_WIDTH_4) 646 621 ctrl_reg |= MVSD_HOST_CTRL_DATA_WIDTH_4_BITS; 647 622 623 + /* 624 + * The HI_SPEED_EN bit is causing trouble with many (but not all) 625 + * high speed SD, SDHC and SDIO cards. Not enabling that bit 626 + * makes all cards work. So let's just ignore that bit for now 627 + * and revisit this issue if problems for not enabling this bit 628 + * are ever reported. 629 + */ 630 + #if 0 648 631 if (ios->timing == MMC_TIMING_MMC_HS || 649 632 ios->timing == MMC_TIMING_SD_HS) 650 633 ctrl_reg |= MVSD_HOST_CTRL_HI_SPEED_EN; 634 + #endif 651 635 652 636 host->ctrl = ctrl_reg; 653 637 mvsd_write(MVSD_HOST_CTRL, ctrl_reg); ··· 916 882 MODULE_AUTHOR("Maen Suleiman, Nicolas Pitre"); 917 883 MODULE_DESCRIPTION("Marvell MMC,SD,SDIO Host Controller driver"); 918 884 MODULE_LICENSE("GPL"); 885 + MODULE_ALIAS("platform:mvsdio");
+35 -12
drivers/mmc/host/mxcmmc.c
··· 140 140 struct work_struct datawork; 141 141 }; 142 142 143 + static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios); 144 + 143 145 static inline int mxcmci_use_dma(struct mxcmci_host *host) 144 146 { 145 147 return host->do_dma; ··· 162 160 writew(0xff, host->base + MMC_REG_RES_TO); 163 161 } 164 162 165 - static void mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data) 163 + static int mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data) 166 164 { 167 165 unsigned int nob = data->blocks; 168 166 unsigned int blksz = data->blksz; ··· 170 168 #ifdef HAS_DMA 171 169 struct scatterlist *sg; 172 170 int i; 171 + int ret; 173 172 #endif 174 173 if (data->flags & MMC_DATA_STREAM) 175 174 nob = 0xffff; ··· 186 183 for_each_sg(data->sg, sg, data->sg_len, i) { 187 184 if (sg->offset & 3 || sg->length & 3) { 188 185 host->do_dma = 0; 189 - return; 186 + return 0; 190 187 } 191 188 } 192 189 ··· 195 192 host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg, 196 193 data->sg_len, host->dma_dir); 197 194 198 - imx_dma_setup_sg(host->dma, data->sg, host->dma_nents, datasize, 199 - host->res->start + MMC_REG_BUFFER_ACCESS, 200 - DMA_MODE_READ); 195 + ret = imx_dma_setup_sg(host->dma, data->sg, host->dma_nents, 196 + datasize, 197 + host->res->start + MMC_REG_BUFFER_ACCESS, 198 + DMA_MODE_READ); 201 199 } else { 202 200 host->dma_dir = DMA_TO_DEVICE; 203 201 host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg, 204 202 data->sg_len, host->dma_dir); 205 203 206 - imx_dma_setup_sg(host->dma, data->sg, host->dma_nents, datasize, 207 - host->res->start + MMC_REG_BUFFER_ACCESS, 208 - DMA_MODE_WRITE); 204 + ret = imx_dma_setup_sg(host->dma, data->sg, host->dma_nents, 205 + datasize, 206 + host->res->start + MMC_REG_BUFFER_ACCESS, 207 + DMA_MODE_WRITE); 209 208 } 210 209 210 + if (ret) { 211 + dev_err(mmc_dev(host->mmc), "failed to setup DMA : %d\n", ret); 212 + return ret; 213 + } 211 214 wmb(); 212 215 213 216 imx_dma_enable(host->dma); 214 217 #endif /* HAS_DMA */ 218 + return 0; 215 219 } 216 220 217 221 static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_command *cmd, ··· 355 345 stat = readl(host->base + MMC_REG_STATUS); 356 346 if (stat & STATUS_ERR_MASK) 357 347 return stat; 358 - if (time_after(jiffies, timeout)) 348 + if (time_after(jiffies, timeout)) { 349 + mxcmci_softreset(host); 350 + mxcmci_set_clk_rate(host, host->clock); 359 351 return STATUS_TIME_OUT_READ; 352 + } 360 353 if (stat & mask) 361 354 return 0; 362 355 cpu_relax(); ··· 544 531 { 545 532 struct mxcmci_host *host = mmc_priv(mmc); 546 533 unsigned int cmdat = host->cmdat; 534 + int error; 547 535 548 536 WARN_ON(host->req != NULL); 549 537 ··· 554 540 host->do_dma = 1; 555 541 #endif 556 542 if (req->data) { 557 - mxcmci_setup_data(host, req->data); 543 + error = mxcmci_setup_data(host, req->data); 544 + if (error) { 545 + req->cmd->error = error; 546 + goto out; 547 + } 548 + 558 549 559 550 cmdat |= CMD_DAT_CONT_DATA_ENABLE; 560 551 ··· 567 548 cmdat |= CMD_DAT_CONT_WRITE; 568 549 } 569 550 570 - if (mxcmci_start_cmd(host, req->cmd, cmdat)) 551 + error = mxcmci_start_cmd(host, req->cmd, cmdat); 552 + out: 553 + if (error) 571 554 mxcmci_finish_request(host, req); 572 555 } 573 556 ··· 745 724 goto out_clk_put; 746 725 } 747 726 748 - mmc->f_min = clk_get_rate(host->clk) >> 7; 727 + mmc->f_min = clk_get_rate(host->clk) >> 16; 728 + if (mmc->f_min < 400000) 729 + mmc->f_min = 400000; 749 730 mmc->f_max = clk_get_rate(host->clk) >> 1; 750 731 751 732 /* recommended in data sheet */
+1 -1
drivers/mmc/host/omap.c
··· 822 822 del_timer(&host->cmd_abort_timer); 823 823 host->abort = 1; 824 824 OMAP_MMC_WRITE(host, IE, 0); 825 - disable_irq(host->irq); 825 + disable_irq_nosync(host->irq); 826 826 schedule_work(&host->cmd_abort_work); 827 827 return IRQ_HANDLED; 828 828 }
+1 -1
drivers/mmc/host/omap_hsmmc.c
··· 680 680 host->dma_ch = -1; 681 681 /* 682 682 * DMA Callback: run in interrupt context. 683 - * mutex_unlock will through a kernel warning if used. 683 + * mutex_unlock will throw a kernel warning if used. 684 684 */ 685 685 up(&host->sem); 686 686 }
+8 -1
drivers/mmc/host/sdhci-of.c
··· 55 55 56 56 static u16 esdhc_readw(struct sdhci_host *host, int reg) 57 57 { 58 - return in_be16(host->ioaddr + (reg ^ 0x2)); 58 + u16 ret; 59 + 60 + if (unlikely(reg == SDHCI_HOST_VERSION)) 61 + ret = in_be16(host->ioaddr + reg); 62 + else 63 + ret = in_be16(host->ioaddr + (reg ^ 0x2)); 64 + return ret; 59 65 } 60 66 61 67 static u8 esdhc_readb(struct sdhci_host *host, int reg) ··· 283 277 static const struct of_device_id sdhci_of_match[] = { 284 278 { .compatible = "fsl,mpc8379-esdhc", .data = &sdhci_esdhc, }, 285 279 { .compatible = "fsl,mpc8536-esdhc", .data = &sdhci_esdhc, }, 280 + { .compatible = "fsl,esdhc", .data = &sdhci_esdhc, }, 286 281 { .compatible = "generic-sdhci", }, 287 282 {}, 288 283 };