Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson:
"We didn't have a batch last week, so this one is slightly larger.
None of them are scary though, a handful of fixes for small DT pieces,
replacing properties with newer conventions.
Highlights:
- N900 fix for setting system revision
- onenand init fix to avoid filesystem corruption
- Clock fix for audio on Beaglebone-x15
- Fixes on shmobile to deal with CONFIG_DEBUG_RODATA (default y in 4.6)
+ misc smaller stuff"
* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
MAINTAINERS: Extend info, add wiki and ml for meson arch
MAINTAINERS: alpine: add a new maintainer and update the entry
ARM: at91/dt: fix typo in sama5d2 pinmux descriptions
ARM: OMAP2+: Fix onenand initialization to avoid filesystem corruption
Revert "regulator: tps65217: remove tps65217.dtsi file"
ARM: shmobile: Remove shmobile_boot_arg
ARM: shmobile: Move shmobile_smp_{mpidr, fn, arg}[] from .text to .bss
ARM: shmobile: r8a7779: Remove remainings of removed SCU boot setup code
ARM: shmobile: Move shmobile_scu_base from .text to .bss
ARM: OMAP2+: Fix omap_device for module reload on PM runtime forbid
ARM: OMAP2+: Improve omap_device error for driver writers
ARM: DTS: am57xx-beagle-x15: Select SYS_CLK2 for audio clocks
ARM: dts: am335x/am57xx: replace gpio-key,wakeup with wakeup-source property
ARM: OMAP2+: Set system_rev from ATAGS for n900
ARM: dts: orion5x: fix the missing mtd flash on linkstation lswtgl
ARM: dts: kirkwood: use unique machine name for ds112
ARM: dts: imx6: remove bogus interrupt-parent from CAAM node
+173
-105
-10
Documentation/devicetree/bindings/regulator/tps65217.txt
-10
Documentation/devicetree/bindings/regulator/tps65217.txt
···
26
26
ti,pmic-shutdown-controller;
27
27
28
28
regulators {
29
-
#address-cells = <1>;
30
-
#size-cells = <0>;
31
-
32
29
dcdc1_reg: dcdc1 {
33
-
reg = <0>;
34
30
regulator-min-microvolt = <900000>;
35
31
regulator-max-microvolt = <1800000>;
36
32
regulator-boot-on;
···
34
38
};
35
39
36
40
dcdc2_reg: dcdc2 {
37
-
reg = <1>;
38
41
regulator-min-microvolt = <900000>;
39
42
regulator-max-microvolt = <3300000>;
40
43
regulator-boot-on;
···
41
46
};
42
47
43
48
dcdc3_reg: dcc3 {
44
-
reg = <2>;
45
49
regulator-min-microvolt = <900000>;
46
50
regulator-max-microvolt = <1500000>;
47
51
regulator-boot-on;
···
48
54
};
49
55
50
56
ldo1_reg: ldo1 {
51
-
reg = <3>;
52
57
regulator-min-microvolt = <1000000>;
53
58
regulator-max-microvolt = <3300000>;
54
59
regulator-boot-on;
···
55
62
};
56
63
57
64
ldo2_reg: ldo2 {
58
-
reg = <4>;
59
65
regulator-min-microvolt = <900000>;
60
66
regulator-max-microvolt = <3300000>;
61
67
regulator-boot-on;
···
62
70
};
63
71
64
72
ldo3_reg: ldo3 {
65
-
reg = <5>;
66
73
regulator-min-microvolt = <1800000>;
67
74
regulator-max-microvolt = <3300000>;
68
75
regulator-boot-on;
···
69
78
};
70
79
71
80
ldo4_reg: ldo4 {
72
-
reg = <6>;
73
81
regulator-min-microvolt = <1800000>;
74
82
regulator-max-microvolt = <3300000>;
75
83
regulator-boot-on;
+10
-3
MAINTAINERS
+10
-3
MAINTAINERS
···
920
920
S: Maintained
921
921
F: drivers/clk/sunxi/
922
922
923
-
ARM/Amlogic MesonX SoC support
923
+
ARM/Amlogic Meson SoC support
924
924
M: Carlo Caione <carlo@caione.org>
925
925
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
926
+
L: linux-meson@googlegroups.com
927
+
W: http://linux-meson.com/
926
928
S: Maintained
927
-
F: drivers/media/rc/meson-ir.c
928
-
N: meson[x68]
929
+
F: arch/arm/mach-meson/
930
+
F: arch/arm/boot/dts/meson*
931
+
N: meson
929
932
930
933
ARM/Annapurna Labs ALPINE ARCHITECTURE
931
934
M: Tsahee Zidenberg <tsahee@annapurnalabs.com>
935
+
M: Antoine Tenart <antoine.tenart@free-electrons.com>
932
936
S: Maintained
933
937
F: arch/arm/mach-alpine/
938
+
F: arch/arm/boot/dts/alpine*
939
+
F: arch/arm64/boot/dts/al/
940
+
F: drivers/*/*alpine*
934
941
935
942
ARM/ATMEL AT91RM9200, AT91SAM9 AND SAMA5 SOC SUPPORT
936
943
M: Nicolas Ferre <nicolas.ferre@atmel.com>
+3
-11
arch/arm/boot/dts/am335x-bone-common.dtsi
+3
-11
arch/arm/boot/dts/am335x-bone-common.dtsi
···
285
285
};
286
286
};
287
287
288
+
289
+
/include/ "tps65217.dtsi"
290
+
288
291
&tps {
289
-
compatible = "ti,tps65217";
290
292
/*
291
293
* Configure pmic to enter OFF-state instead of SLEEP-state ("RTC-only
292
294
* mode") at poweroff. Most BeagleBone versions do not support RTC-only
···
309
307
ti,pmic-shutdown-controller;
310
308
311
309
regulators {
312
-
#address-cells = <1>;
313
-
#size-cells = <0>;
314
-
315
310
dcdc1_reg: regulator@0 {
316
-
reg = <0>;
317
311
regulator-name = "vdds_dpr";
318
312
regulator-always-on;
319
313
};
320
314
321
315
dcdc2_reg: regulator@1 {
322
-
reg = <1>;
323
316
/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
324
317
regulator-name = "vdd_mpu";
325
318
regulator-min-microvolt = <925000>;
···
324
327
};
325
328
326
329
dcdc3_reg: regulator@2 {
327
-
reg = <2>;
328
330
/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
329
331
regulator-name = "vdd_core";
330
332
regulator-min-microvolt = <925000>;
···
333
337
};
334
338
335
339
ldo1_reg: regulator@3 {
336
-
reg = <3>;
337
340
regulator-name = "vio,vrtc,vdds";
338
341
regulator-always-on;
339
342
};
340
343
341
344
ldo2_reg: regulator@4 {
342
-
reg = <4>;
343
345
regulator-name = "vdd_3v3aux";
344
346
regulator-always-on;
345
347
};
346
348
347
349
ldo3_reg: regulator@5 {
348
-
reg = <5>;
349
350
regulator-name = "vdd_1v8";
350
351
regulator-always-on;
351
352
};
352
353
353
354
ldo4_reg: regulator@6 {
354
-
reg = <6>;
355
355
regulator-name = "vdd_3v3a";
356
356
regulator-always-on;
357
357
};
+2
-12
arch/arm/boot/dts/am335x-chilisom.dtsi
+2
-12
arch/arm/boot/dts/am335x-chilisom.dtsi
···
128
128
129
129
};
130
130
131
+
/include/ "tps65217.dtsi"
132
+
131
133
&tps {
132
-
compatible = "ti,tps65217";
133
-
134
134
regulators {
135
-
#address-cells = <1>;
136
-
#size-cells = <0>;
137
-
138
135
dcdc1_reg: regulator@0 {
139
-
reg = <0>;
140
136
regulator-name = "vdds_dpr";
141
137
regulator-always-on;
142
138
};
143
139
144
140
dcdc2_reg: regulator@1 {
145
-
reg = <1>;
146
141
/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
147
142
regulator-name = "vdd_mpu";
148
143
regulator-min-microvolt = <925000>;
···
147
152
};
148
153
149
154
dcdc3_reg: regulator@2 {
150
-
reg = <2>;
151
155
/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
152
156
regulator-name = "vdd_core";
153
157
regulator-min-microvolt = <925000>;
···
156
162
};
157
163
158
164
ldo1_reg: regulator@3 {
159
-
reg = <3>;
160
165
regulator-name = "vio,vrtc,vdds";
161
166
regulator-boot-on;
162
167
regulator-always-on;
163
168
};
164
169
165
170
ldo2_reg: regulator@4 {
166
-
reg = <4>;
167
171
regulator-name = "vdd_3v3aux";
168
172
regulator-boot-on;
169
173
regulator-always-on;
170
174
};
171
175
172
176
ldo3_reg: regulator@5 {
173
-
reg = <5>;
174
177
regulator-name = "vdd_1v8";
175
178
regulator-boot-on;
176
179
regulator-always-on;
177
180
};
178
181
179
182
ldo4_reg: regulator@6 {
180
-
reg = <6>;
181
183
regulator-name = "vdd_3v3d";
182
184
regulator-boot-on;
183
185
regulator-always-on;
+2
-12
arch/arm/boot/dts/am335x-nano.dts
+2
-12
arch/arm/boot/dts/am335x-nano.dts
···
375
375
wp-gpios = <&gpio3 18 0>;
376
376
};
377
377
378
+
#include "tps65217.dtsi"
379
+
378
380
&tps {
379
-
compatible = "ti,tps65217";
380
-
381
381
regulators {
382
-
#address-cells = <1>;
383
-
#size-cells = <0>;
384
-
385
382
dcdc1_reg: regulator@0 {
386
-
reg = <0>;
387
383
/* +1.5V voltage with ±4% tolerance */
388
384
regulator-min-microvolt = <1450000>;
389
385
regulator-max-microvolt = <1550000>;
···
388
392
};
389
393
390
394
dcdc2_reg: regulator@1 {
391
-
reg = <1>;
392
395
/* VDD_MPU voltage limits 0.95V - 1.1V with ±4% tolerance */
393
396
regulator-name = "vdd_mpu";
394
397
regulator-min-microvolt = <915000>;
···
397
402
};
398
403
399
404
dcdc3_reg: regulator@2 {
400
-
reg = <2>;
401
405
/* VDD_CORE voltage limits 0.95V - 1.1V with ±4% tolerance */
402
406
regulator-name = "vdd_core";
403
407
regulator-min-microvolt = <915000>;
···
406
412
};
407
413
408
414
ldo1_reg: regulator@3 {
409
-
reg = <3>;
410
415
/* +1.8V voltage with ±4% tolerance */
411
416
regulator-min-microvolt = <1750000>;
412
417
regulator-max-microvolt = <1870000>;
···
414
421
};
415
422
416
423
ldo2_reg: regulator@4 {
417
-
reg = <4>;
418
424
/* +3.3V voltage with ±4% tolerance */
419
425
regulator-min-microvolt = <3175000>;
420
426
regulator-max-microvolt = <3430000>;
···
422
430
};
423
431
424
432
ldo3_reg: regulator@5 {
425
-
reg = <5>;
426
433
/* +1.8V voltage with ±4% tolerance */
427
434
regulator-min-microvolt = <1750000>;
428
435
regulator-max-microvolt = <1870000>;
···
430
439
};
431
440
432
441
ldo4_reg: regulator@6 {
433
-
reg = <6>;
434
442
/* +3.3V voltage with ±4% tolerance */
435
443
regulator-min-microvolt = <3175000>;
436
444
regulator-max-microvolt = <3430000>;
+2
-12
arch/arm/boot/dts/am335x-pepper.dts
+2
-12
arch/arm/boot/dts/am335x-pepper.dts
···
420
420
vin-supply = <&vbat>;
421
421
};
422
422
423
-
&tps {
424
-
compatible = "ti,tps65217";
423
+
/include/ "tps65217.dtsi"
425
424
425
+
&tps {
426
426
backlight {
427
427
isel = <1>; /* ISET1 */
428
428
fdim = <200>; /* TPS65217_BL_FDIM_200HZ */
···
430
430
};
431
431
432
432
regulators {
433
-
#address-cells = <1>;
434
-
#size-cells = <0>;
435
-
436
433
dcdc1_reg: regulator@0 {
437
-
reg = <0>;
438
434
/* VDD_1V8 system supply */
439
435
regulator-always-on;
440
436
};
441
437
442
438
dcdc2_reg: regulator@1 {
443
-
reg = <1>;
444
439
/* VDD_CORE voltage limits 0.95V - 1.26V with +/-4% tolerance */
445
440
regulator-name = "vdd_core";
446
441
regulator-min-microvolt = <925000>;
···
445
450
};
446
451
447
452
dcdc3_reg: regulator@2 {
448
-
reg = <2>;
449
453
/* VDD_MPU voltage limits 0.95V - 1.1V with +/-4% tolerance */
450
454
regulator-name = "vdd_mpu";
451
455
regulator-min-microvolt = <925000>;
···
454
460
};
455
461
456
462
ldo1_reg: regulator@3 {
457
-
reg = <3>;
458
463
/* VRTC 1.8V always-on supply */
459
464
regulator-name = "vrtc,vdds";
460
465
regulator-always-on;
461
466
};
462
467
463
468
ldo2_reg: regulator@4 {
464
-
reg = <4>;
465
469
/* 3.3V rail */
466
470
regulator-name = "vdd_3v3aux";
467
471
regulator-always-on;
468
472
};
469
473
470
474
ldo3_reg: regulator@5 {
471
-
reg = <5>;
472
475
/* VDD_3V3A 3.3V rail */
473
476
regulator-name = "vdd_3v3a";
474
477
regulator-min-microvolt = <3300000>;
···
473
482
};
474
483
475
484
ldo4_reg: regulator@6 {
476
-
reg = <6>;
477
485
/* VDD_3V3B 3.3V rail */
478
486
regulator-name = "vdd_3v3b";
479
487
regulator-always-on;
+2
-2
arch/arm/boot/dts/am335x-shc.dts
+2
-2
arch/arm/boot/dts/am335x-shc.dts
···
46
46
gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
47
47
linux,code = <KEY_BACK>;
48
48
debounce-interval = <1000>;
49
-
gpio-key,wakeup;
49
+
wakeup-source;
50
50
};
51
51
52
52
front_button {
···
54
54
gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>;
55
55
linux,code = <KEY_FRONT>;
56
56
debounce-interval = <1000>;
57
-
gpio-key,wakeup;
57
+
wakeup-source;
58
58
};
59
59
};
60
60
+2
-11
arch/arm/boot/dts/am335x-sl50.dts
+2
-11
arch/arm/boot/dts/am335x-sl50.dts
···
375
375
pinctrl-0 = <&uart4_pins>;
376
376
};
377
377
378
+
#include "tps65217.dtsi"
379
+
378
380
&tps {
379
-
compatible = "ti,tps65217";
380
381
ti,pmic-shutdown-controller;
381
382
382
383
interrupt-parent = <&intc>;
383
384
interrupts = <7>; /* NNMI */
384
385
385
386
regulators {
386
-
#address-cells = <1>;
387
-
#size-cells = <0>;
388
-
389
387
dcdc1_reg: regulator@0 {
390
-
reg = <0>;
391
388
/* VDDS_DDR */
392
389
regulator-min-microvolt = <1500000>;
393
390
regulator-max-microvolt = <1500000>;
···
392
395
};
393
396
394
397
dcdc2_reg: regulator@1 {
395
-
reg = <1>;
396
398
/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
397
399
regulator-name = "vdd_mpu";
398
400
regulator-min-microvolt = <925000>;
···
401
405
};
402
406
403
407
dcdc3_reg: regulator@2 {
404
-
reg = <2>;
405
408
/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
406
409
regulator-name = "vdd_core";
407
410
regulator-min-microvolt = <925000>;
···
410
415
};
411
416
412
417
ldo1_reg: regulator@3 {
413
-
reg = <3>;
414
418
/* VRTC / VIO / VDDS*/
415
419
regulator-always-on;
416
420
regulator-min-microvolt = <1800000>;
···
417
423
};
418
424
419
425
ldo2_reg: regulator@4 {
420
-
reg = <4>;
421
426
/* VDD_3V3AUX */
422
427
regulator-always-on;
423
428
regulator-min-microvolt = <3300000>;
···
424
431
};
425
432
426
433
ldo3_reg: regulator@5 {
427
-
reg = <5>;
428
434
/* VDD_1V8 */
429
435
regulator-min-microvolt = <1800000>;
430
436
regulator-max-microvolt = <1800000>;
···
431
439
};
432
440
433
441
ldo4_reg: regulator@6 {
434
-
reg = <6>;
435
442
/* VDD_3V3A */
436
443
regulator-min-microvolt = <3300000>;
437
444
regulator-max-microvolt = <3300000>;
+4
arch/arm/boot/dts/am57xx-beagle-x15.dts
+4
arch/arm/boot/dts/am57xx-beagle-x15.dts
···
173
173
174
174
sound0_master: simple-audio-card,codec {
175
175
sound-dai = <&tlv320aic3104>;
176
+
assigned-clocks = <&clkoutmux2_clk_mux>;
177
+
assigned-clock-parents = <&sys_clk2_dclk_div>;
176
178
clocks = <&clkout2_clk>;
177
179
};
178
180
};
···
798
796
pinctrl-names = "default", "sleep";
799
797
pinctrl-0 = <&mcasp3_pins_default>;
800
798
pinctrl-1 = <&mcasp3_pins_sleep>;
799
+
assigned-clocks = <&mcasp3_ahclkx_mux>;
800
+
assigned-clock-parents = <&sys_clkin2>;
801
801
status = "okay";
802
802
803
803
op-mode = <0>; /* MCASP_IIS_MODE */
+1
-1
arch/arm/boot/dts/am57xx-cl-som-am57x.dts
+1
-1
arch/arm/boot/dts/am57xx-cl-som-am57x.dts
-1
arch/arm/boot/dts/imx6qdl.dtsi
-1
arch/arm/boot/dts/imx6qdl.dtsi
+1
-1
arch/arm/boot/dts/kirkwood-ds112.dts
+1
-1
arch/arm/boot/dts/kirkwood-ds112.dts
+31
arch/arm/boot/dts/orion5x-linkstation-lswtgl.dts
+31
arch/arm/boot/dts/orion5x-linkstation-lswtgl.dts
···
228
228
};
229
229
};
230
230
231
+
&devbus_bootcs {
232
+
status = "okay";
233
+
devbus,keep-config;
234
+
235
+
flash@0 {
236
+
compatible = "jedec-flash";
237
+
reg = <0 0x40000>;
238
+
bank-width = <1>;
239
+
240
+
partitions {
241
+
compatible = "fixed-partitions";
242
+
#address-cells = <1>;
243
+
#size-cells = <1>;
244
+
245
+
header@0 {
246
+
reg = <0 0x30000>;
247
+
read-only;
248
+
};
249
+
250
+
uboot@30000 {
251
+
reg = <0x30000 0xF000>;
252
+
read-only;
253
+
};
254
+
255
+
uboot_env@3F000 {
256
+
reg = <0x3F000 0x1000>;
257
+
};
258
+
};
259
+
};
260
+
};
261
+
231
262
&mdio {
232
263
status = "okay";
233
264
+1
-1
arch/arm/boot/dts/sama5d2-pinfunc.h
+1
-1
arch/arm/boot/dts/sama5d2-pinfunc.h
···
90
90
#define PIN_PA14__I2SC1_MCK PINMUX_PIN(PIN_PA14, 4, 2)
91
91
#define PIN_PA14__FLEXCOM3_IO2 PINMUX_PIN(PIN_PA14, 5, 1)
92
92
#define PIN_PA14__D9 PINMUX_PIN(PIN_PA14, 6, 2)
93
-
#define PIN_PA15 14
93
+
#define PIN_PA15 15
94
94
#define PIN_PA15__GPIO PINMUX_PIN(PIN_PA15, 0, 0)
95
95
#define PIN_PA15__SPI0_MOSI PINMUX_PIN(PIN_PA15, 1, 1)
96
96
#define PIN_PA15__TF1 PINMUX_PIN(PIN_PA15, 2, 1)
+56
arch/arm/boot/dts/tps65217.dtsi
+56
arch/arm/boot/dts/tps65217.dtsi
···
1
+
/*
2
+
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3
+
*
4
+
* This program is free software; you can redistribute it and/or modify
5
+
* it under the terms of the GNU General Public License version 2 as
6
+
* published by the Free Software Foundation.
7
+
*/
8
+
9
+
/*
10
+
* Integrated Power Management Chip
11
+
* http://www.ti.com/lit/ds/symlink/tps65217.pdf
12
+
*/
13
+
14
+
&tps {
15
+
compatible = "ti,tps65217";
16
+
17
+
regulators {
18
+
#address-cells = <1>;
19
+
#size-cells = <0>;
20
+
21
+
dcdc1_reg: regulator@0 {
22
+
reg = <0>;
23
+
regulator-compatible = "dcdc1";
24
+
};
25
+
26
+
dcdc2_reg: regulator@1 {
27
+
reg = <1>;
28
+
regulator-compatible = "dcdc2";
29
+
};
30
+
31
+
dcdc3_reg: regulator@2 {
32
+
reg = <2>;
33
+
regulator-compatible = "dcdc3";
34
+
};
35
+
36
+
ldo1_reg: regulator@3 {
37
+
reg = <3>;
38
+
regulator-compatible = "ldo1";
39
+
};
40
+
41
+
ldo2_reg: regulator@4 {
42
+
reg = <4>;
43
+
regulator-compatible = "ldo2";
44
+
};
45
+
46
+
ldo3_reg: regulator@5 {
47
+
reg = <5>;
48
+
regulator-compatible = "ldo3";
49
+
};
50
+
51
+
ldo4_reg: regulator@6 {
52
+
reg = <6>;
53
+
regulator-compatible = "ldo4";
54
+
};
55
+
};
56
+
};
+21
-1
arch/arm/mach-omap2/board-generic.c
+21
-1
arch/arm/mach-omap2/board-generic.c
···
18
18
19
19
#include <asm/setup.h>
20
20
#include <asm/mach/arch.h>
21
+
#include <asm/system_info.h>
21
22
22
23
#include "common.h"
23
24
···
78
77
NULL,
79
78
};
80
79
80
+
/* Set system_rev from atags */
81
+
static void __init rx51_set_system_rev(const struct tag *tags)
82
+
{
83
+
const struct tag *tag;
84
+
85
+
if (tags->hdr.tag != ATAG_CORE)
86
+
return;
87
+
88
+
for_each_tag(tag, tags) {
89
+
if (tag->hdr.tag == ATAG_REVISION) {
90
+
system_rev = tag->u.revision.rev;
91
+
break;
92
+
}
93
+
}
94
+
}
95
+
81
96
/* Legacy userspace on Nokia N900 needs ATAGS exported in /proc/atags,
82
97
* save them while the data is still not overwritten
83
98
*/
84
99
static void __init rx51_reserve(void)
85
100
{
86
-
save_atags((const struct tag *)(PAGE_OFFSET + 0x100));
101
+
const struct tag *tags = (const struct tag *)(PAGE_OFFSET + 0x100);
102
+
103
+
save_atags(tags);
104
+
rx51_set_system_rev(tags);
87
105
omap_reserve();
88
106
}
89
107
+3
-3
arch/arm/mach-omap2/gpmc-onenand.c
+3
-3
arch/arm/mach-omap2/gpmc-onenand.c
···
101
101
102
102
static void set_onenand_cfg(void __iomem *onenand_base)
103
103
{
104
-
u32 reg;
104
+
u32 reg = ONENAND_SYS_CFG1_RDY | ONENAND_SYS_CFG1_INT;
105
105
106
-
reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
107
-
reg &= ~((0x7 << ONENAND_SYS_CFG1_BRL_SHIFT) | (0x7 << 9));
108
106
reg |= (latency << ONENAND_SYS_CFG1_BRL_SHIFT) |
109
107
ONENAND_SYS_CFG1_BL_16;
110
108
if (onenand_flags & ONENAND_FLAG_SYNCREAD)
···
121
123
reg |= ONENAND_SYS_CFG1_VHF;
122
124
else
123
125
reg &= ~ONENAND_SYS_CFG1_VHF;
126
+
124
127
writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
125
128
}
126
129
···
288
289
}
289
290
}
290
291
292
+
onenand_async.sync_write = true;
291
293
omap2_onenand_calc_async_timings(&t);
292
294
293
295
ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &onenand_async);
+13
-1
arch/arm/mach-omap2/omap_device.c
+13
-1
arch/arm/mach-omap2/omap_device.c
···
191
191
{
192
192
struct platform_device *pdev = to_platform_device(dev);
193
193
struct omap_device *od;
194
+
int err;
194
195
195
196
switch (event) {
196
197
case BUS_NOTIFY_DEL_DEVICE:
197
198
if (pdev->archdata.od)
198
199
omap_device_delete(pdev->archdata.od);
200
+
break;
201
+
case BUS_NOTIFY_UNBOUND_DRIVER:
202
+
od = to_omap_device(pdev);
203
+
if (od && (od->_state == OMAP_DEVICE_STATE_ENABLED)) {
204
+
dev_info(dev, "enabled after unload, idling\n");
205
+
err = omap_device_idle(pdev);
206
+
if (err)
207
+
dev_err(dev, "failed to idle\n");
208
+
}
199
209
break;
200
210
case BUS_NOTIFY_ADD_DEVICE:
201
211
if (pdev->dev.of_node)
···
612
602
int ret;
613
603
614
604
ret = omap_device_enable(pdev);
615
-
if (ret)
605
+
if (ret) {
606
+
dev_err(dev, "use pm_runtime_put_sync_suspend() in driver?\n");
616
607
return ret;
608
+
}
617
609
618
610
return pm_generic_runtime_resume(dev);
619
611
}
-1
arch/arm/mach-shmobile/common.h
-1
arch/arm/mach-shmobile/common.h
···
4
4
extern void shmobile_init_delay(void);
5
5
extern void shmobile_boot_vector(void);
6
6
extern unsigned long shmobile_boot_fn;
7
-
extern unsigned long shmobile_boot_arg;
8
7
extern unsigned long shmobile_boot_size;
9
8
extern void shmobile_smp_boot(void);
10
9
extern void shmobile_smp_sleep(void);
-6
arch/arm/mach-shmobile/headsmp-scu.S
-6
arch/arm/mach-shmobile/headsmp-scu.S
+16
-12
arch/arm/mach-shmobile/headsmp.S
+16
-12
arch/arm/mach-shmobile/headsmp.S
···
24
24
.arm
25
25
.align 12
26
26
ENTRY(shmobile_boot_vector)
27
-
ldr r0, 2f
28
27
ldr r1, 1f
29
28
bx r1
30
29
···
33
34
.globl shmobile_boot_fn
34
35
shmobile_boot_fn:
35
36
1: .space 4
36
-
.globl shmobile_boot_arg
37
-
shmobile_boot_arg:
38
-
2: .space 4
39
37
.globl shmobile_boot_size
40
38
shmobile_boot_size:
41
39
.long . - shmobile_boot_vector
···
42
46
*/
43
47
44
48
ENTRY(shmobile_smp_boot)
45
-
@ r0 = MPIDR_HWID_BITMASK
46
49
mrc p15, 0, r1, c0, c0, 5 @ r1 = MPIDR
47
-
and r0, r1, r0 @ r0 = cpu_logical_map() value
50
+
and r0, r1, #0xffffff @ MPIDR_HWID_BITMASK
51
+
@ r0 = cpu_logical_map() value
48
52
mov r1, #0 @ r1 = CPU index
49
-
adr r5, 1f @ array of per-cpu mpidr values
50
-
adr r6, 2f @ array of per-cpu functions
51
-
adr r7, 3f @ array of per-cpu arguments
53
+
adr r2, 1f
54
+
ldmia r2, {r5, r6, r7}
55
+
add r5, r5, r2 @ array of per-cpu mpidr values
56
+
add r6, r6, r2 @ array of per-cpu functions
57
+
add r7, r7, r2 @ array of per-cpu arguments
52
58
53
59
shmobile_smp_boot_find_mpidr:
54
60
ldr r8, [r5, r1, lsl #2]
···
78
80
b shmobile_smp_boot
79
81
ENDPROC(shmobile_smp_sleep)
80
82
83
+
.align 2
84
+
1: .long shmobile_smp_mpidr - .
85
+
.long shmobile_smp_fn - 1b
86
+
.long shmobile_smp_arg - 1b
87
+
88
+
.bss
81
89
.globl shmobile_smp_mpidr
82
90
shmobile_smp_mpidr:
83
-
1: .space NR_CPUS * 4
91
+
.space NR_CPUS * 4
84
92
.globl shmobile_smp_fn
85
93
shmobile_smp_fn:
86
-
2: .space NR_CPUS * 4
94
+
.space NR_CPUS * 4
87
95
.globl shmobile_smp_arg
88
96
shmobile_smp_arg:
89
-
3: .space NR_CPUS * 4
97
+
.space NR_CPUS * 4
-1
arch/arm/mach-shmobile/platsmp-apmu.c
-1
arch/arm/mach-shmobile/platsmp-apmu.c
+3
-1
arch/arm/mach-shmobile/platsmp-scu.c
+3
-1
arch/arm/mach-shmobile/platsmp-scu.c
···
17
17
#include <asm/smp_scu.h>
18
18
#include "common.h"
19
19
20
+
21
+
void __iomem *shmobile_scu_base;
22
+
20
23
static int shmobile_smp_scu_notifier_call(struct notifier_block *nfb,
21
24
unsigned long action, void *hcpu)
22
25
{
···
44
41
{
45
42
/* install boot code shared by all CPUs */
46
43
shmobile_boot_fn = virt_to_phys(shmobile_smp_boot);
47
-
shmobile_boot_arg = MPIDR_HWID_BITMASK;
48
44
49
45
/* enable SCU and cache coherency on booting CPU */
50
46
scu_enable(shmobile_scu_base);
-2
arch/arm/mach-shmobile/smp-r8a7779.c
-2
arch/arm/mach-shmobile/smp-r8a7779.c
···
92
92
{
93
93
/* Map the reset vector (in headsmp-scu.S, headsmp.S) */
94
94
__raw_writel(__pa(shmobile_boot_vector), AVECR);
95
-
shmobile_boot_fn = virt_to_phys(shmobile_boot_scu);
96
-
shmobile_boot_arg = (unsigned long)shmobile_scu_base;
97
95
98
96
/* setup r8a7779 specific SCU bits */
99
97
shmobile_scu_base = IOMEM(R8A7779_SCU_BASE);