-12

Documentation/ABI/obsolete/sysfs-bus-iio

reviewed

··· 48 48 What: /sys/.../iio:deviceX/scan_elements/in_voltageY_supply_en 49 49 What: /sys/.../iio:deviceX/scan_elements/in_voltageY_en 50 50 What: /sys/.../iio:deviceX/scan_elements/in_voltageY-voltageZ_en 51 51 - What: /sys/.../iio:deviceX/scan_elements/in_voltageY_i_en 52 52 - What: /sys/.../iio:deviceX/scan_elements/in_voltageY_q_en 53 53 - What: /sys/.../iio:deviceX/scan_elements/in_voltage_i_en 54 54 - What: /sys/.../iio:deviceX/scan_elements/in_voltage_q_en 55 51 What: /sys/.../iio:deviceX/scan_elements/in_incli_x_en 56 52 What: /sys/.../iio:deviceX/scan_elements/in_incli_y_en 57 53 What: /sys/.../iio:deviceX/scan_elements/in_pressureY_en ··· 69 73 What: /sys/.../iio:deviceX/scan_elements/in_voltageY_type 70 74 What: /sys/.../iio:deviceX/scan_elements/in_voltage_type 71 75 What: /sys/.../iio:deviceX/scan_elements/in_voltageY_supply_type 72 72 - What: /sys/.../iio:deviceX/scan_elements/in_voltageY_i_type 73 73 - What: /sys/.../iio:deviceX/scan_elements/in_voltageY_q_type 74 74 - What: /sys/.../iio:deviceX/scan_elements/in_voltage_i_type 75 75 - What: /sys/.../iio:deviceX/scan_elements/in_voltage_q_type 76 76 What: /sys/.../iio:deviceX/scan_elements/in_timestamp_type 77 77 What: /sys/.../iio:deviceX/scan_elements/in_pressureY_type 78 78 What: /sys/.../iio:deviceX/scan_elements/in_pressure_type ··· 102 110 103 111 What: /sys/.../iio:deviceX/scan_elements/in_voltageY_index 104 112 What: /sys/.../iio:deviceX/scan_elements/in_voltageY_supply_index 105 105 - What: /sys/.../iio:deviceX/scan_elements/in_voltageY_i_index 106 106 - What: /sys/.../iio:deviceX/scan_elements/in_voltageY_q_index 107 107 - What: /sys/.../iio:deviceX/scan_elements/in_voltage_i_index 108 108 - What: /sys/.../iio:deviceX/scan_elements/in_voltage_q_index 109 113 What: /sys/.../iio:deviceX/scan_elements/in_accel_x_index 110 114 What: /sys/.../iio:deviceX/scan_elements/in_accel_y_index 111 115 What: /sys/.../iio:deviceX/scan_elements/in_accel_z_index

+35 -32

Documentation/ABI/testing/sysfs-bus-iio

reviewed

··· 141 141 142 142 What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_raw 143 143 What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_supply_raw 144 144 - What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_i_raw 145 145 - What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_q_raw 146 144 KernelVersion: 2.6.35 147 145 Contact: linux-iio@vger.kernel.org 148 146 Description: ··· 415 417 What: /sys/bus/iio/devices/iio:deviceX/in_accel_x_offset 416 418 What: /sys/bus/iio/devices/iio:deviceX/in_accel_y_offset 417 419 What: /sys/bus/iio/devices/iio:deviceX/in_accel_z_offset 420 420 + What: /sys/bus/iio/devices/iio:deviceX/in_altvoltage_q_offset 421 421 + What: /sys/bus/iio/devices/iio:deviceX/in_altvoltage_i_offset 418 422 What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_offset 419 423 What: /sys/bus/iio/devices/iio:deviceX/in_voltage_offset 420 424 What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_i_offset 421 425 What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_q_offset 422 422 - What: /sys/bus/iio/devices/iio:deviceX/in_voltage_q_offset 423 423 - What: /sys/bus/iio/devices/iio:deviceX/in_voltage_i_offset 424 426 What: /sys/bus/iio/devices/iio:deviceX/in_currentY_offset 425 427 What: /sys/bus/iio/devices/iio:deviceX/in_current_offset 426 426 - What: /sys/bus/iio/devices/iio:deviceX/in_currentY_i_offset 427 427 - What: /sys/bus/iio/devices/iio:deviceX/in_currentY_q_offset 428 428 - What: /sys/bus/iio/devices/iio:deviceX/in_current_q_offset 429 429 - What: /sys/bus/iio/devices/iio:deviceX/in_current_i_offset 430 428 What: /sys/bus/iio/devices/iio:deviceX/in_tempY_offset 431 429 What: /sys/bus/iio/devices/iio:deviceX/in_temp_offset 432 430 What: /sys/bus/iio/devices/iio:deviceX/in_pressureY_offset ··· 450 456 to the _raw output. 451 457 452 458 What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_scale 453 453 - What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_i_scale 454 459 What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_q_scale 455 460 What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_supply_scale 456 461 What: /sys/bus/iio/devices/iio:deviceX/in_voltage_scale 457 457 - What: /sys/bus/iio/devices/iio:deviceX/in_voltage_i_scale 458 458 - What: /sys/bus/iio/devices/iio:deviceX/in_voltage_q_scale 459 462 What: /sys/bus/iio/devices/iio:deviceX/in_voltage-voltage_scale 460 463 What: /sys/bus/iio/devices/iio:deviceX/out_voltageY_scale 461 464 What: /sys/bus/iio/devices/iio:deviceX/out_altvoltageY_scale 462 465 What: /sys/bus/iio/devices/iio:deviceX/in_currentY_scale 463 466 What: /sys/bus/iio/devices/iio:deviceX/in_currentY_supply_scale 464 467 What: /sys/bus/iio/devices/iio:deviceX/in_current_scale 465 465 - What: /sys/bus/iio/devices/iio:deviceX/in_currentY_i_scale 466 466 - What: /sys/bus/iio/devices/iio:deviceX/in_currentY_q_scale 467 467 - What: /sys/bus/iio/devices/iio:deviceX/in_current_i_scale 468 468 What: /sys/bus/iio/devices/iio:deviceX/in_current_q_scale 469 469 What: /sys/bus/iio/devices/iio:deviceX/in_accel_scale 470 470 What: /sys/bus/iio/devices/iio:deviceX/in_accel_peak_scale ··· 547 559 - a small discrete set of values like "0 2 4 6 8" 548 560 - a range specified as "[min step max]" 549 561 562 562 + What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_convdelay 563 563 + KernelVersion: 6.17 564 564 + Contact: linux-iio@vger.kernel.org 565 565 + Description: 566 566 + Delay of start of conversion from common reference point shared 567 567 + by all channels. Can be writable when used to compensate for 568 568 + delay variation introduced by external filters feeding a 569 569 + simultaneous sampling ADC. 570 570 + 571 571 + E.g., for the ad7606 ADC series, this value is intended as a 572 572 + configurable time delay in seconds, to correct delay introduced 573 573 + by an optional external filtering circuit. 574 574 + 575 575 + What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_convdelay_available 576 576 + KernelVersion: 6.16 577 577 + Contact: linux-iio@vger.kernel.org 578 578 + Description: 579 579 + Available values of convdelay. Maybe expressed as: 580 580 + 581 581 + - a range specified as "[min step max]" 582 582 + 583 583 + If shared across all channels, <type>_convdelay_available 584 584 + is used. 585 585 + 550 586 What: /sys/bus/iio/devices/iio:deviceX/in_accel_x_calibscale 551 587 What: /sys/bus/iio/devices/iio:deviceX/in_accel_y_calibscale 552 588 What: /sys/bus/iio/devices/iio:deviceX/in_accel_z_calibscale ··· 591 579 What: /sys/bus/iio/devices/iio:deviceX/in_pressureY_calibscale 592 580 What: /sys/bus/iio/devices/iio:deviceX/in_proximity0_calibscale 593 581 What: /sys/bus/iio/devices/iio:deviceX/in_voltage_calibscale 594 594 - What: /sys/bus/iio/devices/iio:deviceX/in_voltage_i_calibscale 595 595 - What: /sys/bus/iio/devices/iio:deviceX/in_voltage_q_calibscale 596 582 What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_calibscale 597 597 - What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_i_calibscale 598 598 - What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_q_calibscale 599 583 What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_supply_calibscale 600 584 What: /sys/bus/iio/devices/iio:deviceX/out_currentY_calibscale 601 585 What: /sys/bus/iio/devices/iio:deviceX/out_voltageY_calibscale ··· 813 805 all the other channels, since it involves changing the VCO 814 806 fundamental output frequency. 815 807 808 808 + What: /sys/bus/iio/devices/iio:deviceX/in_altvoltageY_i_phase 809 809 + What: /sys/bus/iio/devices/iio:deviceX/in_altvoltageY_q_phase 816 810 What: /sys/bus/iio/devices/iio:deviceX/out_altvoltageY_phase 811 811 + What: /sys/bus/iio/devices/iio:deviceX/out_altvoltageY_i_phase 812 812 + What: /sys/bus/iio/devices/iio:deviceX/out_altvoltageY_q_phase 817 813 KernelVersion: 3.4.0 818 814 Contact: linux-iio@vger.kernel.org 819 815 Description: ··· 1446 1434 What: /sys/.../iio:deviceX/bufferY/in_voltageY_supply_en 1447 1435 What: /sys/.../iio:deviceX/bufferY/in_voltageY_en 1448 1436 What: /sys/.../iio:deviceX/bufferY/in_voltageY-voltageZ_en 1449 1449 - What: /sys/.../iio:deviceX/bufferY/in_voltageY_i_en 1450 1450 - What: /sys/.../iio:deviceX/bufferY/in_voltageY_q_en 1451 1451 - What: /sys/.../iio:deviceX/bufferY/in_voltage_i_en 1452 1452 - What: /sys/.../iio:deviceX/bufferY/in_voltage_q_en 1453 1437 What: /sys/.../iio:deviceX/bufferY/in_incli_x_en 1454 1438 What: /sys/.../iio:deviceX/bufferY/in_incli_y_en 1455 1439 What: /sys/.../iio:deviceX/bufferY/in_pressureY_en ··· 1466 1458 What: /sys/.../iio:deviceX/bufferY/in_voltageY_type 1467 1459 What: /sys/.../iio:deviceX/bufferY/in_voltage_type 1468 1460 What: /sys/.../iio:deviceX/bufferY/in_voltageY_supply_type 1469 1469 - What: /sys/.../iio:deviceX/bufferY/in_voltageY_i_type 1470 1470 - What: /sys/.../iio:deviceX/bufferY/in_voltageY_q_type 1471 1471 - What: /sys/.../iio:deviceX/bufferY/in_voltage_i_type 1472 1472 - What: /sys/.../iio:deviceX/bufferY/in_voltage_q_type 1473 1461 What: /sys/.../iio:deviceX/bufferY/in_timestamp_type 1474 1462 What: /sys/.../iio:deviceX/bufferY/in_pressureY_type 1475 1463 What: /sys/.../iio:deviceX/bufferY/in_pressure_type ··· 1503 1499 1504 1500 What: /sys/.../iio:deviceX/bufferY/in_voltageY_index 1505 1501 What: /sys/.../iio:deviceX/bufferY/in_voltageY_supply_index 1506 1506 - What: /sys/.../iio:deviceX/bufferY/in_voltageY_i_index 1507 1507 - What: /sys/.../iio:deviceX/bufferY/in_voltageY_q_index 1508 1508 - What: /sys/.../iio:deviceX/bufferY/in_voltage_i_index 1509 1509 - What: /sys/.../iio:deviceX/bufferY/in_voltage_q_index 1510 1502 What: /sys/.../iio:deviceX/bufferY/in_accel_x_index 1511 1503 What: /sys/.../iio:deviceX/bufferY/in_accel_y_index 1512 1504 What: /sys/.../iio:deviceX/bufferY/in_accel_z_index ··· 1692 1692 1693 1693 What: /sys/bus/iio/devices/iio:deviceX/in_currentY_raw 1694 1694 What: /sys/bus/iio/devices/iio:deviceX/in_currentY_supply_raw 1695 1695 - What: /sys/bus/iio/devices/iio:deviceX/in_currentY_i_raw 1696 1696 - What: /sys/bus/iio/devices/iio:deviceX/in_currentY_q_raw 1697 1695 KernelVersion: 3.17 1698 1696 Contact: linux-iio@vger.kernel.org 1699 1697 Description: ··· 2276 2278 Reading returns a list with the possible filter modes. Options 2277 2279 for the attribute: 2278 2280 2281 2281 + * "none" - Filter is disabled/bypassed. 2282 2282 + * "sinc1" - The digital sinc1 filter. Fast 1st 2283 2283 + conversion time. Poor noise performance. 2279 2284 * "sinc3" - The digital sinc3 filter. Moderate 1st 2280 2285 conversion time. Good noise performance. 2281 2286 * "sinc4" - Sinc 4. Excellent noise performance. Long ··· 2294 2293 * "sinc3+pf2" - Sinc3 + device specific Post Filter 2. 2295 2294 * "sinc3+pf3" - Sinc3 + device specific Post Filter 3. 2296 2295 * "sinc3+pf4" - Sinc3 + device specific Post Filter 4. 2296 2296 + * "sinc5+pf1" - Sinc5 + device specific Post Filter 1. 2297 2297 + * "sinc5+avg" - Sinc5 + averaging by 4. 2297 2298 * "wideband" - filter with wideband low ripple passband 2298 2299 and sharp transition band. 2299 2300

+2 -2

Documentation/ABI/testing/sysfs-bus-iio-frequency-admv1013

reviewed

··· 1 1 - What: /sys/bus/iio/devices/iio:deviceX/in_altvoltage0-1_i_calibphase 1 1 + What: /sys/bus/iio/devices/iio:deviceX/in_altvoltage0-altvoltage1_i_calibphase 2 2 KernelVersion: 3 3 Contact: linux-iio@vger.kernel.org 4 4 Description: 5 5 Read/write unscaled value for the Local Oscillatior path quadrature I phase shift. 6 6 7 7 - What: /sys/bus/iio/devices/iio:deviceX/in_altvoltage0-1_q_calibphase 7 7 + What: /sys/bus/iio/devices/iio:deviceX/in_altvoltage0-altvoltage1_q_calibphase 8 8 KernelVersion: 9 9 Contact: linux-iio@vger.kernel.org 10 10 Description:

+96

Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 + # Copyright 2025 Analog Devices Inc. 3 3 + %YAML 1.2 4 4 + --- 5 5 + $id: http://devicetree.org/schemas/iio/adc/adi,ad4080.yaml# 6 6 + $schema: http://devicetree.org/meta-schemas/core.yaml# 7 7 + 8 8 + title: Analog Devices AD4080 20-Bit, 40 MSPS, Differential SAR ADC 9 9 + 10 10 + maintainers: 11 11 + - Antoniu Miclaus <antoniu.miclaus@analog.com> 12 12 + 13 13 + description: | 14 14 + The AD4080 is a high speed, low noise, low distortion, 20-bit, Easy Drive, 15 15 + successive approximation register (SAR) analog-to-digital converter (ADC). 16 16 + Maintaining high performance (signal-to-noise and distortion (SINAD) ratio 17 17 + > 90 dBFS) at signal frequencies in excess of 1 MHz enables the AD4080 to 18 18 + service a wide variety of precision, wide bandwidth data acquisition 19 19 + applications. 20 20 + 21 21 + https://www.analog.com/media/en/technical-documentation/data-sheets/ad4080.pdf 22 22 + 23 23 + $ref: /schemas/spi/spi-peripheral-props.yaml# 24 24 + 25 25 + properties: 26 26 + compatible: 27 27 + enum: 28 28 + - adi,ad4080 29 29 + 30 30 + reg: 31 31 + maxItems: 1 32 32 + 33 33 + spi-max-frequency: 34 34 + description: Configuration of the SPI bus. 35 35 + maximum: 50000000 36 36 + 37 37 + clocks: 38 38 + maxItems: 1 39 39 + 40 40 + clock-names: 41 41 + items: 42 42 + - const: cnv 43 43 + 44 44 + vdd33-supply: true 45 45 + 46 46 + vdd11-supply: true 47 47 + 48 48 + vddldo-supply: true 49 49 + 50 50 + iovdd-supply: true 51 51 + 52 52 + vrefin-supply: true 53 53 + 54 54 + io-backends: 55 55 + maxItems: 1 56 56 + 57 57 + adi,lvds-cnv-enable: 58 58 + description: Enable the LVDS signal type on the CNV pin. Default is CMOS. 59 59 + type: boolean 60 60 + 61 61 + adi,num-lanes: 62 62 + description: 63 63 + Number of lanes on which the data is sent on the output (DA, DB pins). 64 64 + $ref: /schemas/types.yaml#/definitions/uint32 65 65 + enum: [1, 2] 66 66 + default: 1 67 67 + 68 68 + required: 69 69 + - compatible 70 70 + - reg 71 71 + - clocks 72 72 + - clock-names 73 73 + - vdd33-supply 74 74 + - vrefin-supply 75 75 + 76 76 + additionalProperties: false 77 77 + 78 78 + examples: 79 79 + - | 80 80 + spi { 81 81 + #address-cells = <1>; 82 82 + #size-cells = <0>; 83 83 + 84 84 + adc@0 { 85 85 + compatible = "adi,ad4080"; 86 86 + reg = <0>; 87 87 + spi-max-frequency = <10000000>; 88 88 + vdd33-supply = <&vdd33>; 89 89 + vddldo-supply = <&vddldo>; 90 90 + vrefin-supply = <&vrefin>; 91 91 + clocks = <&cnv>; 92 92 + clock-names = "cnv"; 93 93 + io-backends = <&iio_backend>; 94 94 + }; 95 95 + }; 96 96 + ...

+554

Documentation/devicetree/bindings/iio/adc/adi,ad4170-4.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/iio/adc/adi,ad4170-4.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: Analog Devices AD4170-4 and similar Analog to Digital Converters 8 8 + 9 9 + maintainers: 10 10 + - Marcelo Schmitt <marcelo.schmitt@analog.com> 11 11 + 12 12 + description: | 13 13 + Analog Devices AD4170-4 series of Sigma-delta Analog to Digital Converters. 14 14 + Specifications can be found at: 15 15 + https://www.analog.com/media/en/technical-documentation/data-sheets/ad4170-4.pdf 16 16 + https://www.analog.com/media/en/technical-documentation/data-sheets/ad4190-4.pdf 17 17 + https://www.analog.com/media/en/technical-documentation/data-sheets/ad4195-4.pdf 18 18 + 19 19 + $ref: /schemas/spi/spi-peripheral-props.yaml# 20 20 + 21 21 + $defs: 22 22 + reference-buffer: 23 23 + description: | 24 24 + Enable precharge buffer, full buffer, or skip reference buffering of 25 25 + the positive/negative voltage reference. Because the output impedance 26 26 + of the source driving the voltage reference inputs may be dynamic, 27 27 + resistive/capacitive combinations of those inputs can cause DC gain 28 28 + errors if the reference inputs go unbuffered into the ADC. Enable 29 29 + reference buffering if the provided reference source has dynamic high 30 30 + impedance output. Note the absolute voltage allowed on REFINn+ and REFINn- 31 31 + inputs is from AVSS - 50 mV to AVDD + 50 mV when the reference buffers are 32 32 + disabled but narrows to AVSS to AVDD when reference buffering is enabled 33 33 + or in precharge mode. 34 34 + $ref: /schemas/types.yaml#/definitions/string 35 35 + enum: [ precharge, full, disabled ] 36 36 + default: full 37 37 + 38 38 + properties: 39 39 + compatible: 40 40 + enum: 41 41 + - adi,ad4170-4 42 42 + - adi,ad4190-4 43 43 + - adi,ad4195-4 44 44 + 45 45 + avss-supply: 46 46 + description: 47 47 + Reference voltage supply for AVSS. A −2.625V minimum and 0V maximum supply 48 48 + that powers the chip. If not provided, AVSS is assumed to be at system 49 49 + ground (0V). 50 50 + 51 51 + avdd-supply: 52 52 + description: 53 53 + A supply of 4.75V to 5.25V relative to AVSS that powers the chip (AVDD). 54 54 + 55 55 + iovdd-supply: 56 56 + description: 1.7V to 5.25V reference supply to the serial interface (IOVDD). 57 57 + 58 58 + refin1p-supply: 59 59 + description: REFIN+ supply that can be used as reference for conversion. 60 60 + 61 61 + refin1n-supply: 62 62 + description: REFIN- supply that can be used as reference for conversion. 63 63 + 64 64 + refin2p-supply: 65 65 + description: REFIN2+ supply that can be used as reference for conversion. 66 66 + 67 67 + refin2n-supply: 68 68 + description: REFIN2- supply that can be used as reference for conversion. 69 69 + 70 70 + spi-cpol: true 71 71 + 72 72 + spi-cpha: true 73 73 + 74 74 + interrupts: 75 75 + description: 76 76 + Interrupt for signaling the completion of conversion results. The data 77 77 + ready signal (RDY) used as interrupt is by default provided on the SDO 78 78 + pin. Alternatively, it can be provided on the DIG_AUX1 pin in which case 79 79 + the chip disables the RDY function on SDO. Thus, there can be only one 80 80 + data ready interrupt enabled at a time. 81 81 + 82 82 + interrupt-names: 83 83 + description: 84 84 + Specify which pin should be configured as Data Ready interrupt. 85 85 + enum: 86 86 + - sdo 87 87 + - dig_aux1 88 88 + 89 89 + clocks: 90 90 + maxItems: 1 91 91 + description: 92 92 + Optional external clock source. Can specify either an external clock or 93 93 + external crystal. 94 94 + 95 95 + clock-names: 96 96 + enum: 97 97 + - ext-clk 98 98 + - xtal 99 99 + default: ext-clk 100 100 + 101 101 + '#clock-cells': 102 102 + const: 0 103 103 + 104 104 + clock-output-names: 105 105 + maxItems: 1 106 106 + 107 107 + gpio-controller: true 108 108 + 109 109 + "#gpio-cells": 110 110 + const: 2 111 111 + description: | 112 112 + The first cell is for the GPIO number: 0 to 3. 113 113 + The second cell takes standard GPIO flags. 114 114 + 115 115 + ldac-gpios: 116 116 + description: 117 117 + GPIO connected to DIG_AUX2 pin to be used as LDAC toggle to control the 118 118 + transfer of data from the DAC_INPUT_A register to the DAC. 119 119 + maxItems: 1 120 120 + 121 121 + '#address-cells': 122 122 + const: 1 123 123 + 124 124 + '#size-cells': 125 125 + const: 0 126 126 + 127 127 + adi,vbias-pins: 128 128 + description: Analog inputs to apply a voltage bias of (AVDD − AVSS) / 2 to. 129 129 + $ref: /schemas/types.yaml#/definitions/uint32-array 130 130 + minItems: 1 131 131 + maxItems: 9 132 132 + items: 133 133 + minimum: 0 134 134 + maximum: 8 135 135 + 136 136 + allOf: 137 137 + # Some devices don't have integrated DAC 138 138 + - if: 139 139 + properties: 140 140 + compatible: 141 141 + contains: 142 142 + enum: 143 143 + - adi,ad4190-4 144 144 + - adi,ad4195-4 145 145 + then: 146 146 + properties: 147 147 + ldac-gpios: false 148 148 + 149 149 + # Require to specify the interrupt pin when using interrupts 150 150 + - if: 151 151 + required: 152 152 + - interrupts 153 153 + then: 154 154 + required: 155 155 + - interrupt-names 156 156 + 157 157 + # If an external clock is set, the internal clock cannot go out and vice versa 158 158 + - oneOf: 159 159 + - required: [clocks] 160 160 + properties: 161 161 + '#clock-cells': false 162 162 + - required: ['#clock-cells'] 163 163 + properties: 164 164 + clocks: false 165 165 + 166 166 + required: 167 167 + - compatible 168 168 + - reg 169 169 + - avdd-supply 170 170 + - iovdd-supply 171 171 + - spi-cpol 172 172 + - spi-cpha 173 173 + 174 174 + unevaluatedProperties: false 175 175 + 176 176 + patternProperties: 177 177 + "^channel@[0-9a-f]$": 178 178 + $ref: /schemas/iio/adc/adc.yaml# 179 179 + unevaluatedProperties: false 180 180 + description: 181 181 + Represents the external channels which are connected to the ADC. 182 182 + 183 183 + properties: 184 184 + reg: 185 185 + description: 186 186 + The channel number. 187 187 + minimum: 0 188 188 + maximum: 15 189 189 + 190 190 + diff-channels: 191 191 + description: | 192 192 + This property is used for defining the inputs of a differential 193 193 + voltage channel. The first value is the positive input and the second 194 194 + value is the negative input of the channel. 195 195 + 196 196 + Besides the analog input pins AIN0 to AIN8, there are special inputs 197 197 + that can be selected with the following values: 198 198 + 17: Internal temperature sensor 199 199 + 18: (AVDD-AVSS)/5 200 200 + 19: (IOVDD-DGND)/5 201 201 + 20: DAC output 202 202 + 21: ALDO 203 203 + 22: DLDO 204 204 + 23: AVSS 205 205 + 24: DGND 206 206 + 25: REFIN+ 207 207 + 26: REFIN- 208 208 + 27: REFIN2+ 209 209 + 28: REFIN2- 210 210 + 29: REFOUT 211 211 + For the internal temperature sensor, use the input number for both 212 212 + inputs (i.e. diff-channels = <17 17>). 213 213 + items: 214 214 + enum: [0, 1, 2, 3, 4, 5, 6, 7, 8, 17, 18, 19, 20, 21, 22, 23, 24, 25, 215 215 + 26, 27, 28, 29] 216 216 + 217 217 + adi,reference-select: 218 218 + description: | 219 219 + Select the reference source to use when converting on the 220 220 + specific channel. Valid values are: 221 221 + 0: REFIN+/REFIN- 222 222 + 1: REFIN2+/REFIN2− 223 223 + 2: REFOUT/AVSS (internal reference) 224 224 + 3: AVDD/AVSS 225 225 + If not specified, REFOUT/AVSS is used. 226 226 + $ref: /schemas/types.yaml#/definitions/uint32 227 227 + enum: [0, 1, 2, 3] 228 228 + default: 1 229 229 + 230 230 + adi,positive-reference-buffer: 231 231 + $ref: '#/$defs/reference-buffer' 232 232 + 233 233 + adi,negative-reference-buffer: 234 234 + $ref: '#/$defs/reference-buffer' 235 235 + 236 236 + adi,sensor-type: 237 237 + description: 238 238 + The AD4170-4 and similar designs have features to aid interfacing with 239 239 + load cell weigh scale, RTD, and thermocouple sensors. Each of those 240 240 + sensor types requires either distinct wiring configuration or 241 241 + external circuitry for proper sensor operation and can use different 242 242 + ADC chip functionality on their setups. A key characteristic of those 243 243 + external sensors is that they must be excited either by voltage supply 244 244 + or by ADC chip excitation signals. The sensor can then be read through 245 245 + a pair of analog inputs. This property specifies which particular 246 246 + sensor type is connected to the ADC so it can be properly setup and 247 247 + handled. Omit this property for conventional (not weigh scale, RTD, or 248 248 + thermocouple) ADC channel setups. 249 249 + $ref: /schemas/types.yaml#/definitions/string 250 250 + enum: [ weighscale, rtd, thermocouple ] 251 251 + 252 252 + adi,excitation-pin-0: 253 253 + description: 254 254 + Analog input to apply excitation current to while the channel 255 255 + is active. 256 256 + $ref: /schemas/types.yaml#/definitions/uint32 257 257 + minimum: 0 258 258 + maximum: 20 259 259 + default: 0 260 260 + 261 261 + adi,excitation-pin-1: 262 262 + description: 263 263 + Analog input to apply excitation current to while the channel 264 264 + is active. 265 265 + $ref: /schemas/types.yaml#/definitions/uint32 266 266 + minimum: 0 267 267 + maximum: 20 268 268 + default: 0 269 269 + 270 270 + adi,excitation-pin-2: 271 271 + description: 272 272 + Analog input to apply excitation current to while the channel 273 273 + is active. 274 274 + $ref: /schemas/types.yaml#/definitions/uint32 275 275 + minimum: 0 276 276 + maximum: 20 277 277 + default: 0 278 278 + 279 279 + adi,excitation-pin-3: 280 280 + description: 281 281 + Analog input to apply excitation current to while the channel 282 282 + is active. 283 283 + $ref: /schemas/types.yaml#/definitions/uint32 284 284 + minimum: 0 285 285 + maximum: 20 286 286 + default: 0 287 287 + 288 288 + adi,excitation-current-0-microamp: 289 289 + description: 290 290 + Excitation current in microamperes to be applied to pin specified in 291 291 + adi,excitation-pin-0 while this channel is active. 292 292 + enum: [0, 10, 50, 100, 250, 500, 1000, 1500] 293 293 + default: 0 294 294 + 295 295 + adi,excitation-current-1-microamp: 296 296 + description: 297 297 + Excitation current in microamperes to be applied to pin specified in 298 298 + adi,excitation-pin-1 while this channel is active. 299 299 + enum: [0, 10, 50, 100, 250, 500, 1000, 1500] 300 300 + default: 0 301 301 + 302 302 + adi,excitation-current-2-microamp: 303 303 + description: 304 304 + Excitation current in microamperes to be applied to pin specified in 305 305 + adi,excitation-pin-2 while this channel is active. 306 306 + enum: [0, 10, 50, 100, 250, 500, 1000, 1500] 307 307 + default: 0 308 308 + 309 309 + adi,excitation-current-3-microamp: 310 310 + description: 311 311 + Excitation current in microamperes to be applied to pin specified in 312 312 + adi,excitation-pin-3 while this channel is active. 313 313 + enum: [0, 10, 50, 100, 250, 500, 1000, 1500] 314 314 + default: 0 315 315 + 316 316 + adi,excitation-ac: 317 317 + type: boolean 318 318 + description: 319 319 + Whether the external sensor has to be AC or DC excited. When omitted, 320 320 + it is DC excited. 321 321 + 322 322 + allOf: 323 323 + - oneOf: 324 324 + - required: [single-channel, common-mode-channel] 325 325 + properties: 326 326 + diff-channels: false 327 327 + - required: [diff-channels] 328 328 + properties: 329 329 + single-channel: false 330 330 + common-mode-channel: false 331 331 + # Usual ADC channels don't need external circuitry excitation. 332 332 + - if: 333 333 + not: 334 334 + required: 335 335 + - adi,sensor-type 336 336 + then: 337 337 + properties: 338 338 + adi,excitation-pin-0: false 339 339 + adi,excitation-pin-1: false 340 340 + adi,excitation-pin-2: false 341 341 + adi,excitation-pin-3: false 342 342 + adi,excitation-current-0-microamp: false 343 343 + adi,excitation-current-1-microamp: false 344 344 + adi,excitation-current-2-microamp: false 345 345 + adi,excitation-current-3-microamp: false 346 346 + adi,excitation-ac: false 347 347 + # Weigh scale bridge AC excited with one pair of predefined signals. 348 348 + - if: 349 349 + allOf: 350 350 + - properties: 351 351 + adi,sensor-type: 352 352 + contains: 353 353 + const: weighscale 354 354 + - required: 355 355 + - adi,excitation-ac 356 356 + - adi,excitation-pin-2 357 357 + - adi,excitation-pin-3 358 358 + - not: 359 359 + required: 360 360 + - adi,excitation-current-2-microamp 361 361 + - adi,excitation-current-3-microamp 362 362 + then: 363 363 + properties: 364 364 + adi,excitation-pin-2: 365 365 + const: 19 366 366 + adi,excitation-pin-3: 367 367 + const: 20 368 368 + # Weigh scale bridge AC excited with two pairs of predefined signals. 369 369 + - if: 370 370 + allOf: 371 371 + - properties: 372 372 + adi,sensor-type: 373 373 + contains: 374 374 + const: weighscale 375 375 + - required: 376 376 + - adi,excitation-ac 377 377 + - adi,excitation-pin-0 378 378 + - adi,excitation-pin-1 379 379 + - adi,excitation-pin-2 380 380 + - adi,excitation-pin-3 381 381 + - not: 382 382 + required: 383 383 + - adi,excitation-current-0-microamp 384 384 + - adi,excitation-current-1-microamp 385 385 + - adi,excitation-current-2-microamp 386 386 + - adi,excitation-current-3-microamp 387 387 + then: 388 388 + properties: 389 389 + adi,excitation-pin-0: 390 390 + const: 17 391 391 + adi,excitation-pin-1: 392 392 + const: 18 393 393 + adi,excitation-pin-2: 394 394 + const: 19 395 395 + adi,excitation-pin-3: 396 396 + const: 20 397 397 + 398 398 + examples: 399 399 + - | 400 400 + #include <dt-bindings/interrupt-controller/irq.h> 401 401 + spi { 402 402 + #address-cells = <1>; 403 403 + #size-cells = <0>; 404 404 + 405 405 + adc@0 { 406 406 + compatible = "adi,ad4170-4"; 407 407 + reg = <0>; 408 408 + spi-max-frequency = <20000000>; 409 409 + spi-cpol; 410 410 + spi-cpha; 411 411 + avdd-supply = <&avdd>; 412 412 + iovdd-supply = <&iovdd>; 413 413 + clocks = <&clk>; 414 414 + clock-names = "xtal"; 415 415 + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; 416 416 + interrupt-names = "dig_aux1"; 417 417 + adi,vbias-pins = <8>; 418 418 + #address-cells = <1>; 419 419 + #size-cells = <0>; 420 420 + 421 421 + // Sample AIN0 with respect to DGND throughout AVDD/DGND input range 422 422 + // Pseudo-differential unipolar 423 423 + channel@0 { 424 424 + reg = <0>; 425 425 + single-channel = <0>; 426 426 + common-mode-channel = <24>; 427 427 + adi,reference-select = <3>; 428 428 + }; 429 429 + // Weigh scale sensor 430 430 + channel@1 { 431 431 + reg = <1>; 432 432 + bipolar; 433 433 + diff-channels = <1 2>; 434 434 + adi,reference-select = <0>; 435 435 + adi,positive-reference-buffer = "precharge"; 436 436 + adi,negative-reference-buffer = "precharge"; 437 437 + adi,sensor-type = "weighscale"; 438 438 + adi,excitation-pin-2 = <19>; 439 439 + adi,excitation-pin-3 = <20>; 440 440 + adi,excitation-ac; 441 441 + }; 442 442 + // RTD sensor 443 443 + channel@2 { 444 444 + reg = <2>; 445 445 + bipolar; 446 446 + diff-channels = <3 4>; 447 447 + adi,reference-select = <0>; 448 448 + adi,sensor-type = "rtd"; 449 449 + adi,excitation-pin-0 = <5>; 450 450 + adi,excitation-pin-1 = <6>; 451 451 + adi,excitation-current-0-microamp = <500>; 452 452 + adi,excitation-current-1-microamp = <500>; 453 453 + adi,excitation-ac; 454 454 + }; 455 455 + // Thermocouple sensor 456 456 + channel@3 { 457 457 + reg = <3>; 458 458 + bipolar; 459 459 + diff-channels = <7 8>; 460 460 + adi,reference-select = <0>; 461 461 + adi,sensor-type = "thermocouple"; 462 462 + adi,excitation-pin-0 = <18>; 463 463 + adi,excitation-current-0-microamp = <500>; 464 464 + }; 465 465 + }; 466 466 + }; 467 467 + - | 468 468 + #include <dt-bindings/interrupt-controller/irq.h> 469 469 + spi { 470 470 + #address-cells = <1>; 471 471 + #size-cells = <0>; 472 472 + 473 473 + adc@0 { 474 474 + compatible = "adi,ad4170-4"; 475 475 + reg = <0>; 476 476 + spi-max-frequency = <20000000>; 477 477 + spi-cpol; 478 478 + spi-cpha; 479 479 + avdd-supply = <&avdd>; 480 480 + iovdd-supply = <&iovdd>; 481 481 + #clock-cells = <0>; 482 482 + clock-output-names = "ad4170-clk16mhz"; 483 483 + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; 484 484 + interrupt-names = "dig_aux1"; 485 485 + #address-cells = <1>; 486 486 + #size-cells = <0>; 487 487 + 488 488 + // Sample AIN0 with respect to AIN1 throughout AVDD/AVSS input range 489 489 + // Differential bipolar. If AVSS < 0V, differential true bipolar 490 490 + channel@0 { 491 491 + reg = <0>; 492 492 + bipolar; 493 493 + diff-channels = <0 1>; 494 494 + adi,reference-select = <3>; 495 495 + }; 496 496 + // Sample AIN2 with respect to DGND throughout AVDD/DGND input range 497 497 + // Pseudo-differential unipolar 498 498 + channel@1 { 499 499 + reg = <1>; 500 500 + single-channel = <2>; 501 501 + common-mode-channel = <24>; 502 502 + adi,reference-select = <3>; 503 503 + }; 504 504 + // Sample AIN3 with respect to 2.5V throughout AVDD/AVSS input range 505 505 + // Pseudo-differential bipolar 506 506 + channel@2 { 507 507 + reg = <2>; 508 508 + bipolar; 509 509 + single-channel = <3>; 510 510 + common-mode-channel = <29>; 511 511 + adi,reference-select = <3>; 512 512 + }; 513 513 + // Sample AIN4 with respect to DGND throughout AVDD/AVSS input range 514 514 + // Pseudo-differential bipolar 515 515 + channel@3 { 516 516 + reg = <3>; 517 517 + bipolar; 518 518 + single-channel = <4>; 519 519 + common-mode-channel = <24>; 520 520 + adi,reference-select = <3>; 521 521 + }; 522 522 + // Sample AIN5 with respect to 2.5V throughout AVDD/AVSS input range 523 523 + // Pseudo-differential unipolar (AD4170-4 datasheet page 46 example) 524 524 + channel@4 { 525 525 + reg = <4>; 526 526 + single-channel = <5>; 527 527 + common-mode-channel = <29>; 528 528 + adi,reference-select = <3>; 529 529 + }; 530 530 + // Sample AIN6 with respect to 2.5V throughout REFIN+/REFIN- input range 531 531 + // Pseudo-differential bipolar 532 532 + channel@5 { 533 533 + reg = <5>; 534 534 + bipolar; 535 535 + single-channel = <6>; 536 536 + common-mode-channel = <29>; 537 537 + adi,reference-select = <0>; 538 538 + }; 539 539 + // Weigh scale sensor 540 540 + channel@6 { 541 541 + reg = <6>; 542 542 + bipolar; 543 543 + diff-channels = <7 8>; 544 544 + adi,reference-select = <0>; 545 545 + adi,sensor-type = "weighscale"; 546 546 + adi,excitation-pin-0 = <17>; 547 547 + adi,excitation-pin-1 = <18>; 548 548 + adi,excitation-pin-2 = <19>; 549 549 + adi,excitation-pin-3 = <20>; 550 550 + adi,excitation-ac; 551 551 + }; 552 552 + }; 553 553 + }; 554 554 + ...

+2

Documentation/devicetree/bindings/iio/adc/adi,ad4851.yaml

reviewed

··· 69 69 spi-max-frequency: 70 70 maximum: 25000000 71 71 72 72 + spi-3wire: true 73 73 + 72 74 '#address-cells': 73 75 const: 1 74 76

+60

Documentation/devicetree/bindings/iio/adc/adi,ad7405.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 + # Copyright 2025 Analog Devices Inc. 3 3 + %YAML 1.2 4 4 + --- 5 5 + $id: http://devicetree.org/schemas/iio/adc/adi,ad7405.yaml# 6 6 + $schema: http://devicetree.org/meta-schemas/core.yaml# 7 7 + 8 8 + title: Analog Devices AD7405 family 9 9 + 10 10 + maintainers: 11 11 + - Dragos Bogdan <dragos.bogdan@analog.com> 12 12 + - Pop Ioan Daniel <pop.ioan-daniel@analog.com> 13 13 + 14 14 + description: | 15 15 + Analog Devices AD7405 is a high performance isolated ADC, 1-channel, 16 16 + 16-bit with a second-order Σ-Δ modulator that converts an analog input signal 17 17 + into a high speed, single-bit data stream. 18 18 + 19 19 + https://www.analog.com/media/en/technical-documentation/data-sheets/ad7405.pdf 20 20 + https://www.analog.com/media/en/technical-documentation/data-sheets/adum7701.pdf 21 21 + https://www.analog.com/media/en/technical-documentation/data-sheets/adum7702.pdf 22 22 + https://www.analog.com/media/en/technical-documentation/data-sheets/ADuM7703.pdf 23 23 + 24 24 + properties: 25 25 + compatible: 26 26 + enum: 27 27 + - adi,ad7405 28 28 + - adi,adum7701 29 29 + - adi,adum7702 30 30 + - adi,adum7703 31 31 + 32 32 + clocks: 33 33 + maxItems: 1 34 34 + 35 35 + vdd1-supply: true 36 36 + 37 37 + vdd2-supply: true 38 38 + 39 39 + io-backends: 40 40 + maxItems: 1 41 41 + 42 42 + required: 43 43 + - compatible 44 44 + - clocks 45 45 + - vdd1-supply 46 46 + - vdd2-supply 47 47 + - io-backends 48 48 + 49 49 + additionalProperties: false 50 50 + 51 51 + examples: 52 52 + - | 53 53 + adc { 54 54 + compatible = "adi,ad7405"; 55 55 + clocks = <&axi_clk_gen 0>; 56 56 + vdd1-supply = <&vdd1>; 57 57 + vdd2-supply = <&vdd2>; 58 58 + io-backends = <&axi_adc>; 59 59 + }; 60 60 + ...

+29

Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml

reviewed

··· 204 204 considered a bipolar differential channel. Otherwise it is bipolar 205 205 single-ended. 206 206 207 207 + adi,rfilter-ohms: 208 208 + description: 209 209 + For ADCs that supports gain calibration, this property must be set to 210 210 + the value of the external RFilter resistor. Proper gain error 211 211 + correction is applied based on this value. 212 212 + default: 0 213 213 + minimum: 0 214 214 + maximum: 64512 215 215 + 207 216 required: 208 217 - reg 209 218 - bipolar ··· 264 255 then: 265 256 properties: 266 257 adi,oversampling-ratio-gpios: false 258 258 + 259 259 + - if: 260 260 + properties: 261 261 + compatible: 262 262 + contains: 263 263 + enum: 264 264 + - adi,ad7605-4 265 265 + - adi,ad7606-4 266 266 + - adi,ad7606-6 267 267 + - adi,ad7606-8 268 268 + - adi,ad7607 269 269 + - adi,ad7608 270 270 + - adi,ad7609 271 271 + - adi,ad7616 272 272 + then: 273 273 + patternProperties: 274 274 + "^channel@[0-9a-f]+$": 275 275 + properties: 276 276 + adi,rfilter-ohms: false 267 277 268 278 - if: 269 279 properties: ··· 426 398 reg = <8>; 427 399 diff-channels = <8 8>; 428 400 bipolar; 401 401 + adi,rfilter-ohms = <2048>; 429 402 }; 430 403 431 404 };

+67 -1

Documentation/devicetree/bindings/iio/adc/adi,ad7768-1.yaml

reviewed

··· 26 26 clock-names: 27 27 const: mclk 28 28 29 29 + trigger-sources: 30 30 + $ref: /schemas/types.yaml#/definitions/phandle-array 31 31 + minItems: 1 32 32 + maxItems: 2 33 33 + description: | 34 34 + A list of phandles referencing trigger source providers. Each entry 35 35 + represents a trigger source for the ADC: 36 36 + 37 37 + - First entry specifies the device responsible for driving the 38 38 + synchronization (SYNC_IN) pin, as an alternative to adi,sync-in-gpios. 39 39 + This can be a `gpio-trigger` or another `ad7768-1` device. If the 40 40 + device's own SYNC_OUT pin is internally connected to its SYNC_IN pin, 41 41 + reference the device itself or omit this property. 42 42 + - Second entry optionally defines a GPIO3 pin used as a START signal trigger. 43 43 + 44 44 + Use the accompanying trigger source cell to identify the type of each entry. 45 45 + 29 46 interrupts: 47 47 + description: 48 48 + DRDY (Data Ready) pin, which signals conversion results are available. 30 49 maxItems: 1 31 50 32 51 '#address-cells': ··· 66 47 in any way, for example if the filter decimation rate changes. 67 48 As the line is active low, it should be marked GPIO_ACTIVE_LOW. 68 49 50 50 + regulators: 51 51 + type: object 52 52 + description: 53 53 + list of regulators provided by this controller. 54 54 + 55 55 + properties: 56 56 + vcm-output: 57 57 + $ref: /schemas/regulator/regulator.yaml# 58 58 + type: object 59 59 + unevaluatedProperties: false 60 60 + 61 61 + additionalProperties: false 62 62 + 69 63 reset-gpios: 70 64 maxItems: 1 71 65 ··· 89 57 "#io-channel-cells": 90 58 const: 1 91 59 60 60 + "#trigger-source-cells": 61 61 + description: | 62 62 + Cell indicates the trigger output signal: 0 = SYNC_OUT, 1 = GPIO3, 63 63 + 2 = DRDY. 64 64 + 65 65 + For better readability, macros for these values are available in 66 66 + dt-bindings/iio/adc/adi,ad7768-1.h. 67 67 + const: 1 68 68 + 69 69 + gpio-controller: true 70 70 + 71 71 + "#gpio-cells": 72 72 + const: 2 73 73 + description: | 74 74 + The first cell is for the GPIO number: 0 to 3. 75 75 + The second cell takes standard GPIO flags. 76 76 + 92 77 required: 93 78 - compatible 94 79 - reg ··· 114 65 - vref-supply 115 66 - spi-cpol 116 67 - spi-cpha 117 117 - - adi,sync-in-gpios 68 68 + 69 69 + dependencies: 70 70 + adi,sync-in-gpios: 71 71 + not: 72 72 + required: 73 73 + - trigger-sources 74 74 + trigger-sources: 75 75 + not: 76 76 + required: 77 77 + - adi,sync-in-gpios 118 78 119 79 patternProperties: 120 80 "^channel@([0-9]|1[0-5])$": ··· 163 105 spi-max-frequency = <2000000>; 164 106 spi-cpol; 165 107 spi-cpha; 108 108 + gpio-controller; 109 109 + #gpio-cells = <2>; 166 110 vref-supply = <&adc_vref>; 167 111 interrupts = <25 IRQ_TYPE_EDGE_RISING>; 168 112 interrupt-parent = <&gpio>; ··· 179 119 channel@0 { 180 120 reg = <0>; 181 121 label = "channel_0"; 122 122 + }; 123 123 + 124 124 + regulators { 125 125 + vcm_reg: vcm-output { 126 126 + regulator-name = "ad7768-1-vcm"; 127 127 + }; 182 128 }; 183 129 }; 184 130 };

+2

Documentation/devicetree/bindings/iio/adc/adi,axi-adc.yaml

reviewed

··· 27 27 the ad7606 family. 28 28 29 29 https://wiki.analog.com/resources/fpga/docs/axi_adc_ip 30 30 + https://analogdevicesinc.github.io/hdl/library/axi_ad408x/index.html 30 31 https://analogdevicesinc.github.io/hdl/library/axi_ad485x/index.html 31 32 http://analogdevicesinc.github.io/hdl/library/axi_ad7606x/index.html 32 33 ··· 35 34 compatible: 36 35 enum: 37 36 - adi,axi-adc-10.0.a 37 37 + - adi,axi-ad408x 38 38 - adi,axi-ad7606x 39 39 - adi,axi-ad485x 40 40

+4

Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml

reviewed

··· 34 34 - const: mediatek,mt2701-auxadc 35 35 - items: 36 36 - enum: 37 37 + - mediatek,mt7981-auxadc 38 38 + - const: mediatek,mt7986-auxadc 39 39 + - items: 40 40 + - enum: 37 41 - mediatek,mt6893-auxadc 38 42 - mediatek,mt8183-auxadc 39 43 - mediatek,mt8186-auxadc

+2

Documentation/devicetree/bindings/iio/adc/mediatek,mt6359-auxadc.yaml

reviewed

··· 22 22 - mediatek,mt6357-auxadc 23 23 - mediatek,mt6358-auxadc 24 24 - mediatek,mt6359-auxadc 25 25 + - mediatek,mt6363-auxadc 26 26 + - mediatek,mt6373-auxadc 25 27 26 28 "#io-channel-cells": 27 29 const: 1

+3

Documentation/devicetree/bindings/iio/adc/nxp,lpc3220-adc.yaml

reviewed

··· 22 22 interrupts: 23 23 maxItems: 1 24 24 25 25 + clocks: 26 26 + maxItems: 1 27 27 + 25 28 vref-supply: true 26 29 27 30 "#io-channel-cells":

+69

Documentation/devicetree/bindings/iio/adc/st,spear600-adc.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/iio/adc/st,spear600-adc.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: ST SPEAr ADC device driver 8 8 + 9 9 + maintainers: 10 10 + - Jonathan Cameron <jic23@kernel.org> 11 11 + 12 12 + description: | 13 13 + Integrated ADC inside the ST SPEAr SoC, SPEAr600, supporting 14 14 + 10-bit resolution. Datasheet can be found here: 15 15 + https://www.st.com/resource/en/datasheet/spear600.pdf 16 16 + 17 17 + properties: 18 18 + compatible: 19 19 + enum: 20 20 + - st,spear600-adc 21 21 + 22 22 + reg: 23 23 + maxItems: 1 24 24 + 25 25 + interrupts: 26 26 + maxItems: 1 27 27 + 28 28 + sampling-frequency: 29 29 + $ref: /schemas/types.yaml#/definitions/uint32 30 30 + minimum: 2500000 31 31 + maximum: 20000000 32 32 + description: 33 33 + Default sampling frequency of the ADC in Hz. 34 34 + 35 35 + vref-external: 36 36 + $ref: /schemas/types.yaml#/definitions/uint32 37 37 + minimum: 1000 38 38 + maximum: 2800 39 39 + description: 40 40 + External voltage reference in milli-volts. If omitted the internal voltage 41 41 + reference will be used. 42 42 + 43 43 + average-samples: 44 44 + $ref: /schemas/types.yaml#/definitions/uint32 45 45 + minimum: 0 46 46 + maximum: 15 47 47 + default: 0 48 48 + description: 49 49 + Number of samples to generate an average value. If omitted, single data 50 50 + conversion will be used. 51 51 + 52 52 + required: 53 53 + - compatible 54 54 + - reg 55 55 + - interrupts 56 56 + - sampling-frequency 57 57 + 58 58 + additionalProperties: false 59 59 + 60 60 + examples: 61 61 + - | 62 62 + adc@d8200000 { 63 63 + compatible = "st,spear600-adc"; 64 64 + reg = <0xd8200000 0x1000>; 65 65 + interrupt-parent = <&vic1>; 66 66 + interrupts = <6>; 67 67 + sampling-frequency = <5000000>; 68 68 + vref-external = <2500>; /* 2.5V VRef */ 69 69 + };

+59

Documentation/devicetree/bindings/iio/gyroscope/invensense,itg3200.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/iio/gyroscope/invensense,itg3200.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: Invensense ITG-3200 Gyroscope 8 8 + 9 9 + maintainers: 10 10 + - Jonathan Cameron <jic23@kernel.org> 11 11 + 12 12 + description: | 13 13 + Triple-axis, digital output gyroscope with a three 16-bit analog-to-digital 14 14 + converters (ADCs) for digitizing the gyro outputs, a user-selectable internal 15 15 + low-pass filter bandwidth, and a Fast-Mode I2C. 16 16 + 17 17 + properties: 18 18 + compatible: 19 19 + const: invensense,itg3200 20 20 + 21 21 + reg: 22 22 + maxItems: 1 23 23 + 24 24 + vdd-supply: true 25 25 + 26 26 + vlogic-supply: true 27 27 + 28 28 + interrupts: 29 29 + maxItems: 1 30 30 + 31 31 + mount-matrix: 32 32 + description: an optional 3x3 mounting rotation matrix. 33 33 + 34 34 + clocks: 35 35 + maxItems: 1 36 36 + 37 37 + clock-names: 38 38 + items: 39 39 + - const: ext_clock 40 40 + 41 41 + required: 42 42 + - compatible 43 43 + - reg 44 44 + 45 45 + additionalProperties: false 46 46 + 47 47 + examples: 48 48 + - | 49 49 + #include <dt-bindings/interrupt-controller/irq.h> 50 50 + i2c { 51 51 + #address-cells = <1>; 52 52 + #size-cells = <0>; 53 53 + gyroscope@68 { 54 54 + compatible = "invensense,itg3200"; 55 55 + reg = <0x68>; 56 56 + interrupt-parent = <&gpio2>; 57 57 + interrupts = <24 IRQ_TYPE_EDGE_FALLING>; 58 58 + }; 59 59 + };

+62

Documentation/devicetree/bindings/iio/proximity/nicera,d3323aa.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/iio/proximity/nicera,d3323aa.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: Nicera D3-323-AA PIR sensor 8 8 + 9 9 + maintainers: 10 10 + - Waqar Hameed <waqar.hameed@axis.com> 11 11 + 12 12 + description: | 13 13 + PIR sensor for human detection. 14 14 + Datasheet: https://www.endrich.com/Datenbl%C3%A4tter/Sensoren/D3-323-AA_e.pdf 15 15 + 16 16 + properties: 17 17 + compatible: 18 18 + const: nicera,d3323aa 19 19 + 20 20 + vdd-supply: 21 21 + description: 22 22 + Supply voltage (1.8 to 5.5 V). 23 23 + 24 24 + vout-clk-gpios: 25 25 + maxItems: 1 26 26 + description: 27 27 + GPIO for clock and detection. 28 28 + After reset, the device signals with two falling edges on this pin that it 29 29 + is ready for configuration (within 1.2 s). 30 30 + During configuration, it is used as clock for data reading and writing (on 31 31 + data-gpios). 32 32 + After all this, when device is in operational mode, it signals on this pin 33 33 + for any detections. 34 34 + 35 35 + data-gpios: 36 36 + maxItems: 1 37 37 + description: 38 38 + GPIO for data reading and writing. This is denoted "DO (SI)" in datasheet. 39 39 + During configuration, this pin is used for writing and reading 40 40 + configuration data (together with vout-clk-gpios as clock). 41 41 + After this, during operational mode, the device will output serial data on 42 42 + this GPIO. 43 43 + 44 44 + required: 45 45 + - compatible 46 46 + - vdd-supply 47 47 + - vout-clk-gpios 48 48 + - data-gpios 49 49 + 50 50 + additionalProperties: false 51 51 + 52 52 + examples: 53 53 + - | 54 54 + #include <dt-bindings/gpio/gpio.h> 55 55 + 56 56 + proximity { 57 57 + compatible = "nicera,d3323aa"; 58 58 + vdd-supply = <&regulator_3v3>; 59 59 + vout-clk-gpios = <&gpio 78 GPIO_ACTIVE_HIGH>; 60 60 + data-gpios = <&gpio 76 GPIO_ACTIVE_HIGH>; 61 61 + }; 62 62 + ...

-24

Documentation/devicetree/bindings/staging/iio/adc/spear-adc.txt

reviewed

··· 1 1 - * ST SPEAr ADC device driver 2 2 - 3 3 - Required properties: 4 4 - - compatible: Should be "st,spear600-adc" 5 5 - - reg: Address and length of the register set for the device 6 6 - - interrupts: Should contain the ADC interrupt 7 7 - - sampling-frequency: Default sampling frequency 8 8 - 9 9 - Optional properties: 10 10 - - vref-external: External voltage reference in milli-volts. If omitted 11 11 - the internal voltage reference will be used. 12 12 - - average-samples: Number of samples to generate an average value. If 13 13 - omitted, single data conversion will be used. 14 14 - 15 15 - Examples: 16 16 - 17 17 - adc: adc@d8200000 { 18 18 - compatible = "st,spear600-adc"; 19 19 - reg = <0xd8200000 0x1000>; 20 20 - interrupt-parent = <&vic1>; 21 21 - interrupts = <6>; 22 22 - sampling-frequency = <5000000>; 23 23 - vref-external = <2500>; /* 2.5V VRef */ 24 24 - };

+40

Documentation/devicetree/bindings/trigger-source/gpio-trigger.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/trigger-source/gpio-trigger.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: Generic trigger source using GPIO 8 8 + 9 9 + description: A GPIO used as a trigger source. 10 10 + 11 11 + maintainers: 12 12 + - Jonathan Santos <Jonathan.Santos@analog.com> 13 13 + 14 14 + properties: 15 15 + compatible: 16 16 + const: gpio-trigger 17 17 + 18 18 + '#trigger-source-cells': 19 19 + const: 0 20 20 + 21 21 + gpios: 22 22 + maxItems: 1 23 23 + description: GPIO to be used as a trigger source. 24 24 + 25 25 + required: 26 26 + - compatible 27 27 + - '#trigger-source-cells' 28 28 + - gpios 29 29 + 30 30 + additionalProperties: false 31 31 + 32 32 + examples: 33 33 + - | 34 34 + #include <dt-bindings/gpio/gpio.h> 35 35 + 36 36 + trigger { 37 37 + compatible = "gpio-trigger"; 38 38 + #trigger-source-cells = <0>; 39 39 + gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; 40 40 + };

+2

Documentation/devicetree/bindings/vendor-prefixes.yaml

reviewed

··· 1067 1067 description: Next Thing Co. 1068 1068 "^ni,.*": 1069 1069 description: National Instruments 1070 1070 + "^nicera,.*": 1071 1071 + description: Nippon Ceramic Co., Ltd. 1070 1072 "^nintendo,.*": 1071 1073 description: Nintendo 1072 1074 "^nlt,.*":

+293

Documentation/iio/adxl313.rst

reviewed

··· 1 1 + .. SPDX-License-Identifier: GPL-2.0 2 2 + 3 3 + =============== 4 4 + ADXL313 driver 5 5 + =============== 6 6 + 7 7 + This driver supports Analog Device's ADXL313 on SPI/I2C bus. 8 8 + 9 9 + 1. Supported devices 10 10 + ==================== 11 11 + 12 12 + * `ADXL313 <https://www.analog.com/ADXL313>`_ 13 13 + 14 14 + The ADXL313is a low noise density, low power, 3-axis accelerometer with 15 15 + selectable measurement ranges. The ADXL313 supports the ±0.5 g, ±1 g, ±2 g and 16 16 + ±4 g ranges. 17 17 + 18 18 + 2. Device attributes 19 19 + ==================== 20 20 + 21 21 + Accelerometer measurements are always provided. 22 22 + 23 23 + Each IIO device, has a device folder under ``/sys/bus/iio/devices/iio:deviceX``, 24 24 + where X is the IIO index of the device. Under these folders reside a set of 25 25 + device files, depending on the characteristics and features of the hardware 26 26 + device in questions. These files are consistently generalized and documented in 27 27 + the IIO ABI documentation. 28 28 + 29 29 + The following tables show the adxl313 related device files, found in the 30 30 + specific device folder path ``/sys/bus/iio/devices/iio:deviceX``. 31 31 + 32 32 + +---------------------------------------------------+----------------------------------------------------------+ 33 33 + | 3-Axis Accelerometer related device files | Description | 34 34 + +---------------------------------------------------+----------------------------------------------------------+ 35 35 + | in_accel_scale | Scale for the accelerometer channels. | 36 36 + +---------------------------------------------------+----------------------------------------------------------+ 37 37 + | in_accel_x_calibbias | Calibration offset for the X-axis accelerometer channel. | 38 38 + +---------------------------------------------------+----------------------------------------------------------+ 39 39 + | in_accel_x_raw | Raw X-axis accelerometer channel value. | 40 40 + +---------------------------------------------------+----------------------------------------------------------+ 41 41 + | in_accel_y_calibbias | y-axis acceleration offset correction | 42 42 + +---------------------------------------------------+----------------------------------------------------------+ 43 43 + | in_accel_y_raw | Raw Y-axis accelerometer channel value. | 44 44 + +---------------------------------------------------+----------------------------------------------------------+ 45 45 + | in_accel_z_calibbias | Calibration offset for the Z-axis accelerometer channel. | 46 46 + +---------------------------------------------------+----------------------------------------------------------+ 47 47 + | in_accel_z_raw | Raw Z-axis accelerometer channel value. | 48 48 + +---------------------------------------------------+----------------------------------------------------------+ 49 49 + 50 50 + +---------------------------------------+----------------------------------------------+ 51 51 + | Miscellaneous device files | Description | 52 52 + +---------------------------------------+----------------------------------------------+ 53 53 + | name | Name of the IIO device. | 54 54 + +---------------------------------------+----------------------------------------------+ 55 55 + | in_accel_sampling_frequency | Currently selected sample rate. | 56 56 + +---------------------------------------+----------------------------------------------+ 57 57 + | in_accel_sampling_frequency_available | Available sampling frequency configurations. | 58 58 + +---------------------------------------+----------------------------------------------+ 59 59 + 60 60 + The iio event related settings, found in ``/sys/bus/iio/devices/iio:deviceX/events``. 61 61 + 62 62 + +---------------------------------------------------+----------------------------------------------------------+ 63 63 + | in_accel_mag_adaptive_falling_period | AC coupled inactivity time. | 64 64 + +---------------------------------------------------+----------------------------------------------------------+ 65 65 + | in_accel_mag_adaptive_falling_value | AC coupled inactivity threshold. | 66 66 + +---------------------------------------------------+----------------------------------------------------------+ 67 67 + | in_accel_mag_adaptive_rising_value | AC coupled activity threshold. | 68 68 + +---------------------------------------------------+----------------------------------------------------------+ 69 69 + | in_accel_mag_falling_period | Inactivity time. | 70 70 + +---------------------------------------------------+----------------------------------------------------------+ 71 71 + | in_accel_mag_falling_value | Inactivity threshold. | 72 72 + +---------------------------------------------------+----------------------------------------------------------+ 73 73 + | in_accel_mag_rising_value | Activity threshold. | 74 74 + +---------------------------------------------------+----------------------------------------------------------+ 75 75 + | in_accel_x\&y\&z_mag_adaptive_falling_en | Enable or disable AC coupled inactivity events. | 76 76 + +---------------------------------------------------+----------------------------------------------------------+ 77 77 + | in_accel_x\|y\|z_mag_adaptive_rising_en | Enable or disable AC coupled activity events. | 78 78 + +---------------------------------------------------+----------------------------------------------------------+ 79 79 + | in_accel_x\&y\&z_mag_falling_en | Enable or disable inactivity events. | 80 80 + +---------------------------------------------------+----------------------------------------------------------+ 81 81 + | in_accel_x\|y\|z_mag_rising_en | Enable or disable activity events. | 82 82 + +---------------------------------------------------+----------------------------------------------------------+ 83 83 + 84 84 + The default coupling is DC coupled events. In this case the threshold will 85 85 + be in place as such, where for the AC coupled case an adaptive threshold 86 86 + (described in the datasheet) will be applied by the sensor. In general activity, 87 87 + i.e. ``ACTIVITY`` or ``ACTIVITY_AC`` and inactivity i.e. ``INACTIVITY`` or 88 88 + ``INACTIVITY_AC``, will be linked with auto-sleep enabled when both are enabled. 89 89 + This means in particular ``ACTIVITY`` can also be linked to ``INACTIVITY_AC`` 90 90 + and vice versa, without problem. 91 91 + 92 92 + Note here, that ``ACTIVITY`` and ``ACTIVITY_AC`` are mutually exclusive. This 93 93 + means, that the most recent configuration will be set. For instance, if 94 94 + ``ACTIVITY`` is enabled, and ``ACTIVITY_AC`` will be enabled, the sensor driver 95 95 + will have ``ACTIVITY`` disabled, but ``ACTIVITY_AC`` enabled. The same is valid 96 96 + for inactivity. In case of turning off an event, it has to match to what is 97 97 + actually enabled, i.e. enabling ``ACTIVITY_AC`` and then disabling ``ACTIVITY`` 98 98 + is simply ignored as it is already disabled. Or, as if it was any other not 99 99 + enabled event, too. 100 100 + 101 101 + Channels processed values 102 102 + ------------------------- 103 103 + 104 104 + A channel value can be read from its _raw attribute. The value returned is the 105 105 + raw value as reported by the devices. To get the processed value of the channel, 106 106 + apply the following formula: 107 107 + 108 108 + .. code-block:: 109 109 + 110 110 + processed value = (_raw + _offset) * _scale 111 111 + 112 112 + Where _offset and _scale are device attributes. If no _offset attribute is 113 113 + present, simply assume its value is 0. 114 114 + 115 115 + The ADXL313 driver offers data for a single types of channels, the table below 116 116 + shows the measurement units for the processed value, which are defined by the 117 117 + IIO framework: 118 118 + 119 119 + +-------------------------------------+---------------------------+ 120 120 + | Channel type | Measurement unit | 121 121 + +-------------------------------------+---------------------------+ 122 122 + | Acceleration on X, Y, and Z axis | Meters per Second squared | 123 123 + +-------------------------------------+---------------------------+ 124 124 + 125 125 + Usage examples 126 126 + -------------- 127 127 + 128 128 + Show device name: 129 129 + 130 130 + .. code-block:: bash 131 131 + 132 132 + root:/sys/bus/iio/devices/iio:device0> cat name 133 133 + adxl313 134 134 + 135 135 + Show accelerometer channels value: 136 136 + 137 137 + .. code-block:: bash 138 138 + 139 139 + root:/sys/bus/iio/devices/iio:device0> cat in_accel_x_raw 140 140 + 2 141 141 + root:/sys/bus/iio/devices/iio:device0> cat in_accel_y_raw 142 142 + -57 143 143 + root:/sys/bus/iio/devices/iio:device0> cat in_accel_z_raw 144 144 + 2 145 145 + root:/sys/bus/iio/devices/iio:device0> cat in_accel_scale 146 146 + 0.009576806 147 147 + 148 148 + The accelerometer values will be: 149 149 + 150 150 + - X-axis acceleration = in_accel_x_raw * in_accel_scale = 0.0191536 m/s^2 151 151 + - Y-axis acceleration = in_accel_y_raw * in_accel_scale = -0.5458779 m/s^2 152 152 + - Z-axis acceleration = in_accel_z_raw * in_accel_scale = 0.0191536 m/s^2 153 153 + 154 154 + Set calibration offset for accelerometer channels. Note, that the calibration 155 155 + will be rounded according to the graduation of LSB units: 156 156 + 157 157 + .. code-block:: bash 158 158 + 159 159 + root:/sys/bus/iio/devices/iio:device0> cat in_accel_x_calibbias 160 160 + 0 161 161 + 162 162 + root:/sys/bus/iio/devices/iio:device0> echo 50 > in_accel_x_calibbias 163 163 + root:/sys/bus/iio/devices/iio:device0> cat in_accel_x_calibbias 164 164 + 48 165 165 + 166 166 + Set sampling frequency: 167 167 + 168 168 + .. code-block:: bash 169 169 + 170 170 + root:/sys/bus/iio/devices/iio:device0> cat in_accel_sampling_frequency 171 171 + 100.000000 172 172 + root:/sys/bus/iio/devices/iio:device0> cat in_accel_sampling_frequency_available 173 173 + 6.250000 12.500000 25.000000 50.000000 100.000000 200.000000 400.000000 800.000000 1600.000000 3200.000000 174 174 + 175 175 + root:/sys/bus/iio/devices/iio:device0> echo 400 > in_accel_sampling_frequency 176 176 + root:/sys/bus/iio/devices/iio:device0> cat in_accel_sampling_frequency 177 177 + 400.000000 178 178 + 179 179 + 3. Device buffers and triggers 180 180 + ============================== 181 181 + 182 182 + This driver supports IIO buffers. 183 183 + 184 184 + All devices support retrieving the raw acceleration measurements using buffers. 185 185 + 186 186 + Usage examples 187 187 + -------------- 188 188 + 189 189 + Select channels for buffer read: 190 190 + 191 191 + .. code-block:: bash 192 192 + 193 193 + root:/sys/bus/iio/devices/iio:device0> echo 1 > scan_elements/in_accel_x_en 194 194 + root:/sys/bus/iio/devices/iio:device0> echo 1 > scan_elements/in_accel_y_en 195 195 + root:/sys/bus/iio/devices/iio:device0> echo 1 > scan_elements/in_accel_z_en 196 196 + 197 197 + Set the number of samples to be stored in the buffer: 198 198 + 199 199 + .. code-block:: bash 200 200 + 201 201 + root:/sys/bus/iio/devices/iio:device0> echo 10 > buffer/length 202 202 + 203 203 + Enable buffer readings: 204 204 + 205 205 + .. code-block:: bash 206 206 + 207 207 + root:/sys/bus/iio/devices/iio:device0> echo 1 > buffer/enable 208 208 + 209 209 + Obtain buffered data: 210 210 + 211 211 + .. code-block:: bash 212 212 + 213 213 + root:/sys/bus/iio/devices/iio:device0> hexdump -C /dev/iio\:device0 214 214 + ... 215 215 + 000000d0 01 fc 31 00 c7 ff 03 fc 31 00 c7 ff 04 fc 33 00 |..1.....1.....3.| 216 216 + 000000e0 c8 ff 03 fc 32 00 c5 ff ff fc 32 00 c7 ff 0a fc |....2.....2.....| 217 217 + 000000f0 30 00 c8 ff 06 fc 33 00 c7 ff 01 fc 2f 00 c8 ff |0.....3...../...| 218 218 + 00000100 02 fc 32 00 c6 ff 04 fc 33 00 c8 ff 05 fc 33 00 |..2.....3.....3.| 219 219 + 00000110 ca ff 02 fc 31 00 c7 ff 02 fc 30 00 c9 ff 09 fc |....1.....0.....| 220 220 + 00000120 35 00 c9 ff 08 fc 35 00 c8 ff 02 fc 31 00 c5 ff |5.....5.....1...| 221 221 + 00000130 03 fc 32 00 c7 ff 04 fc 32 00 c7 ff 02 fc 31 00 |..2.....2.....1.| 222 222 + 00000140 c7 ff 08 fc 30 00 c7 ff 02 fc 32 00 c5 ff ff fc |....0.....2.....| 223 223 + 00000150 31 00 c5 ff 04 fc 31 00 c8 ff 03 fc 32 00 c8 ff |1.....1.....2...| 224 224 + 00000160 01 fc 31 00 c7 ff 05 fc 31 00 c3 ff 04 fc 31 00 |..1.....1.....1.| 225 225 + 00000170 c5 ff 04 fc 30 00 c7 ff 03 fc 31 00 c9 ff 03 fc |....0.....1.....| 226 226 + ... 227 227 + 228 228 + Enabling activity detection: 229 229 + 230 230 + .. code-block:: bash 231 231 + 232 232 + root:/sys/bus/iio/devices/iio:device0> echo 1.28125 > ./events/in_accel_mag_rising_value 233 233 + root:/sys/bus/iio/devices/iio:device0> echo 1 > ./events/in_accel_x\|y\|z_mag_rising_en 234 234 + 235 235 + root:/sys/bus/iio/devices/iio:device0> iio_event_monitor adxl313 236 236 + Found IIO device with name adxl313 with device number 0 237 237 + <only while moving the sensor> 238 238 + Event: time: 1748795762298351281, type: accel(x|y|z), channel: 0, evtype: mag, direction: rising 239 239 + Event: time: 1748795762302653704, type: accel(x|y|z), channel: 0, evtype: mag, direction: rising 240 240 + Event: time: 1748795762304340726, type: accel(x|y|z), channel: 0, evtype: mag, direction: rising 241 241 + ... 242 242 + 243 243 + Disabling activity detection: 244 244 + 245 245 + .. code-block:: bash 246 246 + 247 247 + root:/sys/bus/iio/devices/iio:device0> echo 0 > ./events/in_accel_x\|y\|z_mag_rising_en 248 248 + root:/sys/bus/iio/devices/iio:device0> iio_event_monitor adxl313 249 249 + <nothing> 250 250 + 251 251 + Enabling inactivity detection: 252 252 + 253 253 + .. code-block:: bash 254 254 + 255 255 + root:/sys/bus/iio/devices/iio:device0> echo 1.234375 > ./events/in_accel_mag_falling_value 256 256 + root:/sys/bus/iio/devices/iio:device0> echo 5 > ./events/in_accel_mag_falling_period 257 257 + root:/sys/bus/iio/devices/iio:device0> echo 1 > ./events/in_accel_x\&y\&z_mag_falling_en 258 258 + 259 259 + root:/sys/bus/iio/devices/iio:device0> iio_event_monitor adxl313 260 260 + Found IIO device with name adxl313 with device number 0 261 261 + Event: time: 1748796324115962975, type: accel(x&y&z), channel: 0, evtype: mag, direction: falling 262 262 + Event: time: 1748796329329981772, type: accel(x&y&z), channel: 0, evtype: mag, direction: falling 263 263 + Event: time: 1748796334543399706, type: accel(x&y&z), channel: 0, evtype: mag, direction: falling 264 264 + ... 265 265 + <every 5s now indicates inactivity> 266 266 + 267 267 + Now, enabling activity, e.g. the AC coupled counter-part ``ACTIVITY_AC`` 268 268 + 269 269 + .. code-block:: bash 270 270 + 271 271 + root:/sys/bus/iio/devices/iio:device0> echo 1.28125 > ./events/in_accel_mag_rising_value 272 272 + root:/sys/bus/iio/devices/iio:device0> echo 1 > ./events/in_accel_x\|y\|z_mag_rising_en 273 273 + 274 274 + root:/sys/bus/iio/devices/iio:device0> iio_event_monitor adxl313 275 275 + Found IIO device with name adxl313 with device number 0 276 276 + <some activity with the sensor> 277 277 + Event: time: 1748796880354686777, type: accel(x|y|z), channel: 0, evtype: mag_adaptive, direction: rising 278 278 + <5s of inactivity, then> 279 279 + Event: time: 1748796885543252017, type: accel(x&y&z), channel: 0, evtype: mag, direction: falling 280 280 + <some other activity detected by accelerating the sensor> 281 281 + Event: time: 1748796887756634678, type: accel(x|y|z), channel: 0, evtype: mag_adaptive, direction: rising 282 282 + <again, 5s of inactivity> 283 283 + Event: time: 1748796892964368352, type: accel(x&y&z), channel: 0, evtype: mag, direction: falling 284 284 + <stays like this until next activity in auto-sleep> 285 285 + 286 286 + Note, when AC coupling is in place, the event type will be of ``mag_adaptive``. 287 287 + AC- or DC-coupled (the default) events are used similarly. 288 288 + 289 289 + 4. IIO Interfacing Tools 290 290 + ======================== 291 291 + 292 292 + See Documentation/iio/iio_tools.rst for the description of the available IIO 293 293 + interfacing tools.

+1

Documentation/iio/index.rst

reviewed

··· 31 31 adis16475 32 32 adis16480 33 33 adis16550 34 34 + adxl313 34 35 adxl380 35 36 bno055 36 37 ep93xx_adc

+19 -2

MAINTAINERS

reviewed

··· 1374 1374 F: Documentation/iio/ad4030.rst 1375 1375 F: drivers/iio/adc/ad4030.c 1376 1376 1377 1377 + ANALOG DEVICES INC AD4080 DRIVER 1378 1378 + M: Antoniu Miclaus <antoniu.miclaus@analog.com> 1379 1379 + L: linux-iio@vger.kernel.org 1380 1380 + S: Supported 1381 1381 + W: https://ez.analog.com/linux-software-drivers 1382 1382 + F: Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml 1383 1383 + F: drivers/iio/adc/ad4080.c 1384 1384 + 1377 1385 ANALOG DEVICES INC AD4130 DRIVER 1378 1386 M: Cosmin Tanislav <cosmin.tanislav@analog.com> 1379 1387 L: linux-iio@vger.kernel.org ··· 1390 1382 F: Documentation/ABI/testing/sysfs-bus-iio-adc-ad4130 1391 1383 F: Documentation/devicetree/bindings/iio/adc/adi,ad4130.yaml 1392 1384 F: drivers/iio/adc/ad4130.c 1385 1385 + 1386 1386 + ANALOG DEVICES INC AD4170-4 DRIVER 1387 1387 + M: Marcelo Schmitt <marcelo.schmitt@analog.com> 1388 1388 + L: linux-iio@vger.kernel.org 1389 1389 + S: Supported 1390 1390 + W: https://ez.analog.com/linux-software-drivers 1391 1391 + F: Documentation/devicetree/bindings/iio/adc/adi,ad4170-4.yaml 1392 1392 + F: drivers/iio/adc/ad4170-4.c 1393 1393 1394 1394 ANALOG DEVICES INC AD4695 DRIVER 1395 1395 M: Michael Hennerich <michael.hennerich@analog.com> ··· 1497 1481 W: https://ez.analog.com/linux-software-drivers 1498 1482 F: Documentation/devicetree/bindings/iio/adc/adi,ad7768-1.yaml 1499 1483 F: drivers/iio/adc/ad7768-1.c 1484 1484 + F: include/dt-bindings/iio/adc/adi,ad7768-1.h 1500 1485 1501 1486 ANALOG DEVICES INC AD7780 DRIVER 1502 1487 M: Michael Hennerich <Michael.Hennerich@analog.com> ··· 23552 23535 M: Jonathan Cameron <jic23@kernel.org> 23553 23536 L: linux-iio@vger.kernel.org 23554 23537 S: Odd Fixes 23555 23555 - F: Documentation/devicetree/bindings/staging/iio/ 23556 23538 F: drivers/staging/iio/ 23557 23539 23558 23540 STAGING - NVIDIA COMPLIANT EMBEDDED CONTROLLER INTERFACE (nvec) ··· 25210 25194 T: git git://github.com/srcres258/linux-doc.git doc-zh-tw 25211 25195 F: Documentation/translations/zh_TW/ 25212 25196 25213 25213 - TRIGGER SOURCE - PWM 25197 25197 + TRIGGER SOURCE 25214 25198 M: David Lechner <dlechner@baylibre.com> 25215 25199 S: Maintained 25200 25200 + F: Documentation/devicetree/bindings/trigger-source/gpio-trigger.yaml 25216 25201 F: Documentation/devicetree/bindings/trigger-source/pwm-trigger.yaml 25217 25202 25218 25203 TRUSTED SECURITY MODULE (TSM) INFRASTRUCTURE

+31 -2

drivers/iio/accel/adxl313.h

reviewed

··· 18 18 #define ADXL313_REG_SOFT_RESET 0x18 19 19 #define ADXL313_REG_OFS_AXIS(index) (0x1E + (index)) 20 20 #define ADXL313_REG_THRESH_ACT 0x24 21 21 + #define ADXL313_REG_THRESH_INACT 0x25 22 22 + #define ADXL313_REG_TIME_INACT 0x26 21 23 #define ADXL313_REG_ACT_INACT_CTL 0x27 22 24 #define ADXL313_REG_BW_RATE 0x2C 23 25 #define ADXL313_REG_POWER_CTL 0x2D 26 26 + #define ADXL313_REG_INT_ENABLE 0x2E 24 27 #define ADXL313_REG_INT_MAP 0x2F 28 28 + #define ADXL313_REG_INT_SOURCE 0x30 25 29 #define ADXL313_REG_DATA_FORMAT 0x31 26 30 #define ADXL313_REG_DATA_AXIS(index) (0x32 + ((index) * 2)) 27 31 #define ADXL313_REG_FIFO_CTL 0x38 ··· 40 36 #define ADXL313_RATE_MSK GENMASK(3, 0) 41 37 #define ADXL313_RATE_BASE 6 42 38 43 43 - #define ADXL313_POWER_CTL_MSK GENMASK(3, 2) 44 44 - #define ADXL313_MEASUREMENT_MODE BIT(3) 39 39 + #define ADXL313_POWER_CTL_MSK BIT(3) 40 40 + #define ADXL313_POWER_CTL_INACT_MSK GENMASK(5, 4) 41 41 + #define ADXL313_POWER_CTL_LINK BIT(5) 42 42 + #define ADXL313_POWER_CTL_AUTO_SLEEP BIT(4) 45 43 46 44 #define ADXL313_RANGE_MSK GENMASK(1, 0) 47 45 #define ADXL313_RANGE_MAX 3 ··· 52 46 #define ADXL313_SPI_3WIRE BIT(6) 53 47 #define ADXL313_I2C_DISABLE BIT(6) 54 48 49 49 + #define ADXL313_INT_OVERRUN BIT(0) 50 50 + #define ADXL313_INT_WATERMARK BIT(1) 51 51 + #define ADXL313_INT_INACTIVITY BIT(3) 52 52 + #define ADXL313_INT_ACTIVITY BIT(4) 53 53 + #define ADXL313_INT_DREADY BIT(7) 54 54 + 55 55 + /* FIFO entries: how many values are stored in the FIFO */ 56 56 + #define ADXL313_REG_FIFO_STATUS_ENTRIES_MSK GENMASK(5, 0) 57 57 + /* FIFO samples: number of samples needed for watermark (FIFO mode) */ 58 58 + #define ADXL313_REG_FIFO_CTL_SAMPLES_MSK GENMASK(4, 0) 59 59 + #define ADXL313_REG_FIFO_CTL_MODE_MSK GENMASK(7, 6) 60 60 + 61 61 + #define ADXL313_FIFO_BYPASS 0 62 62 + #define ADXL313_FIFO_STREAM 2 63 63 + 64 64 + #define ADXL313_FIFO_SIZE 32 65 65 + 66 66 + #define ADXL313_NUM_AXIS 3 67 67 + 55 68 extern const struct regmap_access_table adxl312_readable_regs_table; 56 69 extern const struct regmap_access_table adxl313_readable_regs_table; 57 70 extern const struct regmap_access_table adxl314_readable_regs_table; ··· 78 53 extern const struct regmap_access_table adxl312_writable_regs_table; 79 54 extern const struct regmap_access_table adxl313_writable_regs_table; 80 55 extern const struct regmap_access_table adxl314_writable_regs_table; 56 56 + 57 57 + bool adxl313_is_volatile_reg(struct device *dev, unsigned int reg); 81 58 82 59 enum adxl313_device_type { 83 60 ADXL312, ··· 91 64 struct regmap *regmap; 92 65 const struct adxl313_chip_info *chip_info; 93 66 struct mutex lock; /* lock to protect transf_buf */ 67 67 + u8 watermark; 94 68 __le16 transf_buf __aligned(IIO_DMA_MINALIGN); 69 69 + __le16 fifo_buf[ADXL313_NUM_AXIS * ADXL313_FIFO_SIZE + 1]; 95 70 }; 96 71 97 72 struct adxl313_chip_info {

+914 -9

drivers/iio/accel/adxl313_core.c

reviewed

··· 8 8 */ 9 9 10 10 #include <linux/bitfield.h> 11 11 + #include <linux/interrupt.h> 11 12 #include <linux/module.h> 13 13 + #include <linux/overflow.h> 14 14 + #include <linux/property.h> 12 15 #include <linux/regmap.h> 16 16 + #include <linux/units.h> 17 17 + 18 18 + #include <linux/iio/buffer.h> 19 19 + #include <linux/iio/events.h> 20 20 + #include <linux/iio/kfifo_buf.h> 13 21 14 22 #include "adxl313.h" 23 23 + 24 24 + #define ADXL313_INT_NONE U8_MAX 25 25 + #define ADXL313_INT1 1 26 26 + #define ADXL313_INT2 2 27 27 + 28 28 + #define ADXL313_REG_XYZ_BASE ADXL313_REG_DATA_AXIS(0) 29 29 + 30 30 + #define ADXL313_ACT_XYZ_EN GENMASK(6, 4) 31 31 + #define ADXL313_INACT_XYZ_EN GENMASK(2, 0) 32 32 + 33 33 + #define ADXL313_REG_ACT_ACDC_MSK BIT(7) 34 34 + #define ADXL313_REG_INACT_ACDC_MSK BIT(3) 35 35 + #define ADXL313_COUPLING_DC 0 36 36 + #define ADXL313_COUPLING_AC 1 37 37 + 38 38 + /* activity/inactivity */ 39 39 + enum adxl313_activity_type { 40 40 + ADXL313_ACTIVITY, 41 41 + ADXL313_INACTIVITY, 42 42 + ADXL313_ACTIVITY_AC, 43 43 + ADXL313_INACTIVITY_AC, 44 44 + }; 45 45 + 46 46 + static const unsigned int adxl313_act_int_reg[] = { 47 47 + [ADXL313_ACTIVITY] = ADXL313_INT_ACTIVITY, 48 48 + [ADXL313_INACTIVITY] = ADXL313_INT_INACTIVITY, 49 49 + [ADXL313_ACTIVITY_AC] = ADXL313_INT_ACTIVITY, 50 50 + [ADXL313_INACTIVITY_AC] = ADXL313_INT_INACTIVITY, 51 51 + }; 52 52 + 53 53 + static const unsigned int adxl313_act_thresh_reg[] = { 54 54 + [ADXL313_ACTIVITY] = ADXL313_REG_THRESH_ACT, 55 55 + [ADXL313_INACTIVITY] = ADXL313_REG_THRESH_INACT, 56 56 + [ADXL313_ACTIVITY_AC] = ADXL313_REG_THRESH_ACT, 57 57 + [ADXL313_INACTIVITY_AC] = ADXL313_REG_THRESH_INACT, 58 58 + }; 59 59 + 60 60 + static const unsigned int adxl313_act_acdc_msk[] = { 61 61 + [ADXL313_ACTIVITY] = ADXL313_REG_ACT_ACDC_MSK, 62 62 + [ADXL313_INACTIVITY] = ADXL313_REG_INACT_ACDC_MSK, 63 63 + [ADXL313_ACTIVITY_AC] = ADXL313_REG_ACT_ACDC_MSK, 64 64 + [ADXL313_INACTIVITY_AC] = ADXL313_REG_INACT_ACDC_MSK, 65 65 + }; 15 66 16 67 static const struct regmap_range adxl312_readable_reg_range[] = { 17 68 regmap_reg_range(ADXL313_REG_DEVID0, ADXL313_REG_DEVID0), ··· 96 45 .n_yes_ranges = ARRAY_SIZE(adxl312_readable_reg_range), 97 46 }; 98 47 EXPORT_SYMBOL_NS_GPL(adxl314_readable_regs_table, "IIO_ADXL313"); 48 48 + 49 49 + bool adxl313_is_volatile_reg(struct device *dev, unsigned int reg) 50 50 + { 51 51 + switch (reg) { 52 52 + case ADXL313_REG_DATA_AXIS(0): 53 53 + case ADXL313_REG_DATA_AXIS(1): 54 54 + case ADXL313_REG_DATA_AXIS(2): 55 55 + case ADXL313_REG_DATA_AXIS(3): 56 56 + case ADXL313_REG_DATA_AXIS(4): 57 57 + case ADXL313_REG_DATA_AXIS(5): 58 58 + case ADXL313_REG_FIFO_STATUS: 59 59 + case ADXL313_REG_INT_SOURCE: 60 60 + return true; 61 61 + default: 62 62 + return false; 63 63 + } 64 64 + } 65 65 + EXPORT_SYMBOL_NS_GPL(adxl313_is_volatile_reg, "IIO_ADXL313"); 66 66 + 67 67 + static int adxl313_set_measure_en(struct adxl313_data *data, bool en) 68 68 + { 69 69 + return regmap_assign_bits(data->regmap, ADXL313_REG_POWER_CTL, 70 70 + ADXL313_POWER_CTL_MSK, en); 71 71 + } 99 72 100 73 static int adxl312_check_id(struct device *dev, 101 74 struct adxl313_data *data) ··· 246 171 [9] = { 3200, 0 }, 247 172 }; 248 173 249 249 - #define ADXL313_ACCEL_CHANNEL(index, axis) { \ 174 174 + #define ADXL313_ACCEL_CHANNEL(index, reg, axis) { \ 250 175 .type = IIO_ACCEL, \ 251 251 - .address = index, \ 176 176 + .scan_index = (index), \ 177 177 + .address = (reg), \ 252 178 .modified = 1, \ 253 179 .channel2 = IIO_MOD_##axis, \ 254 180 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ ··· 259 183 .info_mask_shared_by_type_available = \ 260 184 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 261 185 .scan_type = { \ 186 186 + .sign = 's', \ 262 187 .realbits = 13, \ 188 188 + .storagebits = 16, \ 189 189 + .endianness = IIO_BE, \ 263 190 }, \ 264 191 } 265 192 193 193 + static const struct iio_event_spec adxl313_activity_events[] = { 194 194 + { 195 195 + .type = IIO_EV_TYPE_MAG, 196 196 + .dir = IIO_EV_DIR_RISING, 197 197 + .mask_separate = BIT(IIO_EV_INFO_ENABLE), 198 198 + .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE), 199 199 + }, 200 200 + { 201 201 + /* activity, AC bit set */ 202 202 + .type = IIO_EV_TYPE_MAG_ADAPTIVE, 203 203 + .dir = IIO_EV_DIR_RISING, 204 204 + .mask_separate = BIT(IIO_EV_INFO_ENABLE), 205 205 + .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE), 206 206 + }, 207 207 + }; 208 208 + 209 209 + static const struct iio_event_spec adxl313_inactivity_events[] = { 210 210 + { 211 211 + /* inactivity */ 212 212 + .type = IIO_EV_TYPE_MAG, 213 213 + .dir = IIO_EV_DIR_FALLING, 214 214 + .mask_separate = BIT(IIO_EV_INFO_ENABLE), 215 215 + .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 216 216 + BIT(IIO_EV_INFO_PERIOD), 217 217 + }, 218 218 + { 219 219 + /* inactivity, AC bit set */ 220 220 + .type = IIO_EV_TYPE_MAG_ADAPTIVE, 221 221 + .dir = IIO_EV_DIR_FALLING, 222 222 + .mask_separate = BIT(IIO_EV_INFO_ENABLE), 223 223 + .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 224 224 + BIT(IIO_EV_INFO_PERIOD), 225 225 + }, 226 226 + }; 227 227 + 228 228 + enum adxl313_chans { 229 229 + chan_x, chan_y, chan_z, 230 230 + }; 231 231 + 266 232 static const struct iio_chan_spec adxl313_channels[] = { 267 267 - ADXL313_ACCEL_CHANNEL(0, X), 268 268 - ADXL313_ACCEL_CHANNEL(1, Y), 269 269 - ADXL313_ACCEL_CHANNEL(2, Z), 233 233 + ADXL313_ACCEL_CHANNEL(0, chan_x, X), 234 234 + ADXL313_ACCEL_CHANNEL(1, chan_y, Y), 235 235 + ADXL313_ACCEL_CHANNEL(2, chan_z, Z), 236 236 + { 237 237 + .type = IIO_ACCEL, 238 238 + .modified = 1, 239 239 + .channel2 = IIO_MOD_X_OR_Y_OR_Z, 240 240 + .scan_index = -1, /* Fake channel for axis OR'ing */ 241 241 + .event_spec = adxl313_activity_events, 242 242 + .num_event_specs = ARRAY_SIZE(adxl313_activity_events), 243 243 + }, 244 244 + { 245 245 + .type = IIO_ACCEL, 246 246 + .modified = 1, 247 247 + .channel2 = IIO_MOD_X_AND_Y_AND_Z, 248 248 + .scan_index = -1, /* Fake channel for axis AND'ing */ 249 249 + .event_spec = adxl313_inactivity_events, 250 250 + .num_event_specs = ARRAY_SIZE(adxl313_inactivity_events), 251 251 + }, 252 252 + }; 253 253 + 254 254 + static const unsigned long adxl313_scan_masks[] = { 255 255 + BIT(chan_x) | BIT(chan_y) | BIT(chan_z), 256 256 + 0 270 257 }; 271 258 272 259 static int adxl313_set_odr(struct adxl313_data *data, ··· 385 246 default: 386 247 return -EINVAL; 387 248 } 249 249 + } 250 250 + 251 251 + static int adxl313_set_inact_time_s(struct adxl313_data *data, 252 252 + unsigned int val_s) 253 253 + { 254 254 + unsigned int max_boundary = U8_MAX; /* by register size */ 255 255 + unsigned int val = min(val_s, max_boundary); 256 256 + 257 257 + return regmap_write(data->regmap, ADXL313_REG_TIME_INACT, val); 258 258 + } 259 259 + 260 260 + /** 261 261 + * adxl313_is_act_inact_ac() - Check if AC coupling is enabled. 262 262 + * @data: The device data. 263 263 + * @type: The activity or inactivity type. 264 264 + * 265 265 + * Provide a type of activity or inactivity, combined with either AC coupling 266 266 + * set, or default to DC coupling. This function verifies if the combination is 267 267 + * currently enabled or not. 268 268 + * 269 269 + * Return: if the provided activity type has AC coupling enabled or a negative 270 270 + * error value. 271 271 + */ 272 272 + static int adxl313_is_act_inact_ac(struct adxl313_data *data, 273 273 + enum adxl313_activity_type type) 274 274 + { 275 275 + unsigned int regval; 276 276 + bool coupling; 277 277 + int ret; 278 278 + 279 279 + ret = regmap_read(data->regmap, ADXL313_REG_ACT_INACT_CTL, &regval); 280 280 + if (ret) 281 281 + return ret; 282 282 + 283 283 + coupling = adxl313_act_acdc_msk[type] & regval; 284 284 + 285 285 + switch (type) { 286 286 + case ADXL313_ACTIVITY: 287 287 + case ADXL313_INACTIVITY: 288 288 + return coupling == ADXL313_COUPLING_DC; 289 289 + case ADXL313_ACTIVITY_AC: 290 290 + case ADXL313_INACTIVITY_AC: 291 291 + return coupling == ADXL313_COUPLING_AC; 292 292 + default: 293 293 + return -EINVAL; 294 294 + } 295 295 + } 296 296 + 297 297 + static int adxl313_set_act_inact_ac(struct adxl313_data *data, 298 298 + enum adxl313_activity_type type, 299 299 + bool cmd_en) 300 300 + { 301 301 + unsigned int act_inact_ac; 302 302 + 303 303 + switch (type) { 304 304 + case ADXL313_ACTIVITY_AC: 305 305 + case ADXL313_INACTIVITY_AC: 306 306 + act_inact_ac = ADXL313_COUPLING_AC && cmd_en; 307 307 + break; 308 308 + case ADXL313_ACTIVITY: 309 309 + case ADXL313_INACTIVITY: 310 310 + act_inact_ac = ADXL313_COUPLING_DC && cmd_en; 311 311 + break; 312 312 + default: 313 313 + return -EINVAL; 314 314 + } 315 315 + 316 316 + return regmap_assign_bits(data->regmap, ADXL313_REG_ACT_INACT_CTL, 317 317 + adxl313_act_acdc_msk[type], act_inact_ac); 318 318 + } 319 319 + 320 320 + static int adxl313_is_act_inact_en(struct adxl313_data *data, 321 321 + enum adxl313_activity_type type) 322 322 + { 323 323 + unsigned int axis_ctrl; 324 324 + unsigned int regval; 325 325 + bool int_en; 326 326 + int ret; 327 327 + 328 328 + ret = regmap_read(data->regmap, ADXL313_REG_ACT_INACT_CTL, &axis_ctrl); 329 329 + if (ret) 330 330 + return ret; 331 331 + 332 332 + /* Check if axis for activity are enabled */ 333 333 + switch (type) { 334 334 + case ADXL313_ACTIVITY: 335 335 + case ADXL313_ACTIVITY_AC: 336 336 + if (!FIELD_GET(ADXL313_ACT_XYZ_EN, axis_ctrl)) 337 337 + return false; 338 338 + break; 339 339 + case ADXL313_INACTIVITY: 340 340 + case ADXL313_INACTIVITY_AC: 341 341 + if (!FIELD_GET(ADXL313_INACT_XYZ_EN, axis_ctrl)) 342 342 + return false; 343 343 + break; 344 344 + default: 345 345 + return -EINVAL; 346 346 + } 347 347 + 348 348 + /* Check if specific interrupt is enabled */ 349 349 + ret = regmap_read(data->regmap, ADXL313_REG_INT_ENABLE, &regval); 350 350 + if (ret) 351 351 + return ret; 352 352 + 353 353 + int_en = adxl313_act_int_reg[type] & regval; 354 354 + if (!int_en) 355 355 + return false; 356 356 + 357 357 + /* Check if configured coupling matches provided type */ 358 358 + return adxl313_is_act_inact_ac(data, type); 359 359 + } 360 360 + 361 361 + static int adxl313_set_act_inact_linkbit(struct adxl313_data *data, bool en) 362 362 + { 363 363 + int act_ac_en, inact_ac_en; 364 364 + int act_en, inact_en; 365 365 + 366 366 + act_en = adxl313_is_act_inact_en(data, ADXL313_ACTIVITY); 367 367 + if (act_en < 0) 368 368 + return act_en; 369 369 + 370 370 + act_ac_en = adxl313_is_act_inact_en(data, ADXL313_ACTIVITY_AC); 371 371 + if (act_ac_en < 0) 372 372 + return act_ac_en; 373 373 + 374 374 + inact_en = adxl313_is_act_inact_en(data, ADXL313_INACTIVITY); 375 375 + if (inact_en < 0) 376 376 + return inact_en; 377 377 + 378 378 + inact_ac_en = adxl313_is_act_inact_en(data, ADXL313_INACTIVITY_AC); 379 379 + if (inact_ac_en < 0) 380 380 + return inact_ac_en; 381 381 + 382 382 + act_en = act_en || act_ac_en; 383 383 + 384 384 + inact_en = inact_en || inact_ac_en; 385 385 + 386 386 + return regmap_assign_bits(data->regmap, ADXL313_REG_POWER_CTL, 387 387 + ADXL313_POWER_CTL_AUTO_SLEEP | ADXL313_POWER_CTL_LINK, 388 388 + en && act_en && inact_en); 389 389 + } 390 390 + 391 391 + static int adxl313_set_act_inact_en(struct adxl313_data *data, 392 392 + enum adxl313_activity_type type, 393 393 + bool cmd_en) 394 394 + { 395 395 + unsigned int axis_ctrl; 396 396 + unsigned int threshold; 397 397 + unsigned int inact_time_s; 398 398 + int ret; 399 399 + 400 400 + if (cmd_en) { 401 401 + /* When turning on, check if threshold is valid */ 402 402 + ret = regmap_read(data->regmap, adxl313_act_thresh_reg[type], 403 403 + &threshold); 404 404 + if (ret) 405 405 + return ret; 406 406 + 407 407 + if (!threshold) /* Just ignore the command if threshold is 0 */ 408 408 + return 0; 409 409 + 410 410 + /* When turning on inactivity, check if inact time is valid */ 411 411 + if (type == ADXL313_INACTIVITY || type == ADXL313_INACTIVITY_AC) { 412 412 + ret = regmap_read(data->regmap, 413 413 + ADXL313_REG_TIME_INACT, 414 414 + &inact_time_s); 415 415 + if (ret) 416 416 + return ret; 417 417 + 418 418 + if (!inact_time_s) 419 419 + return 0; 420 420 + } 421 421 + } else { 422 422 + /* 423 423 + * When turning off an activity, ensure that the correct 424 424 + * coupling event is specified. This step helps prevent misuse - 425 425 + * for example, if an AC-coupled activity is active and the 426 426 + * current call attempts to turn off a DC-coupled activity, this 427 427 + * inconsistency should be detected here. 428 428 + */ 429 429 + if (adxl313_is_act_inact_ac(data, type) <= 0) 430 430 + return 0; 431 431 + } 432 432 + 433 433 + /* Start modifying configuration registers */ 434 434 + ret = adxl313_set_measure_en(data, false); 435 435 + if (ret) 436 436 + return ret; 437 437 + 438 438 + /* Enable axis according to the command */ 439 439 + switch (type) { 440 440 + case ADXL313_ACTIVITY: 441 441 + case ADXL313_ACTIVITY_AC: 442 442 + axis_ctrl = ADXL313_ACT_XYZ_EN; 443 443 + break; 444 444 + case ADXL313_INACTIVITY: 445 445 + case ADXL313_INACTIVITY_AC: 446 446 + axis_ctrl = ADXL313_INACT_XYZ_EN; 447 447 + break; 448 448 + default: 449 449 + return -EINVAL; 450 450 + } 451 451 + ret = regmap_assign_bits(data->regmap, ADXL313_REG_ACT_INACT_CTL, 452 452 + axis_ctrl, cmd_en); 453 453 + if (ret) 454 454 + return ret; 455 455 + 456 456 + /* Update AC/DC-coupling according to the command */ 457 457 + ret = adxl313_set_act_inact_ac(data, type, cmd_en); 458 458 + if (ret) 459 459 + return ret; 460 460 + 461 461 + /* Enable the interrupt line, according to the command */ 462 462 + ret = regmap_assign_bits(data->regmap, ADXL313_REG_INT_ENABLE, 463 463 + adxl313_act_int_reg[type], cmd_en); 464 464 + if (ret) 465 465 + return ret; 466 466 + 467 467 + /* Set link-bit and auto-sleep only when ACT and INACT are enabled */ 468 468 + ret = adxl313_set_act_inact_linkbit(data, cmd_en); 469 469 + if (ret) 470 470 + return ret; 471 471 + 472 472 + return adxl313_set_measure_en(data, true); 388 473 } 389 474 390 475 static int adxl313_read_raw(struct iio_dev *indio_dev, ··· 684 321 } 685 322 } 686 323 324 324 + static int adxl313_read_mag_config(struct adxl313_data *data, 325 325 + enum iio_event_direction dir, 326 326 + enum adxl313_activity_type type_act, 327 327 + enum adxl313_activity_type type_inact) 328 328 + { 329 329 + switch (dir) { 330 330 + case IIO_EV_DIR_RISING: 331 331 + return !!adxl313_is_act_inact_en(data, type_act); 332 332 + case IIO_EV_DIR_FALLING: 333 333 + return !!adxl313_is_act_inact_en(data, type_inact); 334 334 + default: 335 335 + return -EINVAL; 336 336 + } 337 337 + } 338 338 + 339 339 + static int adxl313_write_mag_config(struct adxl313_data *data, 340 340 + enum iio_event_direction dir, 341 341 + enum adxl313_activity_type type_act, 342 342 + enum adxl313_activity_type type_inact, 343 343 + bool state) 344 344 + { 345 345 + switch (dir) { 346 346 + case IIO_EV_DIR_RISING: 347 347 + return adxl313_set_act_inact_en(data, type_act, state); 348 348 + case IIO_EV_DIR_FALLING: 349 349 + return adxl313_set_act_inact_en(data, type_inact, state); 350 350 + default: 351 351 + return -EINVAL; 352 352 + } 353 353 + } 354 354 + 355 355 + static int adxl313_read_event_config(struct iio_dev *indio_dev, 356 356 + const struct iio_chan_spec *chan, 357 357 + enum iio_event_type type, 358 358 + enum iio_event_direction dir) 359 359 + { 360 360 + struct adxl313_data *data = iio_priv(indio_dev); 361 361 + 362 362 + switch (type) { 363 363 + case IIO_EV_TYPE_MAG: 364 364 + return adxl313_read_mag_config(data, dir, 365 365 + ADXL313_ACTIVITY, 366 366 + ADXL313_INACTIVITY); 367 367 + case IIO_EV_TYPE_MAG_ADAPTIVE: 368 368 + return adxl313_read_mag_config(data, dir, 369 369 + ADXL313_ACTIVITY_AC, 370 370 + ADXL313_INACTIVITY_AC); 371 371 + default: 372 372 + return -EINVAL; 373 373 + } 374 374 + } 375 375 + 376 376 + static int adxl313_write_event_config(struct iio_dev *indio_dev, 377 377 + const struct iio_chan_spec *chan, 378 378 + enum iio_event_type type, 379 379 + enum iio_event_direction dir, 380 380 + bool state) 381 381 + { 382 382 + struct adxl313_data *data = iio_priv(indio_dev); 383 383 + 384 384 + switch (type) { 385 385 + case IIO_EV_TYPE_MAG: 386 386 + return adxl313_write_mag_config(data, dir, 387 387 + ADXL313_ACTIVITY, 388 388 + ADXL313_INACTIVITY, 389 389 + state); 390 390 + case IIO_EV_TYPE_MAG_ADAPTIVE: 391 391 + return adxl313_write_mag_config(data, dir, 392 392 + ADXL313_ACTIVITY_AC, 393 393 + ADXL313_INACTIVITY_AC, 394 394 + state); 395 395 + default: 396 396 + return -EINVAL; 397 397 + } 398 398 + } 399 399 + 400 400 + static int adxl313_read_mag_value(struct adxl313_data *data, 401 401 + enum iio_event_direction dir, 402 402 + enum iio_event_info info, 403 403 + enum adxl313_activity_type type_act, 404 404 + enum adxl313_activity_type type_inact, 405 405 + int *val, int *val2) 406 406 + { 407 407 + unsigned int threshold; 408 408 + unsigned int period; 409 409 + int ret; 410 410 + 411 411 + switch (info) { 412 412 + case IIO_EV_INFO_VALUE: 413 413 + switch (dir) { 414 414 + case IIO_EV_DIR_RISING: 415 415 + ret = regmap_read(data->regmap, 416 416 + adxl313_act_thresh_reg[type_act], 417 417 + &threshold); 418 418 + if (ret) 419 419 + return ret; 420 420 + *val = threshold * 15625; 421 421 + *val2 = MICRO; 422 422 + return IIO_VAL_FRACTIONAL; 423 423 + case IIO_EV_DIR_FALLING: 424 424 + ret = regmap_read(data->regmap, 425 425 + adxl313_act_thresh_reg[type_inact], 426 426 + &threshold); 427 427 + if (ret) 428 428 + return ret; 429 429 + *val = threshold * 15625; 430 430 + *val2 = MICRO; 431 431 + return IIO_VAL_FRACTIONAL; 432 432 + default: 433 433 + return -EINVAL; 434 434 + } 435 435 + case IIO_EV_INFO_PERIOD: 436 436 + ret = regmap_read(data->regmap, ADXL313_REG_TIME_INACT, 437 437 + &period); 438 438 + if (ret) 439 439 + return ret; 440 440 + *val = period; 441 441 + return IIO_VAL_INT; 442 442 + default: 443 443 + return -EINVAL; 444 444 + } 445 445 + } 446 446 + 447 447 + static int adxl313_write_mag_value(struct adxl313_data *data, 448 448 + enum iio_event_direction dir, 449 449 + enum iio_event_info info, 450 450 + enum adxl313_activity_type type_act, 451 451 + enum adxl313_activity_type type_inact, 452 452 + int val, int val2) 453 453 + { 454 454 + unsigned int regval; 455 455 + 456 456 + switch (info) { 457 457 + case IIO_EV_INFO_VALUE: 458 458 + /* Scale factor 15.625 mg/LSB */ 459 459 + regval = DIV_ROUND_CLOSEST(MICRO * val + val2, 15625); 460 460 + switch (dir) { 461 461 + case IIO_EV_DIR_RISING: 462 462 + return regmap_write(data->regmap, 463 463 + adxl313_act_thresh_reg[type_act], 464 464 + regval); 465 465 + case IIO_EV_DIR_FALLING: 466 466 + return regmap_write(data->regmap, 467 467 + adxl313_act_thresh_reg[type_inact], 468 468 + regval); 469 469 + default: 470 470 + return -EINVAL; 471 471 + } 472 472 + case IIO_EV_INFO_PERIOD: 473 473 + return adxl313_set_inact_time_s(data, val); 474 474 + default: 475 475 + return -EINVAL; 476 476 + } 477 477 + } 478 478 + 479 479 + static int adxl313_read_event_value(struct iio_dev *indio_dev, 480 480 + const struct iio_chan_spec *chan, 481 481 + enum iio_event_type type, 482 482 + enum iio_event_direction dir, 483 483 + enum iio_event_info info, 484 484 + int *val, int *val2) 485 485 + { 486 486 + struct adxl313_data *data = iio_priv(indio_dev); 487 487 + 488 488 + switch (type) { 489 489 + case IIO_EV_TYPE_MAG: 490 490 + return adxl313_read_mag_value(data, dir, info, 491 491 + ADXL313_ACTIVITY, 492 492 + ADXL313_INACTIVITY, 493 493 + val, val2); 494 494 + case IIO_EV_TYPE_MAG_ADAPTIVE: 495 495 + return adxl313_read_mag_value(data, dir, info, 496 496 + ADXL313_ACTIVITY_AC, 497 497 + ADXL313_INACTIVITY_AC, 498 498 + val, val2); 499 499 + default: 500 500 + return -EINVAL; 501 501 + } 502 502 + } 503 503 + 504 504 + static int adxl313_write_event_value(struct iio_dev *indio_dev, 505 505 + const struct iio_chan_spec *chan, 506 506 + enum iio_event_type type, 507 507 + enum iio_event_direction dir, 508 508 + enum iio_event_info info, 509 509 + int val, int val2) 510 510 + { 511 511 + struct adxl313_data *data = iio_priv(indio_dev); 512 512 + 513 513 + switch (type) { 514 514 + case IIO_EV_TYPE_MAG: 515 515 + return adxl313_write_mag_value(data, dir, info, 516 516 + ADXL313_ACTIVITY, 517 517 + ADXL313_INACTIVITY, 518 518 + val, val2); 519 519 + case IIO_EV_TYPE_MAG_ADAPTIVE: 520 520 + return adxl313_write_mag_value(data, dir, info, 521 521 + ADXL313_ACTIVITY_AC, 522 522 + ADXL313_INACTIVITY_AC, 523 523 + val, val2); 524 524 + default: 525 525 + return -EINVAL; 526 526 + } 527 527 + } 528 528 + 529 529 + static int adxl313_set_watermark(struct iio_dev *indio_dev, unsigned int value) 530 530 + { 531 531 + struct adxl313_data *data = iio_priv(indio_dev); 532 532 + int ret; 533 533 + 534 534 + value = min(value, ADXL313_FIFO_SIZE - 1); 535 535 + 536 536 + ret = adxl313_set_measure_en(data, false); 537 537 + if (ret) 538 538 + return ret; 539 539 + 540 540 + ret = regmap_update_bits(data->regmap, ADXL313_REG_FIFO_CTL, 541 541 + ADXL313_REG_FIFO_CTL_MODE_MSK, value); 542 542 + if (ret) 543 543 + return ret; 544 544 + 545 545 + data->watermark = value; 546 546 + 547 547 + ret = regmap_set_bits(data->regmap, ADXL313_REG_INT_ENABLE, 548 548 + ADXL313_INT_WATERMARK); 549 549 + if (ret) 550 550 + return ret; 551 551 + 552 552 + return adxl313_set_measure_en(data, true); 553 553 + } 554 554 + 555 555 + static int adxl313_get_samples(struct adxl313_data *data) 556 556 + { 557 557 + unsigned int regval; 558 558 + int ret; 559 559 + 560 560 + ret = regmap_read(data->regmap, ADXL313_REG_FIFO_STATUS, &regval); 561 561 + if (ret) 562 562 + return ret; 563 563 + 564 564 + return FIELD_GET(ADXL313_REG_FIFO_STATUS_ENTRIES_MSK, regval); 565 565 + } 566 566 + 567 567 + static int adxl313_fifo_transfer(struct adxl313_data *data, int samples) 568 568 + { 569 569 + unsigned int i; 570 570 + int ret; 571 571 + 572 572 + for (i = 0; i < samples; i++) { 573 573 + ret = regmap_bulk_read(data->regmap, ADXL313_REG_XYZ_BASE, 574 574 + data->fifo_buf + (i * ADXL313_NUM_AXIS), 575 575 + sizeof(data->fifo_buf[0]) * ADXL313_NUM_AXIS); 576 576 + if (ret) 577 577 + return ret; 578 578 + } 579 579 + 580 580 + return 0; 581 581 + } 582 582 + 583 583 + /** 584 584 + * adxl313_fifo_reset() - Reset the FIFO and interrupt status registers. 585 585 + * @data: The device data. 586 586 + * 587 587 + * Reset the FIFO status registers. Reading out status registers clears the 588 588 + * FIFO and interrupt configuration. Thus do not evaluate regmap return values. 589 589 + * Ignore particular read register content. Register content is not processed 590 590 + * any further. Therefore the function returns void. 591 591 + */ 592 592 + static void adxl313_fifo_reset(struct adxl313_data *data) 593 593 + { 594 594 + unsigned int regval; 595 595 + int samples; 596 596 + 597 597 + adxl313_set_measure_en(data, false); 598 598 + 599 599 + samples = adxl313_get_samples(data); 600 600 + if (samples > 0) 601 601 + adxl313_fifo_transfer(data, samples); 602 602 + 603 603 + regmap_read(data->regmap, ADXL313_REG_INT_SOURCE, &regval); 604 604 + 605 605 + adxl313_set_measure_en(data, true); 606 606 + } 607 607 + 608 608 + static int adxl313_buffer_postenable(struct iio_dev *indio_dev) 609 609 + { 610 610 + struct adxl313_data *data = iio_priv(indio_dev); 611 611 + int ret; 612 612 + 613 613 + /* Set FIFO modes with measurement turned off, according to datasheet */ 614 614 + ret = adxl313_set_measure_en(data, false); 615 615 + if (ret) 616 616 + return ret; 617 617 + 618 618 + ret = regmap_write(data->regmap, ADXL313_REG_FIFO_CTL, 619 619 + FIELD_PREP(ADXL313_REG_FIFO_CTL_SAMPLES_MSK, data->watermark) | 620 620 + FIELD_PREP(ADXL313_REG_FIFO_CTL_MODE_MSK, ADXL313_FIFO_STREAM)); 621 621 + if (ret) 622 622 + return ret; 623 623 + 624 624 + return adxl313_set_measure_en(data, true); 625 625 + } 626 626 + 627 627 + static int adxl313_buffer_predisable(struct iio_dev *indio_dev) 628 628 + { 629 629 + struct adxl313_data *data = iio_priv(indio_dev); 630 630 + int ret; 631 631 + 632 632 + ret = adxl313_set_measure_en(data, false); 633 633 + if (ret) 634 634 + return ret; 635 635 + 636 636 + ret = regmap_write(data->regmap, ADXL313_REG_FIFO_CTL, 637 637 + FIELD_PREP(ADXL313_REG_FIFO_CTL_MODE_MSK, ADXL313_FIFO_BYPASS)); 638 638 + 639 639 + ret = regmap_write(data->regmap, ADXL313_REG_INT_ENABLE, 0); 640 640 + if (ret) 641 641 + return ret; 642 642 + 643 643 + return adxl313_set_measure_en(data, true); 644 644 + } 645 645 + 646 646 + static const struct iio_buffer_setup_ops adxl313_buffer_ops = { 647 647 + .postenable = adxl313_buffer_postenable, 648 648 + .predisable = adxl313_buffer_predisable, 649 649 + }; 650 650 + 651 651 + static int adxl313_fifo_push(struct iio_dev *indio_dev, int samples) 652 652 + { 653 653 + struct adxl313_data *data = iio_priv(indio_dev); 654 654 + unsigned int i; 655 655 + int ret; 656 656 + 657 657 + ret = adxl313_fifo_transfer(data, samples); 658 658 + if (ret) 659 659 + return ret; 660 660 + 661 661 + for (i = 0; i < ADXL313_NUM_AXIS * samples; i += ADXL313_NUM_AXIS) 662 662 + iio_push_to_buffers(indio_dev, &data->fifo_buf[i]); 663 663 + 664 664 + return 0; 665 665 + } 666 666 + 667 667 + static int adxl313_push_events(struct iio_dev *indio_dev, int int_stat) 668 668 + { 669 669 + s64 ts = iio_get_time_ns(indio_dev); 670 670 + struct adxl313_data *data = iio_priv(indio_dev); 671 671 + unsigned int regval; 672 672 + int ret = -ENOENT; 673 673 + 674 674 + if (FIELD_GET(ADXL313_INT_ACTIVITY, int_stat)) { 675 675 + ret = regmap_read(data->regmap, ADXL313_REG_ACT_INACT_CTL, &regval); 676 676 + if (ret) 677 677 + return ret; 678 678 + 679 679 + if (FIELD_GET(ADXL313_REG_ACT_ACDC_MSK, regval)) { 680 680 + /* AC coupled */ 681 681 + ret = iio_push_event(indio_dev, 682 682 + IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, 683 683 + IIO_MOD_X_OR_Y_OR_Z, 684 684 + IIO_EV_TYPE_MAG_ADAPTIVE, 685 685 + IIO_EV_DIR_RISING), 686 686 + ts); 687 687 + if (ret) 688 688 + return ret; 689 689 + } else { 690 690 + /* DC coupled, relying on THRESH */ 691 691 + ret = iio_push_event(indio_dev, 692 692 + IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, 693 693 + IIO_MOD_X_OR_Y_OR_Z, 694 694 + IIO_EV_TYPE_MAG, 695 695 + IIO_EV_DIR_RISING), 696 696 + ts); 697 697 + if (ret) 698 698 + return ret; 699 699 + } 700 700 + } 701 701 + 702 702 + if (FIELD_GET(ADXL313_INT_INACTIVITY, int_stat)) { 703 703 + ret = regmap_read(data->regmap, ADXL313_REG_ACT_INACT_CTL, &regval); 704 704 + if (ret) 705 705 + return ret; 706 706 + 707 707 + if (FIELD_GET(ADXL313_REG_INACT_ACDC_MSK, regval)) { 708 708 + /* AC coupled */ 709 709 + ret = iio_push_event(indio_dev, 710 710 + IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, 711 711 + IIO_MOD_X_AND_Y_AND_Z, 712 712 + IIO_EV_TYPE_MAG_ADAPTIVE, 713 713 + IIO_EV_DIR_FALLING), 714 714 + ts); 715 715 + if (ret) 716 716 + return ret; 717 717 + } else { 718 718 + /* DC coupled, relying on THRESH */ 719 719 + ret = iio_push_event(indio_dev, 720 720 + IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, 721 721 + IIO_MOD_X_AND_Y_AND_Z, 722 722 + IIO_EV_TYPE_MAG, 723 723 + IIO_EV_DIR_FALLING), 724 724 + ts); 725 725 + if (ret) 726 726 + return ret; 727 727 + } 728 728 + } 729 729 + 730 730 + return ret; 731 731 + } 732 732 + 733 733 + static irqreturn_t adxl313_irq_handler(int irq, void *p) 734 734 + { 735 735 + struct iio_dev *indio_dev = p; 736 736 + struct adxl313_data *data = iio_priv(indio_dev); 737 737 + int samples, int_stat; 738 738 + 739 739 + if (regmap_read(data->regmap, ADXL313_REG_INT_SOURCE, &int_stat)) 740 740 + return IRQ_NONE; 741 741 + 742 742 + /* 743 743 + * In cases of sensor events not handled (still not implemented) by 744 744 + * this driver, the FIFO needs to be drained to become operational 745 745 + * again. In general the sensor configuration only should issue events 746 746 + * which were configured by this driver. Anyway a miss-configuration 747 747 + * easily might end up in a hanging sensor FIFO. 748 748 + */ 749 749 + if (adxl313_push_events(indio_dev, int_stat)) 750 750 + goto err_reset_fifo; 751 751 + 752 752 + if (FIELD_GET(ADXL313_INT_WATERMARK, int_stat)) { 753 753 + samples = adxl313_get_samples(data); 754 754 + if (samples < 0) 755 755 + goto err_reset_fifo; 756 756 + 757 757 + if (adxl313_fifo_push(indio_dev, samples)) 758 758 + goto err_reset_fifo; 759 759 + } 760 760 + 761 761 + if (FIELD_GET(ADXL313_INT_OVERRUN, int_stat)) 762 762 + goto err_reset_fifo; 763 763 + 764 764 + return IRQ_HANDLED; 765 765 + 766 766 + err_reset_fifo: 767 767 + adxl313_fifo_reset(data); 768 768 + 769 769 + return IRQ_HANDLED; 770 770 + } 771 771 + 772 772 + static int adxl313_reg_access(struct iio_dev *indio_dev, unsigned int reg, 773 773 + unsigned int writeval, unsigned int *readval) 774 774 + { 775 775 + struct adxl313_data *data = iio_priv(indio_dev); 776 776 + 777 777 + if (readval) 778 778 + return regmap_read(data->regmap, reg, readval); 779 779 + return regmap_write(data->regmap, reg, writeval); 780 780 + } 781 781 + 687 782 static const struct iio_info adxl313_info = { 688 783 .read_raw = adxl313_read_raw, 689 784 .write_raw = adxl313_write_raw, 785 785 + .read_event_config = adxl313_read_event_config, 786 786 + .write_event_config = adxl313_write_event_config, 787 787 + .read_event_value = adxl313_read_event_value, 788 788 + .write_event_value = adxl313_write_event_value, 690 789 .read_avail = adxl313_read_freq_avail, 790 790 + .hwfifo_set_watermark = adxl313_set_watermark, 791 791 + .debugfs_reg_access = &adxl313_reg_access, 691 792 }; 692 793 693 794 static int adxl313_setup(struct device *dev, struct adxl313_data *data, ··· 1196 369 } 1197 370 1198 371 /* Enables measurement mode */ 1199 1199 - return regmap_update_bits(data->regmap, ADXL313_REG_POWER_CTL, 1200 1200 - ADXL313_POWER_CTL_MSK, 1201 1201 - ADXL313_MEASUREMENT_MODE); 372 372 + return adxl313_set_measure_en(data, true); 373 373 + } 374 374 + 375 375 + static unsigned int adxl313_get_int_type(struct device *dev, int *irq) 376 376 + { 377 377 + *irq = fwnode_irq_get_byname(dev_fwnode(dev), "INT1"); 378 378 + if (*irq > 0) 379 379 + return ADXL313_INT1; 380 380 + 381 381 + *irq = fwnode_irq_get_byname(dev_fwnode(dev), "INT2"); 382 382 + if (*irq > 0) 383 383 + return ADXL313_INT2; 384 384 + 385 385 + return ADXL313_INT_NONE; 1202 386 } 1203 387 1204 388 /** ··· 1229 391 { 1230 392 struct adxl313_data *data; 1231 393 struct iio_dev *indio_dev; 1232 1232 - int ret; 394 394 + u8 int_line; 395 395 + u8 int_map_msk; 396 396 + int irq, ret; 1233 397 1234 398 indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); 1235 399 if (!indio_dev) ··· 1248 408 indio_dev->modes = INDIO_DIRECT_MODE; 1249 409 indio_dev->channels = adxl313_channels; 1250 410 indio_dev->num_channels = ARRAY_SIZE(adxl313_channels); 411 411 + indio_dev->available_scan_masks = adxl313_scan_masks; 1251 412 1252 413 ret = adxl313_setup(dev, data, setup); 1253 414 if (ret) { 1254 415 dev_err(dev, "ADXL313 setup failed\n"); 1255 416 return ret; 417 417 + } 418 418 + 419 419 + int_line = adxl313_get_int_type(dev, &irq); 420 420 + if (int_line == ADXL313_INT_NONE) { 421 421 + /* 422 422 + * FIFO_BYPASSED mode 423 423 + * 424 424 + * When no interrupt lines are specified, the driver falls back 425 425 + * to use the sensor in FIFO_BYPASS mode. This means turning off 426 426 + * internal FIFO and interrupt generation (since there is no 427 427 + * line specified). Unmaskable interrupts such as overrun or 428 428 + * data ready won't interfere. Even that a FIFO_STREAM mode w/o 429 429 + * connected interrupt line might allow for obtaining raw 430 430 + * measurements, a fallback to disable interrupts when no 431 431 + * interrupt lines are connected seems to be the cleaner 432 432 + * solution. 433 433 + */ 434 434 + ret = regmap_write(data->regmap, ADXL313_REG_FIFO_CTL, 435 435 + FIELD_PREP(ADXL313_REG_FIFO_CTL_MODE_MSK, 436 436 + ADXL313_FIFO_BYPASS)); 437 437 + if (ret) 438 438 + return ret; 439 439 + } else { 440 440 + /* FIFO_STREAM mode */ 441 441 + int_map_msk = ADXL313_INT_DREADY | ADXL313_INT_ACTIVITY | 442 442 + ADXL313_INT_INACTIVITY | ADXL313_INT_WATERMARK | 443 443 + ADXL313_INT_OVERRUN; 444 444 + ret = regmap_assign_bits(data->regmap, ADXL313_REG_INT_MAP, 445 445 + int_map_msk, int_line == ADXL313_INT2); 446 446 + if (ret) 447 447 + return ret; 448 448 + 449 449 + /* 450 450 + * Reset or configure the registers with reasonable default 451 451 + * values. As having 0 in most cases may result in undesirable 452 452 + * behavior if the interrupts are enabled. 453 453 + */ 454 454 + ret = regmap_write(data->regmap, ADXL313_REG_ACT_INACT_CTL, 0x00); 455 455 + if (ret) 456 456 + return ret; 457 457 + 458 458 + ret = regmap_write(data->regmap, ADXL313_REG_TIME_INACT, 5); 459 459 + if (ret) 460 460 + return ret; 461 461 + 462 462 + ret = regmap_write(data->regmap, ADXL313_REG_THRESH_INACT, 0x4f); 463 463 + if (ret) 464 464 + return ret; 465 465 + 466 466 + ret = regmap_write(data->regmap, ADXL313_REG_THRESH_ACT, 0x52); 467 467 + if (ret) 468 468 + return ret; 469 469 + 470 470 + ret = devm_iio_kfifo_buffer_setup(dev, indio_dev, 471 471 + &adxl313_buffer_ops); 472 472 + if (ret) 473 473 + return ret; 474 474 + 475 475 + ret = devm_request_threaded_irq(dev, irq, NULL, 476 476 + &adxl313_irq_handler, 477 477 + IRQF_SHARED | IRQF_ONESHOT, 478 478 + indio_dev->name, indio_dev); 479 479 + if (ret) 480 480 + return ret; 1256 481 } 1257 482 1258 483 return devm_iio_device_register(dev, indio_dev);

+6

drivers/iio/accel/adxl313_i2c.c

reviewed

··· 21 21 .rd_table = &adxl312_readable_regs_table, 22 22 .wr_table = &adxl312_writable_regs_table, 23 23 .max_register = 0x39, 24 24 + .volatile_reg = adxl313_is_volatile_reg, 25 25 + .cache_type = REGCACHE_MAPLE, 24 26 }, 25 27 [ADXL313] = { 26 28 .reg_bits = 8, ··· 30 28 .rd_table = &adxl313_readable_regs_table, 31 29 .wr_table = &adxl313_writable_regs_table, 32 30 .max_register = 0x39, 31 31 + .volatile_reg = adxl313_is_volatile_reg, 32 32 + .cache_type = REGCACHE_MAPLE, 33 33 }, 34 34 [ADXL314] = { 35 35 .reg_bits = 8, ··· 39 35 .rd_table = &adxl314_readable_regs_table, 40 36 .wr_table = &adxl314_writable_regs_table, 41 37 .max_register = 0x39, 38 38 + .volatile_reg = adxl313_is_volatile_reg, 39 39 + .cache_type = REGCACHE_MAPLE, 42 40 }, 43 41 }; 44 42

+6

drivers/iio/accel/adxl313_spi.c

reviewed

··· 24 24 .max_register = 0x39, 25 25 /* Setting bits 7 and 6 enables multiple-byte read */ 26 26 .read_flag_mask = BIT(7) | BIT(6), 27 27 + .volatile_reg = adxl313_is_volatile_reg, 28 28 + .cache_type = REGCACHE_MAPLE, 27 29 }, 28 30 [ADXL313] = { 29 31 .reg_bits = 8, ··· 35 33 .max_register = 0x39, 36 34 /* Setting bits 7 and 6 enables multiple-byte read */ 37 35 .read_flag_mask = BIT(7) | BIT(6), 36 36 + .volatile_reg = adxl313_is_volatile_reg, 37 37 + .cache_type = REGCACHE_MAPLE, 38 38 }, 39 39 [ADXL314] = { 40 40 .reg_bits = 8, ··· 46 42 .max_register = 0x39, 47 43 /* Setting bits 7 and 6 enables multiple-byte read */ 48 44 .read_flag_mask = BIT(7) | BIT(6), 45 45 + .volatile_reg = adxl313_is_volatile_reg, 46 46 + .cache_type = REGCACHE_MAPLE, 49 47 }, 50 48 }; 51 49

+1 -2

drivers/iio/accel/adxl345.h

reviewed

··· 69 69 * BW_RATE bits - Bandwidth and output data rate. The default value is 70 70 * 0x0A, which translates to a 100 Hz output data rate 71 71 */ 72 72 - #define ADXL345_BW_RATE GENMASK(3, 0) 72 72 + #define ADXL345_BW_RATE_MSK GENMASK(3, 0) 73 73 #define ADXL345_BW_LOW_POWER BIT(4) 74 74 #define ADXL345_BASE_RATE_NANO_HZ 97656250LL 75 75 76 76 - #define ADXL345_POWER_CTL_STANDBY 0x00 77 76 #define ADXL345_POWER_CTL_WAKEUP GENMASK(1, 0) 78 77 #define ADXL345_POWER_CTL_SLEEP BIT(2) 79 78 #define ADXL345_POWER_CTL_MEASURE BIT(3)

+225 -63

drivers/iio/accel/adxl345_core.c

reviewed

··· 64 64 [ADXL345_TAP_TIME_DUR] = ADXL345_REG_DUR, 65 65 }; 66 66 67 67 + enum adxl345_odr { 68 68 + ADXL345_ODR_0P10HZ = 0, 69 69 + ADXL345_ODR_0P20HZ, 70 70 + ADXL345_ODR_0P39HZ, 71 71 + ADXL345_ODR_0P78HZ, 72 72 + ADXL345_ODR_1P56HZ, 73 73 + ADXL345_ODR_3P13HZ, 74 74 + ADXL345_ODR_6P25HZ, 75 75 + ADXL345_ODR_12P50HZ, 76 76 + ADXL345_ODR_25HZ, 77 77 + ADXL345_ODR_50HZ, 78 78 + ADXL345_ODR_100HZ, 79 79 + ADXL345_ODR_200HZ, 80 80 + ADXL345_ODR_400HZ, 81 81 + ADXL345_ODR_800HZ, 82 82 + ADXL345_ODR_1600HZ, 83 83 + ADXL345_ODR_3200HZ, 84 84 + }; 85 85 + 86 86 + enum adxl345_range { 87 87 + ADXL345_2G_RANGE = 0, 88 88 + ADXL345_4G_RANGE, 89 89 + ADXL345_8G_RANGE, 90 90 + ADXL345_16G_RANGE, 91 91 + }; 92 92 + 93 93 + /* Certain features recommend 12.5 Hz - 400 Hz ODR */ 94 94 + static const int adxl345_odr_tbl[][2] = { 95 95 + [ADXL345_ODR_0P10HZ] = { 0, 97000 }, 96 96 + [ADXL345_ODR_0P20HZ] = { 0, 195000 }, 97 97 + [ADXL345_ODR_0P39HZ] = { 0, 390000 }, 98 98 + [ADXL345_ODR_0P78HZ] = { 0, 781000 }, 99 99 + [ADXL345_ODR_1P56HZ] = { 1, 562000 }, 100 100 + [ADXL345_ODR_3P13HZ] = { 3, 125000 }, 101 101 + [ADXL345_ODR_6P25HZ] = { 6, 250000 }, 102 102 + [ADXL345_ODR_12P50HZ] = { 12, 500000 }, 103 103 + [ADXL345_ODR_25HZ] = { 25, 0 }, 104 104 + [ADXL345_ODR_50HZ] = { 50, 0 }, 105 105 + [ADXL345_ODR_100HZ] = { 100, 0 }, 106 106 + [ADXL345_ODR_200HZ] = { 200, 0 }, 107 107 + [ADXL345_ODR_400HZ] = { 400, 0 }, 108 108 + [ADXL345_ODR_800HZ] = { 800, 0 }, 109 109 + [ADXL345_ODR_1600HZ] = { 1600, 0 }, 110 110 + [ADXL345_ODR_3200HZ] = { 3200, 0 }, 111 111 + }; 112 112 + 113 113 + /* 114 114 + * Full resolution frequency table: 115 115 + * (g * 2 * 9.80665) / (2^(resolution) - 1) 116 116 + * 117 117 + * resolution := 13 (full) 118 118 + * g := 2|4|8|16 119 119 + * 120 120 + * 2g at 13bit: 0.004789 121 121 + * 4g at 13bit: 0.009578 122 122 + * 8g at 13bit: 0.019156 123 123 + * 16g at 16bit: 0.038312 124 124 + */ 125 125 + static const int adxl345_fullres_range_tbl[][2] = { 126 126 + [ADXL345_2G_RANGE] = { 0, 4789 }, 127 127 + [ADXL345_4G_RANGE] = { 0, 9578 }, 128 128 + [ADXL345_8G_RANGE] = { 0, 19156 }, 129 129 + [ADXL345_16G_RANGE] = { 0, 38312 }, 130 130 + }; 131 131 + 67 132 struct adxl345_state { 68 133 const struct adxl345_chip_info *info; 69 134 struct regmap *regmap; 70 135 bool fifo_delay; /* delay: delay is needed for SPI */ 71 71 - int irq; 72 136 u8 watermark; 73 137 u8 fifo_mode; 74 138 ··· 143 79 __le16 fifo_buf[ADXL345_DIRS * ADXL345_FIFO_SIZE + 1] __aligned(IIO_DMA_MINALIGN); 144 80 }; 145 81 146 146 - static struct iio_event_spec adxl345_events[] = { 82 82 + static const struct iio_event_spec adxl345_events[] = { 147 83 { 148 84 /* single tap */ 149 85 .type = IIO_EV_TYPE_GESTURE, ··· 171 107 BIT(IIO_CHAN_INFO_CALIBBIAS), \ 172 108 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 173 109 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 110 110 + .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE) | \ 111 111 + BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 174 112 .scan_index = (index), \ 175 113 .scan_type = { \ 176 114 .sign = 's', \ ··· 233 167 */ 234 168 static int adxl345_set_measure_en(struct adxl345_state *st, bool en) 235 169 { 236 236 - unsigned int val = en ? ADXL345_POWER_CTL_MEASURE : ADXL345_POWER_CTL_STANDBY; 237 237 - 238 238 - return regmap_write(st->regmap, ADXL345_REG_POWER_CTL, val); 170 170 + return regmap_assign_bits(st->regmap, ADXL345_REG_POWER_CTL, 171 171 + ADXL345_POWER_CTL_MEASURE, en); 239 172 } 240 173 241 174 /* tap */ ··· 448 383 return _adxl345_set_tap_time(st, ADXL345_TAP_TIME_LATENT, val_fract_us); 449 384 } 450 385 386 386 + static int adxl345_find_odr(struct adxl345_state *st, int val, 387 387 + int val2, enum adxl345_odr *odr) 388 388 + { 389 389 + int i; 390 390 + 391 391 + for (i = 0; i < ARRAY_SIZE(adxl345_odr_tbl); i++) { 392 392 + if (val == adxl345_odr_tbl[i][0] && 393 393 + val2 == adxl345_odr_tbl[i][1]) { 394 394 + *odr = i; 395 395 + return 0; 396 396 + } 397 397 + } 398 398 + 399 399 + return -EINVAL; 400 400 + } 401 401 + 402 402 + static int adxl345_set_odr(struct adxl345_state *st, enum adxl345_odr odr) 403 403 + { 404 404 + return regmap_update_bits(st->regmap, ADXL345_REG_BW_RATE, 405 405 + ADXL345_BW_RATE_MSK, 406 406 + FIELD_PREP(ADXL345_BW_RATE_MSK, odr)); 407 407 + } 408 408 + 409 409 + static int adxl345_find_range(struct adxl345_state *st, int val, int val2, 410 410 + enum adxl345_range *range) 411 411 + { 412 412 + int i; 413 413 + 414 414 + for (i = 0; i < ARRAY_SIZE(adxl345_fullres_range_tbl); i++) { 415 415 + if (val == adxl345_fullres_range_tbl[i][0] && 416 416 + val2 == adxl345_fullres_range_tbl[i][1]) { 417 417 + *range = i; 418 418 + return 0; 419 419 + } 420 420 + } 421 421 + 422 422 + return -EINVAL; 423 423 + } 424 424 + 425 425 + static int adxl345_set_range(struct adxl345_state *st, enum adxl345_range range) 426 426 + { 427 427 + return regmap_update_bits(st->regmap, ADXL345_REG_DATA_FORMAT, 428 428 + ADXL345_DATA_FORMAT_RANGE, 429 429 + FIELD_PREP(ADXL345_DATA_FORMAT_RANGE, range)); 430 430 + } 431 431 + 432 432 + static int adxl345_read_avail(struct iio_dev *indio_dev, 433 433 + struct iio_chan_spec const *chan, 434 434 + const int **vals, int *type, 435 435 + int *length, long mask) 436 436 + { 437 437 + switch (mask) { 438 438 + case IIO_CHAN_INFO_SCALE: 439 439 + *vals = (int *)adxl345_fullres_range_tbl; 440 440 + *type = IIO_VAL_INT_PLUS_MICRO; 441 441 + *length = ARRAY_SIZE(adxl345_fullres_range_tbl) * 2; 442 442 + return IIO_AVAIL_LIST; 443 443 + case IIO_CHAN_INFO_SAMP_FREQ: 444 444 + *vals = (int *)adxl345_odr_tbl; 445 445 + *type = IIO_VAL_INT_PLUS_MICRO; 446 446 + *length = ARRAY_SIZE(adxl345_odr_tbl) * 2; 447 447 + return IIO_AVAIL_LIST; 448 448 + } 449 449 + 450 450 + return -EINVAL; 451 451 + } 452 452 + 451 453 static int adxl345_read_raw(struct iio_dev *indio_dev, 452 454 struct iio_chan_spec const *chan, 453 455 int *val, int *val2, long mask) 454 456 { 455 457 struct adxl345_state *st = iio_priv(indio_dev); 456 458 __le16 accel; 457 457 - long long samp_freq_nhz; 458 459 unsigned int regval; 460 460 + enum adxl345_odr odr; 461 461 + enum adxl345_range range; 459 462 int ret; 460 463 461 464 switch (mask) { ··· 542 409 *val = sign_extend32(le16_to_cpu(accel), 12); 543 410 return IIO_VAL_INT; 544 411 case IIO_CHAN_INFO_SCALE: 545 545 - *val = 0; 546 546 - *val2 = st->info->uscale; 412 412 + ret = regmap_read(st->regmap, ADXL345_REG_DATA_FORMAT, &regval); 413 413 + if (ret) 414 414 + return ret; 415 415 + range = FIELD_GET(ADXL345_DATA_FORMAT_RANGE, regval); 416 416 + *val = adxl345_fullres_range_tbl[range][0]; 417 417 + *val2 = adxl345_fullres_range_tbl[range][1]; 547 418 return IIO_VAL_INT_PLUS_MICRO; 548 419 case IIO_CHAN_INFO_CALIBBIAS: 549 420 ret = regmap_read(st->regmap, ··· 565 428 ret = regmap_read(st->regmap, ADXL345_REG_BW_RATE, &regval); 566 429 if (ret) 567 430 return ret; 568 568 - 569 569 - samp_freq_nhz = ADXL345_BASE_RATE_NANO_HZ << 570 570 - (regval & ADXL345_BW_RATE); 571 571 - *val = div_s64_rem(samp_freq_nhz, NANOHZ_PER_HZ, val2); 572 572 - 573 573 - return IIO_VAL_INT_PLUS_NANO; 431 431 + odr = FIELD_GET(ADXL345_BW_RATE_MSK, regval); 432 432 + *val = adxl345_odr_tbl[odr][0]; 433 433 + *val2 = adxl345_odr_tbl[odr][1]; 434 434 + return IIO_VAL_INT_PLUS_MICRO; 574 435 } 575 436 576 437 return -EINVAL; ··· 579 444 int val, int val2, long mask) 580 445 { 581 446 struct adxl345_state *st = iio_priv(indio_dev); 582 582 - s64 n; 447 447 + enum adxl345_range range; 448 448 + enum adxl345_odr odr; 449 449 + int ret; 450 450 + 451 451 + ret = adxl345_set_measure_en(st, false); 452 452 + if (ret) 453 453 + return ret; 583 454 584 455 switch (mask) { 585 456 case IIO_CHAN_INFO_CALIBBIAS: ··· 593 452 * 8-bit resolution at +/- 2g, that is 4x accel data scale 594 453 * factor 595 454 */ 596 596 - return regmap_write(st->regmap, 597 597 - ADXL345_REG_OFS_AXIS(chan->address), 598 598 - val / 4); 455 455 + ret = regmap_write(st->regmap, 456 456 + ADXL345_REG_OFS_AXIS(chan->address), 457 457 + val / 4); 458 458 + if (ret) 459 459 + return ret; 460 460 + break; 599 461 case IIO_CHAN_INFO_SAMP_FREQ: 600 600 - n = div_s64(val * NANOHZ_PER_HZ + val2, 601 601 - ADXL345_BASE_RATE_NANO_HZ); 462 462 + ret = adxl345_find_odr(st, val, val2, &odr); 463 463 + if (ret) 464 464 + return ret; 602 465 603 603 - return regmap_update_bits(st->regmap, ADXL345_REG_BW_RATE, 604 604 - ADXL345_BW_RATE, 605 605 - clamp_val(ilog2(n), 0, 606 606 - ADXL345_BW_RATE)); 466 466 + ret = adxl345_set_odr(st, odr); 467 467 + if (ret) 468 468 + return ret; 469 469 + break; 470 470 + case IIO_CHAN_INFO_SCALE: 471 471 + ret = adxl345_find_range(st, val, val2, &range); 472 472 + if (ret) 473 473 + return ret; 474 474 + 475 475 + ret = adxl345_set_range(st, range); 476 476 + if (ret) 477 477 + return ret; 478 478 + break; 479 479 + default: 480 480 + return -EINVAL; 607 481 } 608 482 609 609 - return -EINVAL; 483 483 + return adxl345_set_measure_en(st, true); 610 484 } 611 485 612 486 static int adxl345_read_event_config(struct iio_dev *indio_dev, ··· 708 552 return IIO_VAL_INT; 709 553 case IIO_EV_INFO_TIMEOUT: 710 554 *val = st->tap_duration_us; 711 711 - *val2 = 1000000; 555 555 + *val2 = MICRO; 712 556 return IIO_VAL_FRACTIONAL; 713 557 case IIO_EV_INFO_RESET_TIMEOUT: 714 558 *val = st->tap_window_us; 715 715 - *val2 = 1000000; 559 559 + *val2 = MICRO; 716 560 return IIO_VAL_FRACTIONAL; 717 561 case IIO_EV_INFO_TAP2_MIN_DELAY: 718 562 *val = st->tap_latent_us; 719 719 - *val2 = 1000000; 563 563 + *val2 = MICRO; 720 564 return IIO_VAL_FRACTIONAL; 721 565 default: 722 566 return -EINVAL; ··· 809 653 switch (mask) { 810 654 case IIO_CHAN_INFO_CALIBBIAS: 811 655 return IIO_VAL_INT; 656 656 + case IIO_CHAN_INFO_SCALE: 657 657 + return IIO_VAL_INT_PLUS_MICRO; 812 658 case IIO_CHAN_INFO_SAMP_FREQ: 813 813 - return IIO_VAL_INT_PLUS_NANO; 659 659 + return IIO_VAL_INT_PLUS_MICRO; 814 660 default: 815 661 return -EINVAL; 816 662 } ··· 824 666 825 667 adxl345_set_measure_en(st, false); 826 668 } 827 827 - 828 828 - static IIO_CONST_ATTR_SAMP_FREQ_AVAIL( 829 829 - "0.09765625 0.1953125 0.390625 0.78125 1.5625 3.125 6.25 12.5 25 50 100 200 400 800 1600 3200" 830 830 - ); 831 831 - 832 832 - static struct attribute *adxl345_attrs[] = { 833 833 - &iio_const_attr_sampling_frequency_available.dev_attr.attr, 834 834 - NULL 835 835 - }; 836 836 - 837 837 - static const struct attribute_group adxl345_attrs_group = { 838 838 - .attrs = adxl345_attrs, 839 839 - }; 840 669 841 670 static int adxl345_set_fifo(struct adxl345_state *st) 842 671 { ··· 885 740 */ 886 741 static int adxl345_fifo_transfer(struct adxl345_state *st, int samples) 887 742 { 888 888 - size_t count; 889 743 int i, ret = 0; 890 744 891 891 - /* count is the 3x the fifo_buf element size, hence 6B */ 892 892 - count = sizeof(st->fifo_buf[0]) * ADXL345_DIRS; 893 745 for (i = 0; i < samples; i++) { 894 894 - /* read 3x 2 byte elements from base address into next fifo_buf position */ 895 746 ret = regmap_bulk_read(st->regmap, ADXL345_REG_XYZ_BASE, 896 896 - st->fifo_buf + (i * count / 2), count); 747 747 + st->fifo_buf + (i * ADXL345_DIRS), 748 748 + sizeof(st->fifo_buf[0]) * ADXL345_DIRS); 897 749 if (ret) 898 750 return ret; 899 751 ··· 1073 931 } 1074 932 1075 933 static const struct iio_info adxl345_info = { 1076 1076 - .attrs = &adxl345_attrs_group, 1077 934 .read_raw = adxl345_read_raw, 1078 935 .write_raw = adxl345_write_raw, 936 936 + .read_avail = adxl345_read_avail, 1079 937 .write_raw_get_fmt = adxl345_write_raw_get_fmt, 1080 938 .read_event_config = adxl345_read_event_config, 1081 939 .write_event_config = adxl345_write_event_config, ··· 1084 942 .debugfs_reg_access = &adxl345_reg_access, 1085 943 .hwfifo_set_watermark = adxl345_set_watermark, 1086 944 }; 945 945 + 946 946 + static int adxl345_get_int_line(struct device *dev, int *irq) 947 947 + { 948 948 + *irq = fwnode_irq_get_byname(dev_fwnode(dev), "INT1"); 949 949 + if (*irq > 0) 950 950 + return ADXL345_INT1; 951 951 + 952 952 + *irq = fwnode_irq_get_byname(dev_fwnode(dev), "INT2"); 953 953 + if (*irq > 0) 954 954 + return ADXL345_INT2; 955 955 + 956 956 + return ADXL345_INT_NONE; 957 957 + } 1087 958 1088 959 /** 1089 960 * adxl345_core_probe() - Probe and setup for the accelerometer. ··· 1128 973 ADXL345_DATA_FORMAT_FULL_RES | 1129 974 ADXL345_DATA_FORMAT_SELF_TEST); 1130 975 unsigned int tap_threshold; 976 976 + int irq; 1131 977 int ret; 1132 978 1133 979 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); ··· 1154 998 indio_dev->channels = adxl345_channels; 1155 999 indio_dev->num_channels = ARRAY_SIZE(adxl345_channels); 1156 1000 indio_dev->available_scan_masks = adxl345_scan_masks; 1001 1001 + 1002 1002 + /* 1003 1003 + * Using I2C at 100kHz would limit the maximum ODR to 200Hz, operation 1004 1004 + * at an output rate above the recommended maximum may result in 1005 1005 + * undesired behavior. 1006 1006 + */ 1007 1007 + ret = adxl345_set_odr(st, ADXL345_ODR_200HZ); 1008 1008 + if (ret) 1009 1009 + return ret; 1010 1010 + 1011 1011 + ret = adxl345_set_range(st, ADXL345_16G_RANGE); 1012 1012 + if (ret) 1013 1013 + return ret; 1157 1014 1158 1015 /* Reset interrupts at start up */ 1159 1016 ret = regmap_write(st->regmap, ADXL345_REG_INT_ENABLE, 0x00); ··· 1213 1044 if (ret) 1214 1045 return ret; 1215 1046 1216 1216 - st->irq = fwnode_irq_get_byname(dev_fwnode(dev), "INT1"); 1217 1217 - if (st->irq < 0) { 1218 1218 - intio = ADXL345_INT2; 1219 1219 - st->irq = fwnode_irq_get_byname(dev_fwnode(dev), "INT2"); 1220 1220 - if (st->irq < 0) 1221 1221 - intio = ADXL345_INT_NONE; 1222 1222 - } 1223 1223 - 1047 1047 + intio = adxl345_get_int_line(dev, &irq); 1224 1048 if (intio != ADXL345_INT_NONE) { 1225 1049 /* 1226 1226 - * Any bits set to 0 in the INT map register send their respective 1227 1227 - * interrupts to the INT1 pin, whereas bits set to 1 send their respective 1228 1228 - * interrupts to the INT2 pin. The intio shall convert this accordingly. 1050 1050 + * In the INT map register, bits set to 0 route their 1051 1051 + * corresponding interrupts to the INT1 pin, while bits set to 1 1052 1052 + * route them to the INT2 pin. The intio should handle this 1053 1053 + * mapping accordingly. 1229 1054 */ 1230 1230 - regval = intio ? 0xff : 0; 1231 1231 - 1232 1232 - ret = regmap_write(st->regmap, ADXL345_REG_INT_MAP, regval); 1055 1055 + ret = regmap_assign_bits(st->regmap, ADXL345_REG_INT_MAP, 1056 1056 + U8_MAX, intio); 1233 1057 if (ret) 1234 1058 return ret; 1235 1059 ··· 1235 1073 if (ret) 1236 1074 return ret; 1237 1075 1238 1238 - ret = devm_request_threaded_irq(dev, st->irq, NULL, 1076 1076 + ret = devm_request_threaded_irq(dev, irq, NULL, 1239 1077 &adxl345_irq_handler, 1240 1078 IRQF_SHARED | IRQF_ONESHOT, 1241 1079 indio_dev->name, indio_dev);

+1 -2

drivers/iio/accel/adxl372.c

reviewed

··· 600 600 601 601 static void adxl372_arrange_axis_data(struct adxl372_state *st, __be16 *sample) 602 602 { 603 603 - __be16 axis_sample[3]; 603 603 + __be16 axis_sample[3] = { }; 604 604 int i = 0; 605 605 606 606 - memset(axis_sample, 0, 3 * sizeof(__be16)); 607 606 if (ADXL372_X_AXIS_EN(st->fifo_axis_mask)) 608 607 axis_sample[i++] = sample[0]; 609 608 if (ADXL372_Y_AXIS_EN(st->fifo_axis_mask))

-3

drivers/iio/accel/bma180.c

reviewed

··· 29 29 #include <linux/iio/trigger_consumer.h> 30 30 #include <linux/iio/triggered_buffer.h> 31 31 32 32 - #define BMA180_DRV_NAME "bma180" 33 33 - #define BMA180_IRQ_NAME "bma180_event" 34 34 - 35 32 enum chip_ids { 36 33 BMA023, 37 34 BMA150,

+1 -4

drivers/iio/accel/bmc150-accel-core.c

reviewed

··· 25 25 26 26 #include "bmc150-accel.h" 27 27 28 28 - #define BMC150_ACCEL_DRV_NAME "bmc150_accel" 29 29 - #define BMC150_ACCEL_IRQ_NAME "bmc150_accel_event" 30 30 - 31 28 #define BMC150_ACCEL_REG_CHIP_ID 0x00 32 29 33 30 #define BMC150_ACCEL_REG_INT_STATUS_2 0x0B ··· 1703 1706 bmc150_accel_irq_handler, 1704 1707 bmc150_accel_irq_thread_handler, 1705 1708 IRQF_TRIGGER_RISING, 1706 1706 - BMC150_ACCEL_IRQ_NAME, 1709 1709 + "bmc150_accel_event", 1707 1710 indio_dev); 1708 1711 if (ret) 1709 1712 goto err_buffer_cleanup;

+11 -1

drivers/iio/accel/kionix-kx022a.c

reviewed

··· 5 5 * ROHM/KIONIX accelerometer driver 6 6 */ 7 7 8 8 + #include <linux/array_size.h> 9 9 + #include <linux/bitmap.h> 8 10 #include <linux/cleanup.h> 9 11 #include <linux/delay.h> 10 12 #include <linux/device.h> 13 13 + #include <linux/errno.h> 14 14 + #include <linux/export.h> 11 15 #include <linux/interrupt.h> 16 16 + #include <linux/math64.h> 17 17 + #include <linux/minmax.h> 12 18 #include <linux/module.h> 13 13 - #include <linux/moduleparam.h> 14 19 #include <linux/mutex.h> 15 20 #include <linux/property.h> 16 21 #include <linux/regmap.h> 17 22 #include <linux/regulator/consumer.h> 18 23 #include <linux/slab.h> 19 24 #include <linux/string_choices.h> 25 25 + #include <linux/sysfs.h> 26 26 + #include <linux/time64.h> 20 27 #include <linux/types.h> 21 28 #include <linux/units.h> 22 29 23 30 #include <linux/iio/iio.h> 31 31 + #include <linux/iio/buffer.h> 24 32 #include <linux/iio/sysfs.h> 25 33 #include <linux/iio/trigger.h> 26 34 #include <linux/iio/trigger_consumer.h> 27 35 #include <linux/iio/triggered_buffer.h> 36 36 + 37 37 + #include <asm/byteorder.h> 28 38 29 39 #include "kionix-kx022a.h" 30 40

+2 -5

drivers/iio/accel/kxcjk-1013.c

reviewed

··· 26 26 #include <linux/iio/triggered_buffer.h> 27 27 #include <linux/iio/accel/kxcjk_1013.h> 28 28 29 29 - #define KXCJK1013_DRV_NAME "kxcjk1013" 30 30 - #define KXCJK1013_IRQ_NAME "kxcjk1013_event" 31 31 - 32 29 #define KXTF9_REG_HP_XOUT_L 0x00 33 30 #define KXTF9_REG_HP_XOUT_H 0x01 34 31 #define KXTF9_REG_HP_YOUT_L 0x02 ··· 1461 1464 kxcjk1013_data_rdy_trig_poll, 1462 1465 kxcjk1013_event_handler, 1463 1466 IRQF_TRIGGER_RISING, 1464 1464 - KXCJK1013_IRQ_NAME, 1467 1467 + "kxcjk1013_event", 1465 1468 indio_dev); 1466 1469 if (ret) 1467 1470 goto err_poweroff; ··· 1671 1674 1672 1675 static struct i2c_driver kxcjk1013_driver = { 1673 1676 .driver = { 1674 1674 - .name = KXCJK1013_DRV_NAME, 1677 1677 + .name = "kxcjk1013", 1675 1678 .acpi_match_table = kx_acpi_match, 1676 1679 .of_match_table = kxcjk1013_of_match, 1677 1680 .pm = pm_ptr(&kxcjk1013_pm_ops),

+2 -4

drivers/iio/accel/mma9551.c

reviewed

··· 17 17 #include <linux/pm_runtime.h> 18 18 #include "mma9551_core.h" 19 19 20 20 - #define MMA9551_DRV_NAME "mma9551" 21 21 - #define MMA9551_IRQ_NAME "mma9551_event" 22 20 #define MMA9551_GPIO_COUNT 4 23 21 24 22 /* Tilt application (inclination in IIO terms). */ ··· 420 422 ret = devm_request_threaded_irq(dev, data->irqs[i], 421 423 NULL, mma9551_event_handler, 422 424 IRQF_TRIGGER_RISING | IRQF_ONESHOT, 423 423 - MMA9551_IRQ_NAME, indio_dev); 425 425 + "mma9551_event", indio_dev); 424 426 if (ret < 0) { 425 427 dev_err(dev, "request irq %d failed\n", data->irqs[i]); 426 428 return ret; ··· 590 592 591 593 static struct i2c_driver mma9551_driver = { 592 594 .driver = { 593 593 - .name = MMA9551_DRV_NAME, 595 595 + .name = "mma9551", 594 596 .acpi_match_table = mma9551_acpi_match, 595 597 .pm = pm_ptr(&mma9551_pm_ops), 596 598 },

+4 -7

drivers/iio/accel/mma9553.c

reviewed

··· 15 15 #include <linux/pm_runtime.h> 16 16 #include "mma9551_core.h" 17 17 18 18 - #define MMA9553_DRV_NAME "mma9553" 19 19 - #define MMA9553_IRQ_NAME "mma9553_event" 20 20 - 21 18 /* Pedometer configuration registers (R/W) */ 22 19 #define MMA9553_REG_CONF_SLEEPMIN 0x00 23 20 #define MMA9553_REG_CONF_SLEEPMAX 0x02 ··· 97 100 ACTIVITY_RUNNING, 98 101 }; 99 102 100 100 - static struct mma9553_event_info { 103 103 + static const struct mma9553_event_info { 101 104 enum iio_chan_type type; 102 105 enum iio_modifier mod; 103 106 enum iio_event_direction dir; ··· 152 155 #define MMA9553_EVENTS_INFO_SIZE ARRAY_SIZE(mma9553_events_info) 153 156 154 157 struct mma9553_event { 155 155 - struct mma9553_event_info *info; 158 158 + const struct mma9553_event_info *info; 156 159 bool enabled; 157 160 }; 158 161 ··· 1099 1102 mma9553_irq_handler, 1100 1103 mma9553_event_handler, 1101 1104 IRQF_TRIGGER_RISING, 1102 1102 - MMA9553_IRQ_NAME, indio_dev); 1105 1105 + "mma9553_event", indio_dev); 1103 1106 if (ret < 0) { 1104 1107 dev_err(&client->dev, "request irq %d failed\n", 1105 1108 client->irq); ··· 1227 1230 1228 1231 static struct i2c_driver mma9553_driver = { 1229 1232 .driver = { 1230 1230 - .name = MMA9553_DRV_NAME, 1233 1233 + .name = "mma9553", 1231 1234 .acpi_match_table = mma9553_acpi_match, 1232 1235 .pm = pm_ptr(&mma9553_pm_ops), 1233 1236 },

+1 -3

drivers/iio/accel/msa311.c

reviewed

··· 897 897 struct { 898 898 __le16 channels[MSA311_SI_Z + 1]; 899 899 aligned_s64 ts; 900 900 - } buf; 901 901 - 902 902 - memset(&buf, 0, sizeof(buf)); 900 900 + } buf = { }; 903 901 904 902 mutex_lock(&msa311->lock); 905 903

+2 -4

drivers/iio/accel/mxc4005.c

reviewed

··· 19 19 #include <linux/iio/trigger_consumer.h> 20 20 21 21 #define MXC4005_DRV_NAME "mxc4005" 22 22 - #define MXC4005_IRQ_NAME "mxc4005_event" 23 23 - #define MXC4005_REGMAP_NAME "mxc4005_regmap" 24 22 25 23 #define MXC4005_REG_XOUT_UPPER 0x03 26 24 #define MXC4005_REG_XOUT_LOWER 0x04 ··· 136 138 } 137 139 138 140 static const struct regmap_config mxc4005_regmap_config = { 139 139 - .name = MXC4005_REGMAP_NAME, 141 141 + .name = "mxc4005_regmap", 140 142 141 143 .reg_bits = 8, 142 144 .val_bits = 8, ··· 491 493 NULL, 492 494 IRQF_TRIGGER_FALLING | 493 495 IRQF_ONESHOT, 494 494 - MXC4005_IRQ_NAME, 496 496 + "mxc4005_event", 495 497 data->dready_trig); 496 498 if (ret) { 497 499 dev_err(&client->dev,

+1 -2

drivers/iio/accel/mxc6255.c

reviewed

··· 17 17 #include <linux/iio/sysfs.h> 18 18 19 19 #define MXC6255_DRV_NAME "mxc6255" 20 20 - #define MXC6255_REGMAP_NAME "mxc6255_regmap" 21 20 22 21 #define MXC6255_REG_XOUT 0x00 23 22 #define MXC6255_REG_YOUT 0x01 ··· 104 105 } 105 106 106 107 static const struct regmap_config mxc6255_regmap_config = { 107 107 - .name = MXC6255_REGMAP_NAME, 108 108 + .name = "mxc6255_regmap", 108 109 109 110 .reg_bits = 8, 110 111 .val_bits = 8,

+11 -18

drivers/iio/accel/sca3000.c

reviewed

··· 369 369 370 370 ret = sca3000_reg_lock_on(st); 371 371 if (ret < 0) 372 372 - goto error_ret; 372 372 + return ret; 373 373 if (ret) { 374 374 ret = __sca3000_unlock_reg_lock(st); 375 375 if (ret) 376 376 - goto error_ret; 376 376 + return ret; 377 377 } 378 378 379 379 /* Set the control select register */ 380 380 ret = sca3000_write_reg(st, SCA3000_REG_CTRL_SEL_ADDR, sel); 381 381 if (ret) 382 382 - goto error_ret; 382 382 + return ret; 383 383 384 384 /* Write the actual value into the register */ 385 385 - ret = sca3000_write_reg(st, SCA3000_REG_CTRL_DATA_ADDR, val); 386 386 - 387 387 - error_ret: 388 388 - return ret; 385 385 + return sca3000_write_reg(st, SCA3000_REG_CTRL_DATA_ADDR, val); 389 386 } 390 387 391 388 /** ··· 399 402 400 403 ret = sca3000_reg_lock_on(st); 401 404 if (ret < 0) 402 402 - goto error_ret; 405 405 + return ret; 403 406 if (ret) { 404 407 ret = __sca3000_unlock_reg_lock(st); 405 408 if (ret) 406 406 - goto error_ret; 409 409 + return ret; 407 410 } 408 411 /* Set the control select register */ 409 412 ret = sca3000_write_reg(st, SCA3000_REG_CTRL_SEL_ADDR, ctrl_reg); 410 413 if (ret) 411 411 - goto error_ret; 414 414 + return ret; 412 415 ret = sca3000_read_data_short(st, SCA3000_REG_CTRL_DATA_ADDR, 1); 413 416 if (ret) 414 414 - goto error_ret; 417 417 + return ret; 415 418 return st->rx[0]; 416 416 - error_ret: 417 417 - return ret; 418 419 } 419 420 420 421 /** ··· 572 577 573 578 ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1); 574 579 if (ret) 575 575 - goto error_ret; 580 580 + return ret; 581 581 + 576 582 switch (SCA3000_REG_MODE_MODE_MASK & st->rx[0]) { 577 583 case SCA3000_REG_MODE_MEAS_MODE_NORMAL: 578 584 *base_freq = info->measurement_mode_freq; ··· 587 591 default: 588 592 ret = -EINVAL; 589 593 } 590 590 - error_ret: 591 594 return ret; 592 595 } 593 596 ··· 829 834 val = st->rx[0]; 830 835 mutex_unlock(&st->lock); 831 836 if (ret) 832 832 - goto error_ret; 837 837 + return ret; 833 838 834 839 switch (val & SCA3000_REG_MODE_MODE_MASK) { 835 840 case SCA3000_REG_MODE_MEAS_MODE_NORMAL: ··· 852 857 break; 853 858 } 854 859 return len; 855 855 - error_ret: 856 856 - return ret; 857 860 } 858 861 859 862 /*

+1 -3

drivers/iio/accel/sca3300.c

reviewed

··· 20 20 #include <linux/iio/trigger_consumer.h> 21 21 #include <linux/iio/triggered_buffer.h> 22 22 23 23 - #define SCA3300_ALIAS "sca3300" 24 24 - 25 23 #define SCA3300_CRC8_POLYNOMIAL 0x1d 26 24 27 25 /* Device mode register */ ··· 672 674 673 675 static struct spi_driver sca3300_driver = { 674 676 .driver = { 675 675 - .name = SCA3300_ALIAS, 677 677 + .name = "sca3300", 676 678 .of_match_table = sca3300_dt_ids, 677 679 }, 678 680 .probe = sca3300_probe,

+1 -2

drivers/iio/accel/stk8312.c

reviewed

··· 46 46 #define STK8312_ALL_CHANNEL_SIZE 3 47 47 48 48 #define STK8312_DRIVER_NAME "stk8312" 49 49 - #define STK8312_IRQ_NAME "stk8312_event" 50 49 51 50 /* 52 51 * The accelerometer has two measurement ranges: ··· 542 543 NULL, 543 544 IRQF_TRIGGER_RISING | 544 545 IRQF_ONESHOT, 545 545 - STK8312_IRQ_NAME, 546 546 + "stk8312_event", 546 547 indio_dev); 547 548 if (ret < 0) { 548 549 dev_err(&client->dev, "request irq %d failed\n",

+1 -2

drivers/iio/accel/stk8ba50.c

reviewed

··· 42 42 #define STK8BA50_ALL_CHANNEL_SIZE 6 43 43 44 44 #define STK8BA50_DRIVER_NAME "stk8ba50" 45 45 - #define STK8BA50_IRQ_NAME "stk8ba50_event" 46 45 47 46 #define STK8BA50_SCALE_AVAIL "0.0384 0.0767 0.1534 0.3069" 48 47 ··· 435 436 NULL, 436 437 IRQF_TRIGGER_RISING | 437 438 IRQF_ONESHOT, 438 438 - STK8BA50_IRQ_NAME, 439 439 + "stk8ba50_event", 439 440 indio_dev); 440 441 if (ret < 0) { 441 442 dev_err(&client->dev, "request irq %d failed\n",

+43

drivers/iio/adc/Kconfig

reviewed

··· 22 22 config AD_SIGMA_DELTA 23 23 tristate 24 24 select IIO_BUFFER 25 25 + select IIO_BUFFER_DMAENGINE 25 26 select IIO_TRIGGERED_BUFFER 27 27 + select SPI_OFFLOAD 26 28 27 29 config AD4000 28 30 tristate "Analog Devices AD4000 ADC Driver" ··· 57 55 To compile this driver as a module, choose M here: the module will be 58 56 called ad4030. 59 57 58 58 + config AD4080 59 59 + tristate "Analog Devices AD4080 high speed ADC" 60 60 + depends on SPI 61 61 + select REGMAP_SPI 62 62 + select IIO_BACKEND 63 63 + help 64 64 + Say yes here to build support for Analog Devices AD4080 65 65 + high speed, low noise, low distortion, 20-bit, Easy Drive, 66 66 + successive approximation register (SAR) analog-to-digital 67 67 + converter (ADC). Supports iio_backended devices for AD4080. 68 68 + 69 69 + To compile this driver as a module, choose M here: the module will be 70 70 + called ad4080. 71 71 + 60 72 config AD4130 61 73 tristate "Analog Device AD4130 ADC Driver" 62 74 depends on SPI ··· 85 69 86 70 To compile this driver as a module, choose M here: the module will be 87 71 called ad4130. 72 72 + 73 73 + 74 74 + config AD4170_4 75 75 + tristate "Analog Device AD4170-4 ADC Driver" 76 76 + depends on SPI 77 77 + select REGMAP_SPI 78 78 + select IIO_BUFFER 79 79 + select IIO_TRIGGERED_BUFFER 80 80 + depends on COMMON_CLK 81 81 + depends on GPIOLIB 82 82 + help 83 83 + Say yes here to build support for Analog Devices AD4170-4 SPI analog 84 84 + to digital converters (ADC). 85 85 + 86 86 + To compile this driver as a module, choose M here: the module will be 87 87 + called ad4170-4. 88 88 89 89 config AD4695 90 90 tristate "Analog Device AD4695 ADC Driver" ··· 284 252 To compile this driver as a module, choose M here: the module will be 285 253 called ad7380. 286 254 255 255 + config AD7405 256 256 + tristate "Analog Device AD7405 ADC Driver" 257 257 + depends on IIO_BACKEND 258 258 + help 259 259 + Say yes here to build support for Analog Devices AD7405, ADUM7701, 260 260 + ADUM7702, ADUM7703 analog to digital converters (ADC). 261 261 + 262 262 + To compile this driver as a module, choose M here: the module will be 263 263 + called ad7405. 264 264 + 287 265 config AD7476 288 266 tristate "Analog Devices AD7476 1-channel ADCs driver and other similar devices from AD and TI" 289 267 depends on SPI ··· 372 330 config AD7768_1 373 331 tristate "Analog Devices AD7768-1 ADC driver" 374 332 depends on SPI 333 333 + select REGULATOR 375 334 select REGMAP_SPI 376 335 select IIO_BUFFER 377 336 select IIO_TRIGGER

+3

drivers/iio/adc/Makefile

reviewed

··· 10 10 obj-$(CONFIG_AD_SIGMA_DELTA) += ad_sigma_delta.o 11 11 obj-$(CONFIG_AD4000) += ad4000.o 12 12 obj-$(CONFIG_AD4030) += ad4030.o 13 13 + obj-$(CONFIG_AD4080) += ad4080.o 13 14 obj-$(CONFIG_AD4130) += ad4130.o 15 15 + obj-$(CONFIG_AD4170_4) += ad4170-4.o 14 16 obj-$(CONFIG_AD4695) += ad4695.o 15 17 obj-$(CONFIG_AD4851) += ad4851.o 16 18 obj-$(CONFIG_AD7091R) += ad7091r-base.o ··· 28 26 obj-$(CONFIG_AD7292) += ad7292.o 29 27 obj-$(CONFIG_AD7298) += ad7298.o 30 28 obj-$(CONFIG_AD7380) += ad7380.o 29 29 + obj-$(CONFIG_AD7405) += ad7405.o 31 30 obj-$(CONFIG_AD7476) += ad7476.o 32 31 obj-$(CONFIG_AD7606_IFACE_PARALLEL) += ad7606_par.o 33 32 obj-$(CONFIG_AD7606_IFACE_SPI) += ad7606_spi.o

+1 -1

drivers/iio/adc/ad4000.c

reviewed

··· 554 554 val = mult_frac(st->vref_mv, MICRO, st->gain_milli); 555 555 556 556 /* Would multiply by NANO here but we multiplied by extra MILLI */ 557 557 - tmp2 = shift_right((u64)val * MICRO, scale_bits); 557 557 + tmp2 = (u64)val * MICRO >> scale_bits; 558 558 tmp0 = div_s64_rem(tmp2, NANO, &tmp1); 559 559 560 560 /* Store scale for when span compression is disabled */

+619

drivers/iio/adc/ad4080.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0-only 2 2 + /* 3 3 + * Analog Devices AD4080 SPI ADC driver 4 4 + * 5 5 + * Copyright 2025 Analog Devices Inc. 6 6 + */ 7 7 + 8 8 + #include <linux/array_size.h> 9 9 + #include <linux/bitfield.h> 10 10 + #include <linux/bits.h> 11 11 + #include <linux/clk.h> 12 12 + #include <linux/device.h> 13 13 + #include <linux/err.h> 14 14 + #include <linux/iio/backend.h> 15 15 + #include <linux/iio/iio.h> 16 16 + #include <linux/mod_devicetable.h> 17 17 + #include <linux/module.h> 18 18 + #include <linux/mutex.h> 19 19 + #include <linux/regmap.h> 20 20 + #include <linux/regulator/consumer.h> 21 21 + #include <linux/spi/spi.h> 22 22 + #include <linux/types.h> 23 23 + #include <linux/unaligned.h> 24 24 + #include <linux/units.h> 25 25 + 26 26 + /* Register Definition */ 27 27 + #define AD4080_REG_INTERFACE_CONFIG_A 0x00 28 28 + #define AD4080_REG_INTERFACE_CONFIG_B 0x01 29 29 + #define AD4080_REG_DEVICE_CONFIG 0x02 30 30 + #define AD4080_REG_CHIP_TYPE 0x03 31 31 + #define AD4080_REG_PRODUCT_ID_L 0x04 32 32 + #define AD4080_REG_PRODUCT_ID_H 0x05 33 33 + #define AD4080_REG_CHIP_GRADE 0x06 34 34 + #define AD4080_REG_SCRATCH_PAD 0x0A 35 35 + #define AD4080_REG_SPI_REVISION 0x0B 36 36 + #define AD4080_REG_VENDOR_L 0x0C 37 37 + #define AD4080_REG_VENDOR_H 0x0D 38 38 + #define AD4080_REG_STREAM_MODE 0x0E 39 39 + #define AD4080_REG_TRANSFER_CONFIG 0x0F 40 40 + #define AD4080_REG_INTERFACE_CONFIG_C 0x10 41 41 + #define AD4080_REG_INTERFACE_STATUS_A 0x11 42 42 + #define AD4080_REG_DEVICE_STATUS 0x14 43 43 + #define AD4080_REG_ADC_DATA_INTF_CONFIG_A 0x15 44 44 + #define AD4080_REG_ADC_DATA_INTF_CONFIG_B 0x16 45 45 + #define AD4080_REG_ADC_DATA_INTF_CONFIG_C 0x17 46 46 + #define AD4080_REG_PWR_CTRL 0x18 47 47 + #define AD4080_REG_GPIO_CONFIG_A 0x19 48 48 + #define AD4080_REG_GPIO_CONFIG_B 0x1A 49 49 + #define AD4080_REG_GPIO_CONFIG_C 0x1B 50 50 + #define AD4080_REG_GENERAL_CONFIG 0x1C 51 51 + #define AD4080_REG_FIFO_WATERMARK_LSB 0x1D 52 52 + #define AD4080_REG_FIFO_WATERMARK_MSB 0x1E 53 53 + #define AD4080_REG_EVENT_HYSTERESIS_LSB 0x1F 54 54 + #define AD4080_REG_EVENT_HYSTERESIS_MSB 0x20 55 55 + #define AD4080_REG_EVENT_DETECTION_HI_LSB 0x21 56 56 + #define AD4080_REG_EVENT_DETECTION_HI_MSB 0x22 57 57 + #define AD4080_REG_EVENT_DETECTION_LO_LSB 0x23 58 58 + #define AD4080_REG_EVENT_DETECTION_LO_MSB 0x24 59 59 + #define AD4080_REG_OFFSET_LSB 0x25 60 60 + #define AD4080_REG_OFFSET_MSB 0x26 61 61 + #define AD4080_REG_GAIN_LSB 0x27 62 62 + #define AD4080_REG_GAIN_MSB 0x28 63 63 + #define AD4080_REG_FILTER_CONFIG 0x29 64 64 + 65 65 + /* AD4080_REG_INTERFACE_CONFIG_A Bit Definition */ 66 66 + #define AD4080_INTERFACE_CONFIG_A_SW_RESET (BIT(7) | BIT(0)) 67 67 + #define AD4080_INTERFACE_CONFIG_A_ADDR_ASC BIT(5) 68 68 + #define AD4080_INTERFACE_CONFIG_A_SDO_ENABLE BIT(4) 69 69 + 70 70 + /* AD4080_REG_INTERFACE_CONFIG_B Bit Definition */ 71 71 + #define AD4080_INTERFACE_CONFIG_B_SINGLE_INST BIT(7) 72 72 + #define AD4080_INTERFACE_CONFIG_B_SHORT_INST BIT(3) 73 73 + 74 74 + /* AD4080_REG_DEVICE_CONFIG Bit Definition */ 75 75 + #define AD4080_DEVICE_CONFIG_OPERATING_MODES_MSK GENMASK(1, 0) 76 76 + 77 77 + /* AD4080_REG_TRANSFER_CONFIG Bit Definition */ 78 78 + #define AD4080_TRANSFER_CONFIG_KEEP_STREAM_LENGTH_VAL BIT(2) 79 79 + 80 80 + /* AD4080_REG_INTERFACE_CONFIG_C Bit Definition */ 81 81 + #define AD4080_INTERFACE_CONFIG_C_STRICT_REG_ACCESS BIT(5) 82 82 + 83 83 + /* AD4080_REG_ADC_DATA_INTF_CONFIG_A Bit Definition */ 84 84 + #define AD4080_ADC_DATA_INTF_CONFIG_A_RESERVED_CONFIG_A BIT(6) 85 85 + #define AD4080_ADC_DATA_INTF_CONFIG_A_INTF_CHK_EN BIT(4) 86 86 + #define AD4080_ADC_DATA_INTF_CONFIG_A_SPI_LVDS_LANES BIT(2) 87 87 + #define AD4080_ADC_DATA_INTF_CONFIG_A_DATA_INTF_MODE BIT(0) 88 88 + 89 89 + /* AD4080_REG_ADC_DATA_INTF_CONFIG_B Bit Definition */ 90 90 + #define AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_CLK_CNT_MSK GENMASK(7, 4) 91 91 + #define AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_SELF_CLK_MODE BIT(3) 92 92 + #define AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_EN BIT(0) 93 93 + 94 94 + /* AD4080_REG_ADC_DATA_INTF_CONFIG_C Bit Definition */ 95 95 + #define AD4080_ADC_DATA_INTF_CONFIG_C_LVDS_VOD_MSK GENMASK(6, 4) 96 96 + 97 97 + /* AD4080_REG_PWR_CTRL Bit Definition */ 98 98 + #define AD4080_PWR_CTRL_ANA_DIG_LDO_PD BIT(1) 99 99 + #define AD4080_PWR_CTRL_INTF_LDO_PD BIT(0) 100 100 + 101 101 + /* AD4080_REG_GPIO_CONFIG_A Bit Definition */ 102 102 + #define AD4080_GPIO_CONFIG_A_GPO_1_EN BIT(1) 103 103 + #define AD4080_GPIO_CONFIG_A_GPO_0_EN BIT(0) 104 104 + 105 105 + /* AD4080_REG_GPIO_CONFIG_B Bit Definition */ 106 106 + #define AD4080_GPIO_CONFIG_B_GPIO_1_SEL_MSK GENMASK(7, 4) 107 107 + #define AD4080_GPIO_CONFIG_B_GPIO_0_SEL_MSK GENMASK(3, 0) 108 108 + #define AD4080_GPIO_CONFIG_B_GPIO_SPI_SDO 0 109 109 + #define AD4080_GPIO_CONFIG_B_GPIO_FIFO_FULL 1 110 110 + #define AD4080_GPIO_CONFIG_B_GPIO_FIFO_READ_DONE 2 111 111 + #define AD4080_GPIO_CONFIG_B_GPIO_FILTER_RES_RDY 3 112 112 + #define AD4080_GPIO_CONFIG_B_GPIO_H_THRESH 4 113 113 + #define AD4080_GPIO_CONFIG_B_GPIO_L_THRESH 5 114 114 + #define AD4080_GPIO_CONFIG_B_GPIO_STATUS_ALERT 6 115 115 + #define AD4080_GPIO_CONFIG_B_GPIO_GPIO_DATA 7 116 116 + #define AD4080_GPIO_CONFIG_B_GPIO_FILTER_SYNC 8 117 117 + #define AD4080_GPIO_CONFIG_B_GPIO_EXTERNAL_EVENT 9 118 118 + 119 119 + /* AD4080_REG_FIFO_CONFIG Bit Definition */ 120 120 + #define AD4080_FIFO_CONFIG_FIFO_MODE_MSK GENMASK(1, 0) 121 121 + 122 122 + /* AD4080_REG_FILTER_CONFIG Bit Definition */ 123 123 + #define AD4080_FILTER_CONFIG_SINC_DEC_RATE_MSK GENMASK(6, 3) 124 124 + #define AD4080_FILTER_CONFIG_FILTER_SEL_MSK GENMASK(1, 0) 125 125 + 126 126 + /* Miscellaneous Definitions */ 127 127 + #define AD4080_SPI_READ BIT(7) 128 128 + #define AD4080_CHIP_ID GENMASK(2, 0) 129 129 + 130 130 + #define AD4080_LVDS_CNV_CLK_CNT_MAX 7 131 131 + 132 132 + #define AD4080_MAX_SAMP_FREQ 40000000 133 133 + #define AD4080_MIN_SAMP_FREQ 1250000 134 134 + 135 135 + enum ad4080_filter_type { 136 136 + FILTER_NONE, 137 137 + SINC_1, 138 138 + SINC_5, 139 139 + SINC_5_COMP 140 140 + }; 141 141 + 142 142 + static const unsigned int ad4080_scale_table[][2] = { 143 143 + { 6000, 0 }, 144 144 + }; 145 145 + 146 146 + static const char *const ad4080_filter_type_iio_enum[] = { 147 147 + [FILTER_NONE] = "none", 148 148 + [SINC_1] = "sinc1", 149 149 + [SINC_5] = "sinc5", 150 150 + [SINC_5_COMP] = "sinc5+pf1", 151 151 + }; 152 152 + 153 153 + static const int ad4080_dec_rate_avail[] = { 154 154 + 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 155 155 + }; 156 156 + 157 157 + static const int ad4080_dec_rate_none[] = { 1 }; 158 158 + 159 159 + static const char * const ad4080_power_supplies[] = { 160 160 + "vdd33", "vdd11", "vddldo", "iovdd", "vrefin", 161 161 + }; 162 162 + 163 163 + struct ad4080_chip_info { 164 164 + const char *name; 165 165 + unsigned int product_id; 166 166 + int num_scales; 167 167 + const unsigned int (*scale_table)[2]; 168 168 + const struct iio_chan_spec *channels; 169 169 + unsigned int num_channels; 170 170 + }; 171 171 + 172 172 + struct ad4080_state { 173 173 + struct regmap *regmap; 174 174 + struct iio_backend *back; 175 175 + const struct ad4080_chip_info *info; 176 176 + /* 177 177 + * Synchronize access to members the of driver state, and ensure 178 178 + * atomicity of consecutive regmap operations. 179 179 + */ 180 180 + struct mutex lock; 181 181 + unsigned int num_lanes; 182 182 + unsigned int dec_rate; 183 183 + unsigned long clk_rate; 184 184 + enum ad4080_filter_type filter_type; 185 185 + bool lvds_cnv_en; 186 186 + }; 187 187 + 188 188 + static const struct regmap_config ad4080_regmap_config = { 189 189 + .reg_bits = 16, 190 190 + .val_bits = 8, 191 191 + .read_flag_mask = BIT(7), 192 192 + .max_register = 0x29, 193 193 + }; 194 194 + 195 195 + static int ad4080_reg_access(struct iio_dev *indio_dev, unsigned int reg, 196 196 + unsigned int writeval, unsigned int *readval) 197 197 + { 198 198 + struct ad4080_state *st = iio_priv(indio_dev); 199 199 + 200 200 + if (readval) 201 201 + return regmap_read(st->regmap, reg, readval); 202 202 + 203 203 + return regmap_write(st->regmap, reg, writeval); 204 204 + } 205 205 + 206 206 + static int ad4080_get_scale(struct ad4080_state *st, int *val, int *val2) 207 207 + { 208 208 + unsigned int tmp; 209 209 + 210 210 + tmp = (st->info->scale_table[0][0] * 1000000ULL) >> 211 211 + st->info->channels[0].scan_type.realbits; 212 212 + *val = tmp / 1000000; 213 213 + *val2 = tmp % 1000000; 214 214 + 215 215 + return IIO_VAL_INT_PLUS_NANO; 216 216 + } 217 217 + 218 218 + static unsigned int ad4080_get_dec_rate(struct iio_dev *dev, 219 219 + const struct iio_chan_spec *chan) 220 220 + { 221 221 + struct ad4080_state *st = iio_priv(dev); 222 222 + int ret; 223 223 + unsigned int data; 224 224 + 225 225 + ret = regmap_read(st->regmap, AD4080_REG_FILTER_CONFIG, &data); 226 226 + if (ret) 227 227 + return ret; 228 228 + 229 229 + return 1 << (FIELD_GET(AD4080_FILTER_CONFIG_SINC_DEC_RATE_MSK, data) + 1); 230 230 + } 231 231 + 232 232 + static int ad4080_set_dec_rate(struct iio_dev *dev, 233 233 + const struct iio_chan_spec *chan, 234 234 + unsigned int mode) 235 235 + { 236 236 + struct ad4080_state *st = iio_priv(dev); 237 237 + 238 238 + guard(mutex)(&st->lock); 239 239 + 240 240 + if ((st->filter_type >= SINC_5 && mode >= 512) || mode < 2) 241 241 + return -EINVAL; 242 242 + 243 243 + return regmap_update_bits(st->regmap, AD4080_REG_FILTER_CONFIG, 244 244 + AD4080_FILTER_CONFIG_SINC_DEC_RATE_MSK, 245 245 + FIELD_PREP(AD4080_FILTER_CONFIG_SINC_DEC_RATE_MSK, 246 246 + (ilog2(mode) - 1))); 247 247 + } 248 248 + 249 249 + static int ad4080_read_raw(struct iio_dev *indio_dev, 250 250 + struct iio_chan_spec const *chan, 251 251 + int *val, int *val2, long m) 252 252 + { 253 253 + struct ad4080_state *st = iio_priv(indio_dev); 254 254 + int dec_rate; 255 255 + 256 256 + switch (m) { 257 257 + case IIO_CHAN_INFO_SCALE: 258 258 + return ad4080_get_scale(st, val, val2); 259 259 + case IIO_CHAN_INFO_SAMP_FREQ: 260 260 + dec_rate = ad4080_get_dec_rate(indio_dev, chan); 261 261 + if (dec_rate < 0) 262 262 + return dec_rate; 263 263 + if (st->filter_type == SINC_5_COMP) 264 264 + dec_rate *= 2; 265 265 + if (st->filter_type) 266 266 + *val = DIV_ROUND_CLOSEST(st->clk_rate, dec_rate); 267 267 + else 268 268 + *val = st->clk_rate; 269 269 + return IIO_VAL_INT; 270 270 + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 271 271 + if (st->filter_type == FILTER_NONE) { 272 272 + *val = 1; 273 273 + } else { 274 274 + *val = ad4080_get_dec_rate(indio_dev, chan); 275 275 + if (*val < 0) 276 276 + return *val; 277 277 + } 278 278 + return IIO_VAL_INT; 279 279 + default: 280 280 + return -EINVAL; 281 281 + } 282 282 + } 283 283 + 284 284 + static int ad4080_write_raw(struct iio_dev *indio_dev, 285 285 + struct iio_chan_spec const *chan, 286 286 + int val, int val2, long mask) 287 287 + { 288 288 + struct ad4080_state *st = iio_priv(indio_dev); 289 289 + 290 290 + switch (mask) { 291 291 + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 292 292 + if (st->filter_type == FILTER_NONE && val > 1) 293 293 + return -EINVAL; 294 294 + 295 295 + return ad4080_set_dec_rate(indio_dev, chan, val); 296 296 + default: 297 297 + return -EINVAL; 298 298 + } 299 299 + } 300 300 + 301 301 + static int ad4080_lvds_sync_write(struct ad4080_state *st) 302 302 + { 303 303 + struct device *dev = regmap_get_device(st->regmap); 304 304 + int ret; 305 305 + 306 306 + ret = regmap_set_bits(st->regmap, AD4080_REG_ADC_DATA_INTF_CONFIG_A, 307 307 + AD4080_ADC_DATA_INTF_CONFIG_A_INTF_CHK_EN); 308 308 + if (ret) 309 309 + return ret; 310 310 + 311 311 + ret = iio_backend_interface_data_align(st->back, 10000); 312 312 + if (ret) 313 313 + return dev_err_probe(dev, ret, 314 314 + "Data alignment process failed\n"); 315 315 + 316 316 + dev_dbg(dev, "Success: Pattern correct and Locked!\n"); 317 317 + return regmap_clear_bits(st->regmap, AD4080_REG_ADC_DATA_INTF_CONFIG_A, 318 318 + AD4080_ADC_DATA_INTF_CONFIG_A_INTF_CHK_EN); 319 319 + } 320 320 + 321 321 + static int ad4080_get_filter_type(struct iio_dev *dev, 322 322 + const struct iio_chan_spec *chan) 323 323 + { 324 324 + struct ad4080_state *st = iio_priv(dev); 325 325 + unsigned int data; 326 326 + int ret; 327 327 + 328 328 + ret = regmap_read(st->regmap, AD4080_REG_FILTER_CONFIG, &data); 329 329 + if (ret) 330 330 + return ret; 331 331 + 332 332 + return FIELD_GET(AD4080_FILTER_CONFIG_FILTER_SEL_MSK, data); 333 333 + } 334 334 + 335 335 + static int ad4080_set_filter_type(struct iio_dev *dev, 336 336 + const struct iio_chan_spec *chan, 337 337 + unsigned int mode) 338 338 + { 339 339 + struct ad4080_state *st = iio_priv(dev); 340 340 + int dec_rate; 341 341 + int ret; 342 342 + 343 343 + guard(mutex)(&st->lock); 344 344 + 345 345 + dec_rate = ad4080_get_dec_rate(dev, chan); 346 346 + if (dec_rate < 0) 347 347 + return dec_rate; 348 348 + 349 349 + if (mode >= SINC_5 && dec_rate >= 512) 350 350 + return -EINVAL; 351 351 + 352 352 + ret = iio_backend_filter_type_set(st->back, mode); 353 353 + if (ret) 354 354 + return ret; 355 355 + 356 356 + ret = regmap_update_bits(st->regmap, AD4080_REG_FILTER_CONFIG, 357 357 + AD4080_FILTER_CONFIG_FILTER_SEL_MSK, 358 358 + FIELD_PREP(AD4080_FILTER_CONFIG_FILTER_SEL_MSK, 359 359 + mode)); 360 360 + if (ret) 361 361 + return ret; 362 362 + 363 363 + st->filter_type = mode; 364 364 + 365 365 + return 0; 366 366 + } 367 367 + 368 368 + static int ad4080_read_avail(struct iio_dev *indio_dev, 369 369 + struct iio_chan_spec const *chan, 370 370 + const int **vals, int *type, int *length, 371 371 + long mask) 372 372 + { 373 373 + struct ad4080_state *st = iio_priv(indio_dev); 374 374 + 375 375 + switch (mask) { 376 376 + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 377 377 + switch (st->filter_type) { 378 378 + case FILTER_NONE: 379 379 + *vals = ad4080_dec_rate_none; 380 380 + *length = ARRAY_SIZE(ad4080_dec_rate_none); 381 381 + break; 382 382 + default: 383 383 + *vals = ad4080_dec_rate_avail; 384 384 + *length = st->filter_type >= SINC_5 ? 385 385 + (ARRAY_SIZE(ad4080_dec_rate_avail) - 2) : 386 386 + ARRAY_SIZE(ad4080_dec_rate_avail); 387 387 + break; 388 388 + } 389 389 + *type = IIO_VAL_INT; 390 390 + return IIO_AVAIL_LIST; 391 391 + default: 392 392 + return -EINVAL; 393 393 + } 394 394 + } 395 395 + 396 396 + static const struct iio_info ad4080_iio_info = { 397 397 + .debugfs_reg_access = ad4080_reg_access, 398 398 + .read_raw = ad4080_read_raw, 399 399 + .write_raw = ad4080_write_raw, 400 400 + .read_avail = ad4080_read_avail, 401 401 + }; 402 402 + 403 403 + static const struct iio_enum ad4080_filter_type_enum = { 404 404 + .items = ad4080_filter_type_iio_enum, 405 405 + .num_items = ARRAY_SIZE(ad4080_filter_type_iio_enum), 406 406 + .set = ad4080_set_filter_type, 407 407 + .get = ad4080_get_filter_type, 408 408 + }; 409 409 + 410 410 + static struct iio_chan_spec_ext_info ad4080_ext_info[] = { 411 411 + IIO_ENUM("filter_type", IIO_SHARED_BY_ALL, &ad4080_filter_type_enum), 412 412 + IIO_ENUM_AVAILABLE("filter_type", IIO_SHARED_BY_ALL, 413 413 + &ad4080_filter_type_enum), 414 414 + { } 415 415 + }; 416 416 + 417 417 + static const struct iio_chan_spec ad4080_channel = { 418 418 + .type = IIO_VOLTAGE, 419 419 + .indexed = 1, 420 420 + .channel = 0, 421 421 + .info_mask_separate = BIT(IIO_CHAN_INFO_SCALE), 422 422 + .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | 423 423 + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), 424 424 + .info_mask_shared_by_all_available = 425 425 + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), 426 426 + .ext_info = ad4080_ext_info, 427 427 + .scan_index = 0, 428 428 + .scan_type = { 429 429 + .sign = 's', 430 430 + .realbits = 20, 431 431 + .storagebits = 32, 432 432 + }, 433 433 + }; 434 434 + 435 435 + static const struct ad4080_chip_info ad4080_chip_info = { 436 436 + .name = "ad4080", 437 437 + .product_id = AD4080_CHIP_ID, 438 438 + .scale_table = ad4080_scale_table, 439 439 + .num_scales = ARRAY_SIZE(ad4080_scale_table), 440 440 + .num_channels = 1, 441 441 + .channels = &ad4080_channel, 442 442 + }; 443 443 + 444 444 + static int ad4080_setup(struct iio_dev *indio_dev) 445 445 + { 446 446 + struct ad4080_state *st = iio_priv(indio_dev); 447 447 + struct device *dev = regmap_get_device(st->regmap); 448 448 + unsigned int id; 449 449 + int ret; 450 450 + 451 451 + ret = regmap_write(st->regmap, AD4080_REG_INTERFACE_CONFIG_A, 452 452 + AD4080_INTERFACE_CONFIG_A_SW_RESET); 453 453 + if (ret) 454 454 + return ret; 455 455 + 456 456 + ret = regmap_write(st->regmap, AD4080_REG_INTERFACE_CONFIG_A, 457 457 + AD4080_INTERFACE_CONFIG_A_SDO_ENABLE); 458 458 + if (ret) 459 459 + return ret; 460 460 + 461 461 + ret = regmap_read(st->regmap, AD4080_REG_CHIP_TYPE, &id); 462 462 + if (ret) 463 463 + return ret; 464 464 + 465 465 + if (id != AD4080_CHIP_ID) 466 466 + dev_info(dev, "Unrecognized CHIP_ID 0x%X\n", id); 467 467 + 468 468 + ret = regmap_set_bits(st->regmap, AD4080_REG_GPIO_CONFIG_A, 469 469 + AD4080_GPIO_CONFIG_A_GPO_1_EN); 470 470 + if (ret) 471 471 + return ret; 472 472 + 473 473 + ret = regmap_write(st->regmap, AD4080_REG_GPIO_CONFIG_B, 474 474 + FIELD_PREP(AD4080_GPIO_CONFIG_B_GPIO_1_SEL_MSK, 475 475 + AD4080_GPIO_CONFIG_B_GPIO_FILTER_RES_RDY)); 476 476 + if (ret) 477 477 + return ret; 478 478 + 479 479 + ret = iio_backend_num_lanes_set(st->back, st->num_lanes); 480 480 + if (ret) 481 481 + return ret; 482 482 + 483 483 + if (!st->lvds_cnv_en) 484 484 + return 0; 485 485 + 486 486 + /* Set maximum LVDS Data Transfer Latency */ 487 487 + ret = regmap_update_bits(st->regmap, 488 488 + AD4080_REG_ADC_DATA_INTF_CONFIG_B, 489 489 + AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_CLK_CNT_MSK, 490 490 + FIELD_PREP(AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_CLK_CNT_MSK, 491 491 + AD4080_LVDS_CNV_CLK_CNT_MAX)); 492 492 + if (ret) 493 493 + return ret; 494 494 + 495 495 + if (st->num_lanes > 1) { 496 496 + ret = regmap_set_bits(st->regmap, AD4080_REG_ADC_DATA_INTF_CONFIG_A, 497 497 + AD4080_ADC_DATA_INTF_CONFIG_A_SPI_LVDS_LANES); 498 498 + if (ret) 499 499 + return ret; 500 500 + } 501 501 + 502 502 + ret = regmap_set_bits(st->regmap, 503 503 + AD4080_REG_ADC_DATA_INTF_CONFIG_B, 504 504 + AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_EN); 505 505 + if (ret) 506 506 + return ret; 507 507 + 508 508 + return ad4080_lvds_sync_write(st); 509 509 + } 510 510 + 511 511 + static int ad4080_properties_parse(struct ad4080_state *st) 512 512 + { 513 513 + struct device *dev = regmap_get_device(st->regmap); 514 514 + 515 515 + st->lvds_cnv_en = device_property_read_bool(dev, "adi,lvds-cnv-enable"); 516 516 + 517 517 + st->num_lanes = 1; 518 518 + device_property_read_u32(dev, "adi,num-lanes", &st->num_lanes); 519 519 + if (!st->num_lanes || st->num_lanes > 2) 520 520 + return dev_err_probe(dev, -EINVAL, 521 521 + "Invalid 'adi,num-lanes' value: %u", 522 522 + st->num_lanes); 523 523 + 524 524 + return 0; 525 525 + } 526 526 + 527 527 + static int ad4080_probe(struct spi_device *spi) 528 528 + { 529 529 + struct iio_dev *indio_dev; 530 530 + struct device *dev = &spi->dev; 531 531 + struct ad4080_state *st; 532 532 + struct clk *clk; 533 533 + int ret; 534 534 + 535 535 + indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 536 536 + if (!indio_dev) 537 537 + return -ENOMEM; 538 538 + 539 539 + st = iio_priv(indio_dev); 540 540 + 541 541 + ret = devm_regulator_bulk_get_enable(dev, 542 542 + ARRAY_SIZE(ad4080_power_supplies), 543 543 + ad4080_power_supplies); 544 544 + if (ret) 545 545 + return dev_err_probe(dev, ret, 546 546 + "failed to get and enable supplies\n"); 547 547 + 548 548 + st->regmap = devm_regmap_init_spi(spi, &ad4080_regmap_config); 549 549 + if (IS_ERR(st->regmap)) 550 550 + return PTR_ERR(st->regmap); 551 551 + 552 552 + st->info = spi_get_device_match_data(spi); 553 553 + if (!st->info) 554 554 + return -ENODEV; 555 555 + 556 556 + ret = devm_mutex_init(dev, &st->lock); 557 557 + if (ret) 558 558 + return ret; 559 559 + 560 560 + indio_dev->name = st->info->name; 561 561 + indio_dev->channels = st->info->channels; 562 562 + indio_dev->num_channels = st->info->num_channels; 563 563 + indio_dev->info = &ad4080_iio_info; 564 564 + 565 565 + ret = ad4080_properties_parse(st); 566 566 + if (ret) 567 567 + return ret; 568 568 + 569 569 + clk = devm_clk_get_enabled(&spi->dev, "cnv"); 570 570 + if (IS_ERR(clk)) 571 571 + return PTR_ERR(clk); 572 572 + 573 573 + st->clk_rate = clk_get_rate(clk); 574 574 + 575 575 + st->back = devm_iio_backend_get(dev, NULL); 576 576 + if (IS_ERR(st->back)) 577 577 + return PTR_ERR(st->back); 578 578 + 579 579 + ret = devm_iio_backend_request_buffer(dev, st->back, indio_dev); 580 580 + if (ret) 581 581 + return ret; 582 582 + 583 583 + ret = devm_iio_backend_enable(dev, st->back); 584 584 + if (ret) 585 585 + return ret; 586 586 + 587 587 + ret = ad4080_setup(indio_dev); 588 588 + if (ret) 589 589 + return ret; 590 590 + 591 591 + return devm_iio_device_register(&spi->dev, indio_dev); 592 592 + } 593 593 + 594 594 + static const struct spi_device_id ad4080_id[] = { 595 595 + { "ad4080", (kernel_ulong_t)&ad4080_chip_info }, 596 596 + { } 597 597 + }; 598 598 + MODULE_DEVICE_TABLE(spi, ad4080_id); 599 599 + 600 600 + static const struct of_device_id ad4080_of_match[] = { 601 601 + { .compatible = "adi,ad4080", &ad4080_chip_info }, 602 602 + { } 603 603 + }; 604 604 + MODULE_DEVICE_TABLE(of, ad4080_of_match); 605 605 + 606 606 + static struct spi_driver ad4080_driver = { 607 607 + .driver = { 608 608 + .name = "ad4080", 609 609 + .of_match_table = ad4080_of_match, 610 610 + }, 611 611 + .probe = ad4080_probe, 612 612 + .id_table = ad4080_id, 613 613 + }; 614 614 + module_spi_driver(ad4080_driver); 615 615 + 616 616 + MODULE_AUTHOR("Antoniu Miclaus <antoniu.miclaus@analog.com"); 617 617 + MODULE_DESCRIPTION("Analog Devices AD4080"); 618 618 + MODULE_LICENSE("GPL"); 619 619 + MODULE_IMPORT_NS("IIO_BACKEND");

+3027

drivers/iio/adc/ad4170-4.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0+ 2 2 + /* 3 3 + * Analog Devices AD4170-4 ADC driver 4 4 + * 5 5 + * Copyright (C) 2025 Analog Devices, Inc. 6 6 + * Author: Ana-Maria Cusco <ana-maria.cusco@analog.com> 7 7 + * Author: Marcelo Schmitt <marcelo.schmitt@analog.com> 8 8 + */ 9 9 + 10 10 + #include <linux/array_size.h> 11 11 + #include <linux/bitfield.h> 12 12 + #include <linux/bitmap.h> 13 13 + #include <linux/bitops.h> 14 14 + #include <linux/bits.h> 15 15 + #include <linux/cleanup.h> 16 16 + #include <linux/clk.h> 17 17 + #include <linux/clk-provider.h> 18 18 + #include <linux/delay.h> 19 19 + #include <linux/device.h> 20 20 + #include <linux/err.h> 21 21 + #include <linux/gpio/driver.h> 22 22 + #include <linux/iio/buffer.h> 23 23 + #include <linux/iio/iio.h> 24 24 + #include <linux/iio/trigger.h> 25 25 + #include <linux/iio/trigger_consumer.h> 26 26 + #include <linux/iio/triggered_buffer.h> 27 27 + #include <linux/interrupt.h> 28 28 + #include <linux/irq.h> 29 29 + #include <linux/math64.h> 30 30 + #include <linux/minmax.h> 31 31 + #include <linux/module.h> 32 32 + #include <linux/property.h> 33 33 + #include <linux/regmap.h> 34 34 + #include <linux/regulator/consumer.h> 35 35 + #include <linux/spi/spi.h> 36 36 + #include <linux/time.h> 37 37 + #include <linux/types.h> 38 38 + #include <linux/unaligned.h> 39 39 + #include <linux/units.h> 40 40 + #include <linux/util_macros.h> 41 41 + 42 42 + /* 43 43 + * AD4170 registers 44 44 + * Multibyte register addresses point to the most significant byte which is the 45 45 + * address to use to get the most significant byte first (address accessed is 46 46 + * decremented by one for each data byte) 47 47 + * 48 48 + * Each register address define follows the AD4170_<REG_NAME>_REG format. 49 49 + * Each mask follows the AD4170_<REG_NAME>_<FIELD_NAME> format. 50 50 + * E.g. AD4170_PIN_MUXING_DIG_AUX1_CTRL_MSK is for accessing DIG_AUX1_CTRL field 51 51 + * of PIN_MUXING_REG. 52 52 + * Each constant follows the AD4170_<REG_NAME>_<FIELD_NAME>_<FUNCTION> format. 53 53 + * E.g. AD4170_PIN_MUXING_DIG_AUX1_DISABLED is the value written to 54 54 + * DIG_AUX1_CTRL field of PIN_MUXING register to disable DIG_AUX1 pin. 55 55 + * Some register names and register field names are shortened versions of 56 56 + * their datasheet counterpart names to provide better code readability. 57 57 + */ 58 58 + #define AD4170_CONFIG_A_REG 0x00 59 59 + #define AD4170_DATA_24B_REG 0x1E 60 60 + #define AD4170_PIN_MUXING_REG 0x69 61 61 + #define AD4170_CLOCK_CTRL_REG 0x6B 62 62 + #define AD4170_ADC_CTRL_REG 0x71 63 63 + #define AD4170_CHAN_EN_REG 0x79 64 64 + #define AD4170_CHAN_SETUP_REG(x) (0x81 + 4 * (x)) 65 65 + #define AD4170_CHAN_MAP_REG(x) (0x83 + 4 * (x)) 66 66 + #define AD4170_MISC_REG(x) (0xC1 + 14 * (x)) 67 67 + #define AD4170_AFE_REG(x) (0xC3 + 14 * (x)) 68 68 + #define AD4170_FILTER_REG(x) (0xC5 + 14 * (x)) 69 69 + #define AD4170_FILTER_FS_REG(x) (0xC7 + 14 * (x)) 70 70 + #define AD4170_OFFSET_REG(x) (0xCA + 14 * (x)) 71 71 + #define AD4170_GAIN_REG(x) (0xCD + 14 * (x)) 72 72 + #define AD4170_V_BIAS_REG 0x135 73 73 + #define AD4170_CURRENT_SRC_REG(x) (0x139 + 2 * (x)) 74 74 + #define AD4170_GPIO_MODE_REG 0x191 75 75 + #define AD4170_GPIO_OUTPUT_REG 0x193 76 76 + #define AD4170_GPIO_INPUT_REG 0x195 77 77 + #define AD4170_ADC_CTRL_CONT_READ_EXIT_REG 0x200 /* virtual reg */ 78 78 + 79 79 + #define AD4170_REG_READ_MASK BIT(14) 80 80 + 81 81 + /* AD4170_CONFIG_A_REG - INTERFACE_CONFIG_A REGISTER */ 82 82 + #define AD4170_SW_RESET_MSK (BIT(7) | BIT(0)) 83 83 + 84 84 + /* AD4170_PIN_MUXING_REG */ 85 85 + #define AD4170_PIN_MUXING_DIG_AUX1_CTRL_MSK GENMASK(5, 4) 86 86 + 87 87 + /* AD4170_CLOCK_CTRL_REG */ 88 88 + #define AD4170_CLOCK_CTRL_CLOCKSEL_MSK GENMASK(1, 0) 89 89 + 90 90 + /* AD4170_ADC_CTRL_REG */ 91 91 + #define AD4170_ADC_CTRL_MULTI_DATA_REG_SEL_MSK BIT(7) 92 92 + #define AD4170_ADC_CTRL_CONT_READ_MSK GENMASK(5, 4) 93 93 + #define AD4170_ADC_CTRL_MODE_MSK GENMASK(3, 0) 94 94 + 95 95 + /* AD4170_CHAN_EN_REG */ 96 96 + #define AD4170_CHAN_EN(ch) BIT(ch) 97 97 + 98 98 + /* AD4170_CHAN_SETUP_REG */ 99 99 + #define AD4170_CHAN_SETUP_SETUP_MSK GENMASK(2, 0) 100 100 + 101 101 + /* AD4170_CHAN_MAP_REG */ 102 102 + #define AD4170_CHAN_MAP_AINP_MSK GENMASK(12, 8) 103 103 + #define AD4170_CHAN_MAP_AINM_MSK GENMASK(4, 0) 104 104 + 105 105 + /* AD4170_MISC_REG */ 106 106 + #define AD4170_MISC_CHOP_IEXC_MSK GENMASK(15, 14) 107 107 + #define AD4170_MISC_CHOP_ADC_MSK GENMASK(9, 8) 108 108 + 109 109 + /* AD4170_AFE_REG */ 110 110 + #define AD4170_AFE_REF_BUF_M_MSK GENMASK(11, 10) 111 111 + #define AD4170_AFE_REF_BUF_P_MSK GENMASK(9, 8) 112 112 + #define AD4170_AFE_REF_SELECT_MSK GENMASK(6, 5) 113 113 + #define AD4170_AFE_BIPOLAR_MSK BIT(4) 114 114 + #define AD4170_AFE_PGA_GAIN_MSK GENMASK(3, 0) 115 115 + 116 116 + /* AD4170_FILTER_REG */ 117 117 + #define AD4170_FILTER_FILTER_TYPE_MSK GENMASK(3, 0) 118 118 + 119 119 + /* AD4170_CURRENT_SRC_REG */ 120 120 + #define AD4170_CURRENT_SRC_I_OUT_PIN_MSK GENMASK(12, 8) 121 121 + #define AD4170_CURRENT_SRC_I_OUT_VAL_MSK GENMASK(2, 0) 122 122 + 123 123 + /* AD4170_GPIO_MODE_REG */ 124 124 + #define AD4170_GPIO_MODE_GPIO0_MSK GENMASK(1, 0) 125 125 + #define AD4170_GPIO_MODE_GPIO1_MSK GENMASK(3, 2) 126 126 + #define AD4170_GPIO_MODE_GPIO2_MSK GENMASK(5, 4) 127 127 + #define AD4170_GPIO_MODE_GPIO3_MSK GENMASK(7, 6) 128 128 + 129 129 + /* AD4170_GPIO_OUTPUT_REG */ 130 130 + #define AD4170_GPIO_OUTPUT_GPIO_MSK(x) BIT(x) 131 131 + 132 132 + /* AD4170 register constants */ 133 133 + 134 134 + /* AD4170_CLOCK_CTRL_REG constants */ 135 135 + #define AD4170_CLOCK_CTRL_CLOCKSEL_INT 0x0 136 136 + #define AD4170_CLOCK_CTRL_CLOCKSEL_INT_OUT 0x1 137 137 + #define AD4170_CLOCK_CTRL_CLOCKSEL_EXT 0x2 138 138 + #define AD4170_CLOCK_CTRL_CLOCKSEL_EXT_XTAL 0x3 139 139 + 140 140 + /* AD4170_CHAN_MAP_REG constants */ 141 141 + #define AD4170_CHAN_MAP_AIN(x) (x) 142 142 + #define AD4170_CHAN_MAP_TEMP_SENSOR 17 143 143 + #define AD4170_CHAN_MAP_AVDD_AVSS_P 18 144 144 + #define AD4170_CHAN_MAP_AVDD_AVSS_N 18 145 145 + #define AD4170_CHAN_MAP_IOVDD_DGND_P 19 146 146 + #define AD4170_CHAN_MAP_IOVDD_DGND_N 19 147 147 + #define AD4170_CHAN_MAP_AVSS 23 148 148 + #define AD4170_CHAN_MAP_DGND 24 149 149 + #define AD4170_CHAN_MAP_REFIN1_P 25 150 150 + #define AD4170_CHAN_MAP_REFIN1_N 26 151 151 + #define AD4170_CHAN_MAP_REFIN2_P 27 152 152 + #define AD4170_CHAN_MAP_REFIN2_N 28 153 153 + #define AD4170_CHAN_MAP_REFOUT 29 154 154 + 155 155 + /* AD4170_MISC_REG constants */ 156 156 + #define AD4170_MISC_CHOP_IEXC_PAIR1 0x1 157 157 + #define AD4170_MISC_CHOP_IEXC_PAIR2 0x2 158 158 + #define AD4170_MISC_CHOP_IEXC_BOTH 0x3 159 159 + 160 160 + /* AD4170_PIN_MUXING_REG constants */ 161 161 + #define AD4170_PIN_MUXING_DIG_AUX1_DISABLED 0x0 162 162 + #define AD4170_PIN_MUXING_DIG_AUX1_RDY 0x1 163 163 + 164 164 + /* AD4170_ADC_CTRL_REG constants */ 165 165 + #define AD4170_ADC_CTRL_MODE_CONT 0x0 166 166 + #define AD4170_ADC_CTRL_MODE_SINGLE 0x4 167 167 + #define AD4170_ADC_CTRL_MODE_IDLE 0x7 168 168 + 169 169 + #define AD4170_ADC_CTRL_CONT_READ_DISABLE 0x0 170 170 + #define AD4170_ADC_CTRL_CONT_READ_ENABLE 0x1 171 171 + 172 172 + /* AD4170_FILTER_REG constants */ 173 173 + #define AD4170_FILTER_FILTER_TYPE_SINC5_AVG 0x0 174 174 + #define AD4170_FILTER_FILTER_TYPE_SINC5 0x4 175 175 + #define AD4170_FILTER_FILTER_TYPE_SINC3 0x6 176 176 + 177 177 + /* AD4170_CURRENT_SRC_REG constants */ 178 178 + #define AD4170_CURRENT_SRC_I_OUT_PIN_AIN(x) (x) 179 179 + #define AD4170_CURRENT_SRC_I_OUT_PIN_GPIO(x) ((x) + 17) 180 180 + 181 181 + /* AD4170_GPIO_MODE_REG constants */ 182 182 + #define AD4170_GPIO_MODE_GPIO_INPUT 1 183 183 + #define AD4170_GPIO_MODE_GPIO_OUTPUT 2 184 184 + 185 185 + /* Device properties and auxiliary constants */ 186 186 + 187 187 + #define AD4170_NUM_ANALOG_PINS 9 188 188 + #define AD4170_NUM_GPIO_PINS 4 189 189 + #define AD4170_MAX_ADC_CHANNELS 16 190 190 + #define AD4170_MAX_IIO_CHANNELS (AD4170_MAX_ADC_CHANNELS + 1) 191 191 + #define AD4170_MAX_ANALOG_PINS 8 192 192 + #define AD4170_MAX_SETUPS 8 193 193 + #define AD4170_INVALID_SETUP 9 194 194 + #define AD4170_SPI_INST_PHASE_LEN 2 195 195 + #define AD4170_SPI_MAX_XFER_LEN 6 196 196 + #define AD4170_NUM_CURRENT_SRC 4 197 197 + #define AD4170_DEFAULT_SAMP_RATE (125 * HZ_PER_KHZ) 198 198 + 199 199 + #define AD4170_INT_REF_2_5V 2500000 200 200 + 201 201 + /* Internal and external clock properties */ 202 202 + #define AD4170_INT_CLOCK_16MHZ (16 * HZ_PER_MHZ) 203 203 + #define AD4170_EXT_CLOCK_MHZ_MIN (1 * HZ_PER_MHZ) 204 204 + #define AD4170_EXT_CLOCK_MHZ_MAX (17 * HZ_PER_MHZ) 205 205 + 206 206 + #define AD4170_NUM_PGA_OPTIONS 10 207 207 + 208 208 + /* Digital filter properties */ 209 209 + #define AD4170_SINC3_MIN_FS 4 210 210 + #define AD4170_SINC3_MAX_FS 65532 211 211 + #define AD4170_SINC5_MIN_FS 1 212 212 + #define AD4170_SINC5_MAX_FS 256 213 213 + 214 214 + #define AD4170_GAIN_REG_DEFAULT 0x555555 215 215 + 216 216 + #define AD4170_ADC_CTRL_CONT_READ_EXIT 0xA5 217 217 + 218 218 + /* Analog pin functions */ 219 219 + #define AD4170_PIN_UNASSIGNED 0x00 220 220 + #define AD4170_PIN_ANALOG_IN 0x01 221 221 + #define AD4170_PIN_CURRENT_OUT 0x02 222 222 + #define AD4170_PIN_VBIAS 0x04 223 223 + 224 224 + /* GPIO pin functions */ 225 225 + #define AD4170_GPIO_UNASSIGNED 0x00 226 226 + #define AD4170_GPIO_AC_EXCITATION 0x02 227 227 + #define AD4170_GPIO_OUTPUT 0x04 228 228 + 229 229 + /* Current source */ 230 230 + #define AD4170_CURRENT_SRC_DISABLED 0xFF 231 231 + 232 232 + static const unsigned int ad4170_reg_size[] = { 233 233 + [AD4170_CONFIG_A_REG] = 1, 234 234 + [AD4170_DATA_24B_REG] = 3, 235 235 + [AD4170_PIN_MUXING_REG] = 2, 236 236 + [AD4170_CLOCK_CTRL_REG] = 2, 237 237 + [AD4170_ADC_CTRL_REG] = 2, 238 238 + [AD4170_CHAN_EN_REG] = 2, 239 239 + /* 240 240 + * CHANNEL_SETUP and CHANNEL_MAP register are all 2 byte size each and 241 241 + * their addresses are interleaved such that we have CHANNEL_SETUP0 242 242 + * address followed by CHANNEL_MAP0 address, followed by CHANNEL_SETUP1, 243 243 + * and so on until CHANNEL_MAP15. 244 244 + * Thus, initialize the register size for them only once. 245 245 + */ 246 246 + [AD4170_CHAN_SETUP_REG(0) ... AD4170_CHAN_MAP_REG(AD4170_MAX_ADC_CHANNELS - 1)] = 2, 247 247 + /* 248 248 + * MISC, AFE, FILTER, FILTER_FS, OFFSET, and GAIN register addresses are 249 249 + * also interleaved but MISC, AFE, FILTER, FILTER_FS, OFFSET are 16-bit 250 250 + * while OFFSET, GAIN are 24-bit registers so we can't init them all to 251 251 + * the same size. 252 252 + */ 253 253 + [AD4170_MISC_REG(0) ... AD4170_FILTER_FS_REG(0)] = 2, 254 254 + [AD4170_MISC_REG(1) ... AD4170_FILTER_FS_REG(1)] = 2, 255 255 + [AD4170_MISC_REG(2) ... AD4170_FILTER_FS_REG(2)] = 2, 256 256 + [AD4170_MISC_REG(3) ... AD4170_FILTER_FS_REG(3)] = 2, 257 257 + [AD4170_MISC_REG(4) ... AD4170_FILTER_FS_REG(4)] = 2, 258 258 + [AD4170_MISC_REG(5) ... AD4170_FILTER_FS_REG(5)] = 2, 259 259 + [AD4170_MISC_REG(6) ... AD4170_FILTER_FS_REG(6)] = 2, 260 260 + [AD4170_MISC_REG(7) ... AD4170_FILTER_FS_REG(7)] = 2, 261 261 + [AD4170_OFFSET_REG(0) ... AD4170_GAIN_REG(0)] = 3, 262 262 + [AD4170_OFFSET_REG(1) ... AD4170_GAIN_REG(1)] = 3, 263 263 + [AD4170_OFFSET_REG(2) ... AD4170_GAIN_REG(2)] = 3, 264 264 + [AD4170_OFFSET_REG(3) ... AD4170_GAIN_REG(3)] = 3, 265 265 + [AD4170_OFFSET_REG(4) ... AD4170_GAIN_REG(4)] = 3, 266 266 + [AD4170_OFFSET_REG(5) ... AD4170_GAIN_REG(5)] = 3, 267 267 + [AD4170_OFFSET_REG(6) ... AD4170_GAIN_REG(6)] = 3, 268 268 + [AD4170_OFFSET_REG(7) ... AD4170_GAIN_REG(7)] = 3, 269 269 + [AD4170_V_BIAS_REG] = 2, 270 270 + [AD4170_CURRENT_SRC_REG(0) ... AD4170_CURRENT_SRC_REG(3)] = 2, 271 271 + [AD4170_GPIO_MODE_REG] = 2, 272 272 + [AD4170_GPIO_OUTPUT_REG] = 2, 273 273 + [AD4170_GPIO_INPUT_REG] = 2, 274 274 + [AD4170_ADC_CTRL_CONT_READ_EXIT_REG] = 0, 275 275 + }; 276 276 + 277 277 + enum ad4170_ref_buf { 278 278 + AD4170_REF_BUF_PRE, /* Pre-charge referrence buffer */ 279 279 + AD4170_REF_BUF_FULL, /* Full referrence buffering */ 280 280 + AD4170_REF_BUF_BYPASS, /* Bypass referrence buffering */ 281 281 + }; 282 282 + 283 283 + /* maps adi,positive/negative-reference-buffer property values to enum */ 284 284 + static const char * const ad4170_ref_buf_str[] = { 285 285 + [AD4170_REF_BUF_PRE] = "precharge", 286 286 + [AD4170_REF_BUF_FULL] = "full", 287 287 + [AD4170_REF_BUF_BYPASS] = "disabled", 288 288 + }; 289 289 + 290 290 + enum ad4170_ref_select { 291 291 + AD4170_REF_REFIN1, 292 292 + AD4170_REF_REFIN2, 293 293 + AD4170_REF_REFOUT, 294 294 + AD4170_REF_AVDD, 295 295 + }; 296 296 + 297 297 + enum ad4170_filter_type { 298 298 + AD4170_SINC5_AVG, 299 299 + AD4170_SINC5, 300 300 + AD4170_SINC3, 301 301 + }; 302 302 + 303 303 + enum ad4170_regulator { 304 304 + AD4170_AVDD_SUP, 305 305 + AD4170_AVSS_SUP, 306 306 + AD4170_IOVDD_SUP, 307 307 + AD4170_REFIN1P_SUP, 308 308 + AD4170_REFIN1N_SUP, 309 309 + AD4170_REFIN2P_SUP, 310 310 + AD4170_REFIN2N_SUP, 311 311 + AD4170_MAX_SUP, 312 312 + }; 313 313 + 314 314 + static const char *const ad4170_clk_sel[] = { 315 315 + "ext-clk", "xtal", 316 316 + }; 317 317 + 318 318 + enum ad4170_int_pin_sel { 319 319 + AD4170_INT_PIN_SDO, 320 320 + AD4170_INT_PIN_DIG_AUX1, 321 321 + }; 322 322 + 323 323 + static const char * const ad4170_int_pin_names[] = { 324 324 + [AD4170_INT_PIN_SDO] = "sdo", 325 325 + [AD4170_INT_PIN_DIG_AUX1] = "dig_aux1", 326 326 + }; 327 327 + 328 328 + static const unsigned int ad4170_sinc3_filt_fs_tbl[] = { 329 329 + 4, 8, 12, 16, 20, 40, 48, 80, /* 0 - 7 */ 330 330 + 100, 256, 500, 1000, 5000, 8332, 10000, 25000, /* 8 - 15 */ 331 331 + 50000, 65532, /* 16 - 17 */ 332 332 + }; 333 333 + 334 334 + #define AD4170_MAX_FS_TBL_SIZE ARRAY_SIZE(ad4170_sinc3_filt_fs_tbl) 335 335 + 336 336 + static const unsigned int ad4170_sinc5_filt_fs_tbl[] = { 337 337 + 1, 2, 4, 8, 12, 16, 20, 40, 48, 80, 100, 256, 338 338 + }; 339 339 + 340 340 + static const unsigned int ad4170_iout_pin_tbl[] = { 341 341 + AD4170_CURRENT_SRC_I_OUT_PIN_AIN(0), 342 342 + AD4170_CURRENT_SRC_I_OUT_PIN_AIN(1), 343 343 + AD4170_CURRENT_SRC_I_OUT_PIN_AIN(2), 344 344 + AD4170_CURRENT_SRC_I_OUT_PIN_AIN(3), 345 345 + AD4170_CURRENT_SRC_I_OUT_PIN_AIN(4), 346 346 + AD4170_CURRENT_SRC_I_OUT_PIN_AIN(5), 347 347 + AD4170_CURRENT_SRC_I_OUT_PIN_AIN(6), 348 348 + AD4170_CURRENT_SRC_I_OUT_PIN_AIN(7), 349 349 + AD4170_CURRENT_SRC_I_OUT_PIN_AIN(8), 350 350 + AD4170_CURRENT_SRC_I_OUT_PIN_GPIO(0), 351 351 + AD4170_CURRENT_SRC_I_OUT_PIN_GPIO(1), 352 352 + AD4170_CURRENT_SRC_I_OUT_PIN_GPIO(2), 353 353 + AD4170_CURRENT_SRC_I_OUT_PIN_GPIO(3), 354 354 + }; 355 355 + 356 356 + static const unsigned int ad4170_iout_current_ua_tbl[] = { 357 357 + 0, 10, 50, 100, 250, 500, 1000, 1500, 358 358 + }; 359 359 + 360 360 + enum ad4170_sensor_enum { 361 361 + AD4170_ADC_SENSOR = 0, 362 362 + AD4170_WEIGH_SCALE_SENSOR = 1, 363 363 + AD4170_RTD_SENSOR = 2, 364 364 + AD4170_THERMOCOUPLE_SENSOR = 3, 365 365 + }; 366 366 + 367 367 + /* maps adi,sensor-type property value to enum */ 368 368 + static const char * const ad4170_sensor_type[] = { 369 369 + [AD4170_ADC_SENSOR] = "adc", 370 370 + [AD4170_WEIGH_SCALE_SENSOR] = "weighscale", 371 371 + [AD4170_RTD_SENSOR] = "rtd", 372 372 + [AD4170_THERMOCOUPLE_SENSOR] = "thermocouple", 373 373 + }; 374 374 + 375 375 + struct ad4170_chip_info { 376 376 + const char *name; 377 377 + }; 378 378 + 379 379 + static const struct ad4170_chip_info ad4170_chip_info = { 380 380 + .name = "ad4170-4", 381 381 + }; 382 382 + 383 383 + static const struct ad4170_chip_info ad4190_chip_info = { 384 384 + .name = "ad4190-4", 385 385 + }; 386 386 + 387 387 + static const struct ad4170_chip_info ad4195_chip_info = { 388 388 + .name = "ad4195-4", 389 389 + }; 390 390 + 391 391 + /* 392 392 + * There are 8 of each MISC, AFE, FILTER, FILTER_FS, OFFSET, and GAIN 393 393 + * configuration registers. That is, there are 8 miscellaneous registers, MISC0 394 394 + * to MISC7. Each MISC register is associated with a setup; MISCN is associated 395 395 + * with setup number N. The other 5 above mentioned types of registers have 396 396 + * analogous structure. A setup is a set of those registers. For example, 397 397 + * setup 1 comprises of MISC1, AFE1, FILTER1, FILTER_FS1, OFFSET1, and GAIN1 398 398 + * registers. Also, there are 16 CHANNEL_SETUP registers (CHANNEL_SETUP0 to 399 399 + * CHANNEL_SETUP15). Each channel setup is associated with one of the 8 possible 400 400 + * setups. Thus, AD4170 can support up to 16 channels but, since there are only 401 401 + * 8 available setups, channels must share settings if more than 8 channels are 402 402 + * configured. 403 403 + * 404 404 + * If this struct is modified, ad4170_setup_eq() will probably need to be 405 405 + * updated too. 406 406 + */ 407 407 + struct ad4170_setup { 408 408 + u16 misc; 409 409 + u16 afe; 410 410 + u16 filter; 411 411 + u16 filter_fs; 412 412 + u32 offset; /* For calibration purposes */ 413 413 + u32 gain; /* For calibration purposes */ 414 414 + }; 415 415 + 416 416 + struct ad4170_setup_info { 417 417 + struct ad4170_setup setup; 418 418 + unsigned int enabled_channels; 419 419 + unsigned int channels; 420 420 + }; 421 421 + 422 422 + struct ad4170_chan_info { 423 423 + unsigned int input_range_uv; 424 424 + unsigned int setup_num; /* Index to access state setup_infos array */ 425 425 + struct ad4170_setup setup; /* cached setup */ 426 426 + int offset_tbl[10]; 427 427 + u32 scale_tbl[10][2]; 428 428 + bool initialized; 429 429 + bool enabled; 430 430 + }; 431 431 + 432 432 + static const char * const ad4170_filt_names[] = { 433 433 + [AD4170_SINC5_AVG] = "sinc5+avg", 434 434 + [AD4170_SINC5] = "sinc5", 435 435 + [AD4170_SINC3] = "sinc3", 436 436 + }; 437 437 + 438 438 + struct ad4170_state { 439 439 + struct mutex lock; /* Protect read-modify-write and multi write sequences */ 440 440 + int vrefs_uv[AD4170_MAX_SUP]; 441 441 + u32 mclk_hz; 442 442 + struct ad4170_setup_info setup_infos[AD4170_MAX_SETUPS]; 443 443 + struct ad4170_chan_info chan_infos[AD4170_MAX_ADC_CHANNELS]; 444 444 + struct completion completion; 445 445 + struct iio_chan_spec chans[AD4170_MAX_IIO_CHANNELS]; 446 446 + struct spi_device *spi; 447 447 + struct regmap *regmap; 448 448 + int sps_tbl[ARRAY_SIZE(ad4170_filt_names)][AD4170_MAX_FS_TBL_SIZE][2]; 449 449 + __be32 bounce_buffer[AD4170_MAX_ADC_CHANNELS]; 450 450 + struct spi_message msg; 451 451 + struct spi_transfer xfer; 452 452 + struct iio_trigger *trig; 453 453 + struct clk_hw int_clk_hw; 454 454 + unsigned int clock_ctrl; 455 455 + unsigned int pins_fn[AD4170_NUM_ANALOG_PINS]; 456 456 + int gpio_fn[AD4170_NUM_GPIO_PINS]; 457 457 + unsigned int cur_src_pins[AD4170_NUM_CURRENT_SRC]; 458 458 + struct gpio_chip gpiochip; 459 459 + /* 460 460 + * DMA (thus cache coherency maintenance) requires the transfer buffers 461 461 + * to live in their own cache lines. 462 462 + */ 463 463 + u8 rx_buf[4] __aligned(IIO_DMA_MINALIGN); 464 464 + }; 465 465 + 466 466 + static void ad4170_fill_sps_tbl(struct ad4170_state *st) 467 467 + { 468 468 + unsigned int tmp0, tmp1, i; 469 469 + 470 470 + /* 471 471 + * The ODR can be calculated the same way for sinc5+avg, sinc5, and 472 472 + * sinc3 filter types with the exception that sinc5 filter has a 473 473 + * narrowed range of allowed FILTER_FS values. 474 474 + */ 475 475 + for (i = 0; i < ARRAY_SIZE(ad4170_sinc3_filt_fs_tbl); i++) { 476 476 + tmp0 = div_u64_rem(st->mclk_hz, 32 * ad4170_sinc3_filt_fs_tbl[i], 477 477 + &tmp1); 478 478 + tmp1 = mult_frac(tmp1, MICRO, 32 * ad4170_sinc3_filt_fs_tbl[i]); 479 479 + /* Fill sinc5+avg filter SPS table */ 480 480 + st->sps_tbl[AD4170_SINC5_AVG][i][0] = tmp0; /* Integer part */ 481 481 + st->sps_tbl[AD4170_SINC5_AVG][i][1] = tmp1; /* Fractional part */ 482 482 + 483 483 + /* Fill sinc3 filter SPS table */ 484 484 + st->sps_tbl[AD4170_SINC3][i][0] = tmp0; /* Integer part */ 485 485 + st->sps_tbl[AD4170_SINC3][i][1] = tmp1; /* Fractional part */ 486 486 + } 487 487 + /* Sinc5 filter ODR doesn't use all FILTER_FS bits */ 488 488 + for (i = 0; i < ARRAY_SIZE(ad4170_sinc5_filt_fs_tbl); i++) { 489 489 + tmp0 = div_u64_rem(st->mclk_hz, 32 * ad4170_sinc5_filt_fs_tbl[i], 490 490 + &tmp1); 491 491 + tmp1 = mult_frac(tmp1, MICRO, 32 * ad4170_sinc5_filt_fs_tbl[i]); 492 492 + /* Fill sinc5 filter SPS table */ 493 493 + st->sps_tbl[AD4170_SINC5][i][0] = tmp0; /* Integer part */ 494 494 + st->sps_tbl[AD4170_SINC5][i][1] = tmp1; /* Fractional part */ 495 495 + } 496 496 + } 497 497 + 498 498 + static int ad4170_debugfs_reg_access(struct iio_dev *indio_dev, 499 499 + unsigned int reg, unsigned int writeval, 500 500 + unsigned int *readval) 501 501 + { 502 502 + struct ad4170_state *st = iio_priv(indio_dev); 503 503 + 504 504 + if (readval) 505 505 + return regmap_read(st->regmap, reg, readval); 506 506 + 507 507 + return regmap_write(st->regmap, reg, writeval); 508 508 + } 509 509 + 510 510 + static int ad4170_get_reg_size(struct ad4170_state *st, unsigned int reg, 511 511 + unsigned int *size) 512 512 + { 513 513 + if (reg >= ARRAY_SIZE(ad4170_reg_size)) 514 514 + return -EINVAL; 515 515 + 516 516 + *size = ad4170_reg_size[reg]; 517 517 + 518 518 + return 0; 519 519 + } 520 520 + 521 521 + static int ad4170_reg_write(void *context, unsigned int reg, unsigned int val) 522 522 + { 523 523 + struct ad4170_state *st = context; 524 524 + u8 tx_buf[AD4170_SPI_MAX_XFER_LEN]; 525 525 + unsigned int size; 526 526 + int ret; 527 527 + 528 528 + ret = ad4170_get_reg_size(st, reg, &size); 529 529 + if (ret) 530 530 + return ret; 531 531 + 532 532 + put_unaligned_be16(reg, tx_buf); 533 533 + switch (size) { 534 534 + case 3: 535 535 + put_unaligned_be24(val, &tx_buf[AD4170_SPI_INST_PHASE_LEN]); 536 536 + break; 537 537 + case 2: 538 538 + put_unaligned_be16(val, &tx_buf[AD4170_SPI_INST_PHASE_LEN]); 539 539 + break; 540 540 + case 1: 541 541 + tx_buf[AD4170_SPI_INST_PHASE_LEN] = val; 542 542 + break; 543 543 + case 0: 544 544 + /* Write continuous read exit code */ 545 545 + tx_buf[0] = AD4170_ADC_CTRL_CONT_READ_EXIT; 546 546 + return spi_write_then_read(st->spi, tx_buf, 1, NULL, 0); 547 547 + default: 548 548 + return -EINVAL; 549 549 + } 550 550 + 551 551 + return spi_write_then_read(st->spi, tx_buf, 552 552 + AD4170_SPI_INST_PHASE_LEN + size, NULL, 0); 553 553 + } 554 554 + 555 555 + static int ad4170_reg_read(void *context, unsigned int reg, unsigned int *val) 556 556 + { 557 557 + struct ad4170_state *st = context; 558 558 + u8 tx_buf[AD4170_SPI_INST_PHASE_LEN]; 559 559 + unsigned int size; 560 560 + int ret; 561 561 + 562 562 + put_unaligned_be16(AD4170_REG_READ_MASK | reg, tx_buf); 563 563 + 564 564 + ret = ad4170_get_reg_size(st, reg, &size); 565 565 + if (ret) 566 566 + return ret; 567 567 + 568 568 + ret = spi_write_then_read(st->spi, tx_buf, ARRAY_SIZE(tx_buf), 569 569 + st->rx_buf, size); 570 570 + if (ret) 571 571 + return ret; 572 572 + 573 573 + switch (size) { 574 574 + case 3: 575 575 + *val = get_unaligned_be24(st->rx_buf); 576 576 + return 0; 577 577 + case 2: 578 578 + *val = get_unaligned_be16(st->rx_buf); 579 579 + return 0; 580 580 + case 1: 581 581 + *val = st->rx_buf[0]; 582 582 + return 0; 583 583 + default: 584 584 + return -EINVAL; 585 585 + } 586 586 + } 587 587 + 588 588 + static const struct regmap_config ad4170_regmap_config = { 589 589 + .reg_read = ad4170_reg_read, 590 590 + .reg_write = ad4170_reg_write, 591 591 + }; 592 592 + 593 593 + static bool ad4170_setup_eq(struct ad4170_setup *a, struct ad4170_setup *b) 594 594 + { 595 595 + if (a->misc != b->misc || 596 596 + a->afe != b->afe || 597 597 + a->filter != b->filter || 598 598 + a->filter_fs != b->filter_fs || 599 599 + a->offset != b->offset || 600 600 + a->gain != b->gain) 601 601 + return false; 602 602 + 603 603 + return true; 604 604 + } 605 605 + 606 606 + static int ad4170_find_setup(struct ad4170_state *st, 607 607 + struct ad4170_setup *target_setup, 608 608 + unsigned int *setup_num, bool *overwrite) 609 609 + { 610 610 + unsigned int i; 611 611 + 612 612 + *setup_num = AD4170_INVALID_SETUP; 613 613 + *overwrite = false; 614 614 + 615 615 + for (i = 0; i < AD4170_MAX_SETUPS; i++) { 616 616 + struct ad4170_setup_info *setup_info = &st->setup_infos[i]; 617 617 + 618 618 + /* Immediately accept a matching setup. */ 619 619 + if (ad4170_setup_eq(target_setup, &setup_info->setup)) { 620 620 + *setup_num = i; 621 621 + return 0; 622 622 + } 623 623 + 624 624 + /* Ignore all setups which are used by enabled channels. */ 625 625 + if (setup_info->enabled_channels) 626 626 + continue; 627 627 + 628 628 + /* Find the least used slot. */ 629 629 + if (*setup_num == AD4170_INVALID_SETUP || 630 630 + setup_info->channels < st->setup_infos[*setup_num].channels) 631 631 + *setup_num = i; 632 632 + } 633 633 + 634 634 + if (*setup_num == AD4170_INVALID_SETUP) 635 635 + return -EINVAL; 636 636 + 637 637 + *overwrite = true; 638 638 + return 0; 639 639 + } 640 640 + 641 641 + static void ad4170_unlink_channel(struct ad4170_state *st, unsigned int channel) 642 642 + { 643 643 + struct ad4170_chan_info *chan_info = &st->chan_infos[channel]; 644 644 + struct ad4170_setup_info *setup_info = &st->setup_infos[chan_info->setup_num]; 645 645 + 646 646 + chan_info->setup_num = AD4170_INVALID_SETUP; 647 647 + setup_info->channels--; 648 648 + } 649 649 + 650 650 + static int ad4170_unlink_setup(struct ad4170_state *st, unsigned int setup_num) 651 651 + { 652 652 + unsigned int i; 653 653 + 654 654 + for (i = 0; i < AD4170_MAX_ADC_CHANNELS; i++) { 655 655 + struct ad4170_chan_info *chan_info = &st->chan_infos[i]; 656 656 + 657 657 + if (!chan_info->initialized || chan_info->setup_num != setup_num) 658 658 + continue; 659 659 + 660 660 + ad4170_unlink_channel(st, i); 661 661 + } 662 662 + return 0; 663 663 + } 664 664 + 665 665 + static int ad4170_link_channel_setup(struct ad4170_state *st, 666 666 + unsigned int chan_addr, 667 667 + unsigned int setup_num) 668 668 + { 669 669 + struct ad4170_setup_info *setup_info = &st->setup_infos[setup_num]; 670 670 + struct ad4170_chan_info *chan_info = &st->chan_infos[chan_addr]; 671 671 + int ret; 672 672 + 673 673 + ret = regmap_update_bits(st->regmap, AD4170_CHAN_SETUP_REG(chan_addr), 674 674 + AD4170_CHAN_SETUP_SETUP_MSK, 675 675 + FIELD_PREP(AD4170_CHAN_SETUP_SETUP_MSK, setup_num)); 676 676 + if (ret) 677 677 + return ret; 678 678 + 679 679 + chan_info->setup_num = setup_num; 680 680 + setup_info->channels++; 681 681 + return 0; 682 682 + } 683 683 + 684 684 + static int ad4170_write_setup(struct ad4170_state *st, unsigned int setup_num, 685 685 + struct ad4170_setup *setup) 686 686 + { 687 687 + int ret; 688 688 + 689 689 + /* 690 690 + * It is recommended to place the ADC in standby mode or idle mode to 691 691 + * write to OFFSET and GAIN registers. 692 692 + */ 693 693 + ret = regmap_update_bits(st->regmap, AD4170_ADC_CTRL_REG, 694 694 + AD4170_ADC_CTRL_MODE_MSK, 695 695 + FIELD_PREP(AD4170_ADC_CTRL_MODE_MSK, 696 696 + AD4170_ADC_CTRL_MODE_IDLE)); 697 697 + if (ret) 698 698 + return ret; 699 699 + 700 700 + ret = regmap_write(st->regmap, AD4170_MISC_REG(setup_num), setup->misc); 701 701 + if (ret) 702 702 + return ret; 703 703 + 704 704 + ret = regmap_write(st->regmap, AD4170_AFE_REG(setup_num), setup->afe); 705 705 + if (ret) 706 706 + return ret; 707 707 + 708 708 + ret = regmap_write(st->regmap, AD4170_FILTER_REG(setup_num), 709 709 + setup->filter); 710 710 + if (ret) 711 711 + return ret; 712 712 + 713 713 + ret = regmap_write(st->regmap, AD4170_FILTER_FS_REG(setup_num), 714 714 + setup->filter_fs); 715 715 + if (ret) 716 716 + return ret; 717 717 + 718 718 + ret = regmap_write(st->regmap, AD4170_OFFSET_REG(setup_num), 719 719 + setup->offset); 720 720 + if (ret) 721 721 + return ret; 722 722 + 723 723 + ret = regmap_write(st->regmap, AD4170_GAIN_REG(setup_num), setup->gain); 724 724 + if (ret) 725 725 + return ret; 726 726 + 727 727 + memcpy(&st->setup_infos[setup_num].setup, setup, sizeof(*setup)); 728 728 + return 0; 729 729 + } 730 730 + 731 731 + static int ad4170_write_channel_setup(struct ad4170_state *st, 732 732 + unsigned int chan_addr, bool on_enable) 733 733 + { 734 734 + struct ad4170_chan_info *chan_info = &st->chan_infos[chan_addr]; 735 735 + bool overwrite; 736 736 + int setup_num; 737 737 + int ret; 738 738 + 739 739 + /* 740 740 + * Similar to AD4130 driver, the following cases need to be handled. 741 741 + * 742 742 + * 1. Enabled and linked channel with setup changes: 743 743 + * - Find a setup. If not possible, return error. 744 744 + * - Unlink channel from current setup. 745 745 + * - If the setup found has only disabled channels linked to it, 746 746 + * unlink all channels, and write the new setup to it. 747 747 + * - Link channel to new setup. 748 748 + * 749 749 + * 2. Soon to be enabled and unlinked channel: 750 750 + * - Find a setup. If not possible, return error. 751 751 + * - If the setup found has only disabled channels linked to it, 752 752 + * unlink all channels, and write the new setup to it. 753 753 + * - Link channel to the setup. 754 754 + * 755 755 + * 3. Disabled and linked channel with setup changes: 756 756 + * - Unlink channel from current setup. 757 757 + * 758 758 + * 4. Soon to be enabled and linked channel: 759 759 + * 5. Disabled and unlinked channel with setup changes: 760 760 + * - Do nothing. 761 761 + */ 762 762 + 763 763 + /* Cases 3, 4, and 5 */ 764 764 + if (chan_info->setup_num != AD4170_INVALID_SETUP) { 765 765 + /* Case 4 */ 766 766 + if (on_enable) 767 767 + return 0; 768 768 + 769 769 + /* Case 3 */ 770 770 + if (!chan_info->enabled) { 771 771 + ad4170_unlink_channel(st, chan_addr); 772 772 + return 0; 773 773 + } 774 774 + } else if (!on_enable && !chan_info->enabled) { 775 775 + /* Case 5 */ 776 776 + return 0; 777 777 + } 778 778 + 779 779 + /* Cases 1 & 2 */ 780 780 + ret = ad4170_find_setup(st, &chan_info->setup, &setup_num, &overwrite); 781 781 + if (ret) 782 782 + return ret; 783 783 + 784 784 + if (chan_info->setup_num != AD4170_INVALID_SETUP) 785 785 + /* Case 1 */ 786 786 + ad4170_unlink_channel(st, chan_addr); 787 787 + 788 788 + if (overwrite) { 789 789 + ret = ad4170_unlink_setup(st, setup_num); 790 790 + if (ret) 791 791 + return ret; 792 792 + 793 793 + ret = ad4170_write_setup(st, setup_num, &chan_info->setup); 794 794 + if (ret) 795 795 + return ret; 796 796 + } 797 797 + 798 798 + return ad4170_link_channel_setup(st, chan_addr, setup_num); 799 799 + } 800 800 + 801 801 + static int ad4170_set_channel_enable(struct ad4170_state *st, 802 802 + unsigned int chan_addr, bool status) 803 803 + { 804 804 + struct ad4170_chan_info *chan_info = &st->chan_infos[chan_addr]; 805 805 + struct ad4170_setup_info *setup_info; 806 806 + int ret; 807 807 + 808 808 + if (chan_info->enabled == status) 809 809 + return 0; 810 810 + 811 811 + if (status) { 812 812 + ret = ad4170_write_channel_setup(st, chan_addr, true); 813 813 + if (ret) 814 814 + return ret; 815 815 + } 816 816 + 817 817 + setup_info = &st->setup_infos[chan_info->setup_num]; 818 818 + 819 819 + ret = regmap_update_bits(st->regmap, AD4170_CHAN_EN_REG, 820 820 + AD4170_CHAN_EN(chan_addr), 821 821 + status ? AD4170_CHAN_EN(chan_addr) : 0); 822 822 + if (ret) 823 823 + return ret; 824 824 + 825 825 + setup_info->enabled_channels += status ? 1 : -1; 826 826 + chan_info->enabled = status; 827 827 + return 0; 828 828 + } 829 829 + 830 830 + static int __ad4170_get_filter_type(unsigned int filter) 831 831 + { 832 832 + u16 f_conf = FIELD_GET(AD4170_FILTER_FILTER_TYPE_MSK, filter); 833 833 + 834 834 + switch (f_conf) { 835 835 + case AD4170_FILTER_FILTER_TYPE_SINC5_AVG: 836 836 + return AD4170_SINC5_AVG; 837 837 + case AD4170_FILTER_FILTER_TYPE_SINC5: 838 838 + return AD4170_SINC5; 839 839 + case AD4170_FILTER_FILTER_TYPE_SINC3: 840 840 + return AD4170_SINC3; 841 841 + default: 842 842 + return -EINVAL; 843 843 + } 844 844 + } 845 845 + 846 846 + static int ad4170_set_filter_type(struct iio_dev *indio_dev, 847 847 + struct iio_chan_spec const *chan, 848 848 + unsigned int val) 849 849 + { 850 850 + struct ad4170_state *st = iio_priv(indio_dev); 851 851 + struct ad4170_chan_info *chan_info = &st->chan_infos[chan->address]; 852 852 + struct ad4170_setup *setup = &chan_info->setup; 853 853 + unsigned int filter_type_conf; 854 854 + int ret; 855 855 + 856 856 + switch (val) { 857 857 + case AD4170_SINC5_AVG: 858 858 + filter_type_conf = AD4170_FILTER_FILTER_TYPE_SINC5_AVG; 859 859 + break; 860 860 + case AD4170_SINC5: 861 861 + filter_type_conf = AD4170_FILTER_FILTER_TYPE_SINC5; 862 862 + break; 863 863 + case AD4170_SINC3: 864 864 + filter_type_conf = AD4170_FILTER_FILTER_TYPE_SINC3; 865 865 + break; 866 866 + default: 867 867 + return -EINVAL; 868 868 + } 869 869 + 870 870 + /* 871 871 + * The filters provide the same ODR for a given filter_fs value but 872 872 + * there are different minimum and maximum filter_fs limits for each 873 873 + * filter. The filter_fs value will be adjusted if the current filter_fs 874 874 + * is out of the limits of the just requested filter. Since the 875 875 + * filter_fs value affects the ODR (sampling_frequency), changing the 876 876 + * filter may lead to a change in the sampling frequency. 877 877 + */ 878 878 + scoped_guard(mutex, &st->lock) { 879 879 + if (!iio_device_claim_direct(indio_dev)) 880 880 + return -EBUSY; 881 881 + 882 882 + if (val == AD4170_SINC5_AVG || val == AD4170_SINC3) 883 883 + setup->filter_fs = clamp(val, AD4170_SINC3_MIN_FS, 884 884 + AD4170_SINC3_MAX_FS); 885 885 + else 886 886 + setup->filter_fs = clamp(val, AD4170_SINC5_MIN_FS, 887 887 + AD4170_SINC5_MAX_FS); 888 888 + 889 889 + setup->filter &= ~AD4170_FILTER_FILTER_TYPE_MSK; 890 890 + setup->filter |= FIELD_PREP(AD4170_FILTER_FILTER_TYPE_MSK, 891 891 + filter_type_conf); 892 892 + 893 893 + ret = ad4170_write_channel_setup(st, chan->address, false); 894 894 + iio_device_release_direct(indio_dev); 895 895 + } 896 896 + 897 897 + return ret; 898 898 + } 899 899 + 900 900 + static int ad4170_get_filter_type(struct iio_dev *indio_dev, 901 901 + struct iio_chan_spec const *chan) 902 902 + { 903 903 + struct ad4170_state *st = iio_priv(indio_dev); 904 904 + struct ad4170_chan_info *chan_info = &st->chan_infos[chan->address]; 905 905 + struct ad4170_setup *setup = &chan_info->setup; 906 906 + 907 907 + return __ad4170_get_filter_type(setup->filter); 908 908 + } 909 909 + 910 910 + static const struct iio_enum ad4170_filter_type_enum = { 911 911 + .items = ad4170_filt_names, 912 912 + .num_items = ARRAY_SIZE(ad4170_filt_names), 913 913 + .get = ad4170_get_filter_type, 914 914 + .set = ad4170_set_filter_type, 915 915 + }; 916 916 + 917 917 + static const struct iio_chan_spec_ext_info ad4170_filter_type_ext_info[] = { 918 918 + IIO_ENUM("filter_type", IIO_SEPARATE, &ad4170_filter_type_enum), 919 919 + IIO_ENUM_AVAILABLE("filter_type", IIO_SHARED_BY_TYPE, 920 920 + &ad4170_filter_type_enum), 921 921 + { } 922 922 + }; 923 923 + 924 924 + static const struct iio_chan_spec ad4170_channel_template = { 925 925 + .type = IIO_VOLTAGE, 926 926 + .indexed = 1, 927 927 + .differential = 1, 928 928 + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 929 929 + BIT(IIO_CHAN_INFO_SCALE) | 930 930 + BIT(IIO_CHAN_INFO_CALIBBIAS) | 931 931 + BIT(IIO_CHAN_INFO_CALIBSCALE) | 932 932 + BIT(IIO_CHAN_INFO_SAMP_FREQ) | 933 933 + BIT(IIO_CHAN_INFO_OFFSET), 934 934 + .info_mask_separate_available = BIT(IIO_CHAN_INFO_SCALE) | 935 935 + BIT(IIO_CHAN_INFO_SAMP_FREQ), 936 936 + .ext_info = ad4170_filter_type_ext_info, 937 937 + .scan_type = { 938 938 + .realbits = 24, 939 939 + .storagebits = 32, 940 940 + .shift = 8, 941 941 + .endianness = IIO_BE, 942 942 + }, 943 943 + }; 944 944 + 945 945 + static const struct iio_chan_spec ad4170_temp_channel_template = { 946 946 + .type = IIO_TEMP, 947 947 + .indexed = 0, 948 948 + .channel = 17, 949 949 + .channel2 = 17, 950 950 + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 951 951 + BIT(IIO_CHAN_INFO_SCALE) | 952 952 + BIT(IIO_CHAN_INFO_OFFSET) | 953 953 + BIT(IIO_CHAN_INFO_CALIBSCALE) | 954 954 + BIT(IIO_CHAN_INFO_CALIBBIAS) | 955 955 + BIT(IIO_CHAN_INFO_SAMP_FREQ), 956 956 + .info_mask_separate_available = BIT(IIO_CHAN_INFO_SAMP_FREQ), 957 957 + .scan_type = { 958 958 + .sign = 's', 959 959 + .realbits = 24, 960 960 + .storagebits = 32, 961 961 + .shift = 8, 962 962 + .endianness = IIO_BE, 963 963 + }, 964 964 + }; 965 965 + 966 966 + /* 967 967 + * Receives the number of a multiplexed AD4170 input (ain_n), and stores the 968 968 + * voltage (in µV) of the specified input into ain_voltage. If the input number 969 969 + * is a ordinary analog input (AIN0 to AIN8), stores zero into ain_voltage. 970 970 + * If a voltage regulator required by a special input is unavailable, return 971 971 + * error code. Return 0 on success. 972 972 + */ 973 973 + static int ad4170_get_ain_voltage_uv(struct ad4170_state *st, int ain_n, 974 974 + int *ain_voltage) 975 975 + { 976 976 + struct device *dev = &st->spi->dev; 977 977 + int v_diff; 978 978 + 979 979 + *ain_voltage = 0; 980 980 + /* 981 981 + * The voltage bias (vbias) sets the common-mode voltage of the channel 982 982 + * to (AVDD + AVSS)/2. If provided, AVSS supply provides the magnitude 983 983 + * (absolute value) of the negative voltage supplied to the AVSS pin. 984 984 + * So, we do AVDD - AVSS to compute the DC voltage generated by the bias 985 985 + * voltage generator. 986 986 + */ 987 987 + if (st->pins_fn[ain_n] & AD4170_PIN_VBIAS) { 988 988 + int v_diff = st->vrefs_uv[AD4170_AVDD_SUP] - st->vrefs_uv[AD4170_AVSS_SUP]; 989 989 + *ain_voltage = v_diff / 2; 990 990 + return 0; 991 991 + } 992 992 + 993 993 + if (ain_n <= AD4170_CHAN_MAP_TEMP_SENSOR) 994 994 + return 0; 995 995 + 996 996 + switch (ain_n) { 997 997 + case AD4170_CHAN_MAP_AVDD_AVSS_N: 998 998 + v_diff = st->vrefs_uv[AD4170_AVDD_SUP] - st->vrefs_uv[AD4170_AVSS_SUP]; 999 999 + *ain_voltage = v_diff / 5; 1000 1000 + return 0; 1001 1001 + case AD4170_CHAN_MAP_IOVDD_DGND_N: 1002 1002 + *ain_voltage = st->vrefs_uv[AD4170_IOVDD_SUP] / 5; 1003 1003 + return 0; 1004 1004 + case AD4170_CHAN_MAP_AVSS: 1005 1005 + *ain_voltage = st->vrefs_uv[AD4170_AVSS_SUP]; 1006 1006 + return 0; 1007 1007 + case AD4170_CHAN_MAP_DGND: 1008 1008 + *ain_voltage = 0; 1009 1009 + return 0; 1010 1010 + case AD4170_CHAN_MAP_REFIN1_P: 1011 1011 + if (st->vrefs_uv[AD4170_REFIN1P_SUP] == -ENODEV) 1012 1012 + return dev_err_probe(dev, -ENODEV, 1013 1013 + "input set to REFIN+ but ref not provided\n"); 1014 1014 + 1015 1015 + *ain_voltage = st->vrefs_uv[AD4170_REFIN1P_SUP]; 1016 1016 + return 0; 1017 1017 + case AD4170_CHAN_MAP_REFIN1_N: 1018 1018 + if (st->vrefs_uv[AD4170_REFIN1N_SUP] == -ENODEV) 1019 1019 + return dev_err_probe(dev, -ENODEV, 1020 1020 + "input set to REFIN- but ref not provided\n"); 1021 1021 + 1022 1022 + *ain_voltage = st->vrefs_uv[AD4170_REFIN1N_SUP]; 1023 1023 + return 0; 1024 1024 + case AD4170_CHAN_MAP_REFIN2_P: 1025 1025 + if (st->vrefs_uv[AD4170_REFIN2P_SUP] == -ENODEV) 1026 1026 + return dev_err_probe(dev, -ENODEV, 1027 1027 + "input set to REFIN2+ but ref not provided\n"); 1028 1028 + 1029 1029 + *ain_voltage = st->vrefs_uv[AD4170_REFIN2P_SUP]; 1030 1030 + return 0; 1031 1031 + case AD4170_CHAN_MAP_REFIN2_N: 1032 1032 + if (st->vrefs_uv[AD4170_REFIN2N_SUP] == -ENODEV) 1033 1033 + return dev_err_probe(dev, -ENODEV, 1034 1034 + "input set to REFIN2- but ref not provided\n"); 1035 1035 + 1036 1036 + *ain_voltage = st->vrefs_uv[AD4170_REFIN2N_SUP]; 1037 1037 + return 0; 1038 1038 + case AD4170_CHAN_MAP_REFOUT: 1039 1039 + /* REFOUT is 2.5V relative to AVSS so take that into account */ 1040 1040 + *ain_voltage = st->vrefs_uv[AD4170_AVSS_SUP] + AD4170_INT_REF_2_5V; 1041 1041 + return 0; 1042 1042 + default: 1043 1043 + return -EINVAL; 1044 1044 + } 1045 1045 + } 1046 1046 + 1047 1047 + static int ad4170_validate_analog_input(struct ad4170_state *st, int pin) 1048 1048 + { 1049 1049 + if (pin <= AD4170_MAX_ANALOG_PINS) { 1050 1050 + if (st->pins_fn[pin] & AD4170_PIN_CURRENT_OUT) 1051 1051 + return dev_err_probe(&st->spi->dev, -EINVAL, 1052 1052 + "Pin %d already used with fn %u.\n", 1053 1053 + pin, st->pins_fn[pin]); 1054 1054 + 1055 1055 + st->pins_fn[pin] |= AD4170_PIN_ANALOG_IN; 1056 1056 + } 1057 1057 + return 0; 1058 1058 + } 1059 1059 + 1060 1060 + static int ad4170_validate_channel_input(struct ad4170_state *st, int pin, bool com) 1061 1061 + { 1062 1062 + /* Check common-mode input pin is mapped to a special input. */ 1063 1063 + if (com && (pin < AD4170_CHAN_MAP_AVDD_AVSS_P || pin > AD4170_CHAN_MAP_REFOUT)) 1064 1064 + return dev_err_probe(&st->spi->dev, -EINVAL, 1065 1065 + "Invalid common-mode input pin number. %d\n", 1066 1066 + pin); 1067 1067 + 1068 1068 + /* Check differential input pin is mapped to a analog input pin. */ 1069 1069 + if (!com && pin > AD4170_MAX_ANALOG_PINS) 1070 1070 + return dev_err_probe(&st->spi->dev, -EINVAL, 1071 1071 + "Invalid analog input pin number. %d\n", 1072 1072 + pin); 1073 1073 + 1074 1074 + return ad4170_validate_analog_input(st, pin); 1075 1075 + } 1076 1076 + 1077 1077 + /* 1078 1078 + * Verifies whether the channel input configuration is valid by checking the 1079 1079 + * input numbers. 1080 1080 + * Returns 0 on valid channel input configuration. -EINVAL otherwise. 1081 1081 + */ 1082 1082 + static int ad4170_validate_channel(struct ad4170_state *st, 1083 1083 + struct iio_chan_spec const *chan) 1084 1084 + { 1085 1085 + int ret; 1086 1086 + 1087 1087 + ret = ad4170_validate_channel_input(st, chan->channel, false); 1088 1088 + if (ret) 1089 1089 + return ret; 1090 1090 + 1091 1091 + return ad4170_validate_channel_input(st, chan->channel2, 1092 1092 + !chan->differential); 1093 1093 + } 1094 1094 + 1095 1095 + /* 1096 1096 + * Verifies whether the channel configuration is valid by checking the provided 1097 1097 + * input type, polarity, and voltage references result in a sane input range. 1098 1098 + * Returns negative error code on failure. 1099 1099 + */ 1100 1100 + static int ad4170_get_input_range(struct ad4170_state *st, 1101 1101 + struct iio_chan_spec const *chan, 1102 1102 + unsigned int ch_reg, unsigned int ref_sel) 1103 1103 + { 1104 1104 + bool bipolar = chan->scan_type.sign == 's'; 1105 1105 + struct device *dev = &st->spi->dev; 1106 1106 + int refp, refn, ain_voltage, ret; 1107 1107 + 1108 1108 + switch (ref_sel) { 1109 1109 + case AD4170_REF_REFIN1: 1110 1110 + if (st->vrefs_uv[AD4170_REFIN1P_SUP] == -ENODEV || 1111 1111 + st->vrefs_uv[AD4170_REFIN1N_SUP] == -ENODEV) 1112 1112 + return dev_err_probe(dev, -ENODEV, 1113 1113 + "REFIN± selected but not provided\n"); 1114 1114 + 1115 1115 + refp = st->vrefs_uv[AD4170_REFIN1P_SUP]; 1116 1116 + refn = st->vrefs_uv[AD4170_REFIN1N_SUP]; 1117 1117 + break; 1118 1118 + case AD4170_REF_REFIN2: 1119 1119 + if (st->vrefs_uv[AD4170_REFIN2P_SUP] == -ENODEV || 1120 1120 + st->vrefs_uv[AD4170_REFIN2N_SUP] == -ENODEV) 1121 1121 + return dev_err_probe(dev, -ENODEV, 1122 1122 + "REFIN2± selected but not provided\n"); 1123 1123 + 1124 1124 + refp = st->vrefs_uv[AD4170_REFIN2P_SUP]; 1125 1125 + refn = st->vrefs_uv[AD4170_REFIN2N_SUP]; 1126 1126 + break; 1127 1127 + case AD4170_REF_AVDD: 1128 1128 + refp = st->vrefs_uv[AD4170_AVDD_SUP]; 1129 1129 + refn = st->vrefs_uv[AD4170_AVSS_SUP]; 1130 1130 + break; 1131 1131 + case AD4170_REF_REFOUT: 1132 1132 + /* REFOUT is 2.5 V relative to AVSS */ 1133 1133 + refp = st->vrefs_uv[AD4170_AVSS_SUP] + AD4170_INT_REF_2_5V; 1134 1134 + refn = st->vrefs_uv[AD4170_AVSS_SUP]; 1135 1135 + break; 1136 1136 + default: 1137 1137 + return -EINVAL; 1138 1138 + } 1139 1139 + 1140 1140 + /* 1141 1141 + * Find out the analog input range from the channel type, polarity, and 1142 1142 + * voltage reference selection. 1143 1143 + * AD4170 channels are either differential or pseudo-differential. 1144 1144 + * Diff input voltage range: −VREF/gain to +VREF/gain (datasheet page 6) 1145 1145 + * Pseudo-diff input voltage range: 0 to VREF/gain (datasheet page 6) 1146 1146 + */ 1147 1147 + if (chan->differential) { 1148 1148 + if (!bipolar) 1149 1149 + return dev_err_probe(dev, -EINVAL, 1150 1150 + "Channel %u differential unipolar\n", 1151 1151 + ch_reg); 1152 1152 + 1153 1153 + /* 1154 1154 + * Differential bipolar channel. 1155 1155 + * avss-supply is never above 0V. 1156 1156 + * Assuming refin1n-supply not above 0V. 1157 1157 + * Assuming refin2n-supply not above 0V. 1158 1158 + */ 1159 1159 + return refp + abs(refn); 1160 1160 + } 1161 1161 + /* 1162 1162 + * Some configurations can lead to invalid setups. 1163 1163 + * For example, if AVSS = -2.5V, REF_SELECT set to REFOUT (REFOUT/AVSS), 1164 1164 + * and pseudo-diff channel configuration set, then the input range 1165 1165 + * should go from 0V to +VREF (single-ended - datasheet pg 10), but 1166 1166 + * REFOUT/AVSS range would be -2.5V to 0V. 1167 1167 + * Check the positive reference is higher than 0V for pseudo-diff 1168 1168 + * channels. 1169 1169 + * Note that at this point in the code, refp can only be >= 0 since all 1170 1170 + * error codes from reading the regulator voltage have been checked 1171 1171 + * either at ad4170_regulator_setup() or above in this function. 1172 1172 + */ 1173 1173 + if (refp == 0) 1174 1174 + return dev_err_probe(dev, -EINVAL, 1175 1175 + "REF+ == GND for pseudo-diff chan %u\n", 1176 1176 + ch_reg); 1177 1177 + 1178 1178 + if (bipolar) 1179 1179 + return refp; 1180 1180 + 1181 1181 + /* 1182 1182 + * Pseudo-differential unipolar channel. 1183 1183 + * Input expected to swing from IN- to +VREF. 1184 1184 + */ 1185 1185 + ret = ad4170_get_ain_voltage_uv(st, chan->channel2, &ain_voltage); 1186 1186 + if (ret) 1187 1187 + return ret; 1188 1188 + 1189 1189 + if (refp - ain_voltage <= 0) 1190 1190 + return dev_err_probe(dev, -EINVAL, 1191 1191 + "Negative input >= REF+ for pseudo-diff chan %u\n", 1192 1192 + ch_reg); 1193 1193 + 1194 1194 + return refp - ain_voltage; 1195 1195 + } 1196 1196 + 1197 1197 + static int __ad4170_read_sample(struct iio_dev *indio_dev, 1198 1198 + struct iio_chan_spec const *chan, int *val) 1199 1199 + { 1200 1200 + struct ad4170_state *st = iio_priv(indio_dev); 1201 1201 + unsigned long settling_time_ms; 1202 1202 + int ret; 1203 1203 + 1204 1204 + reinit_completion(&st->completion); 1205 1205 + ret = regmap_update_bits(st->regmap, AD4170_ADC_CTRL_REG, 1206 1206 + AD4170_ADC_CTRL_MODE_MSK, 1207 1207 + FIELD_PREP(AD4170_ADC_CTRL_MODE_MSK, 1208 1208 + AD4170_ADC_CTRL_MODE_SINGLE)); 1209 1209 + if (ret) 1210 1210 + return ret; 1211 1211 + 1212 1212 + /* 1213 1213 + * When a channel is manually selected by the user, the ADC needs an 1214 1214 + * extra time to provide the first stable conversion. The ADC settling 1215 1215 + * time depends on the filter type, filter frequency, and ADC clock 1216 1216 + * frequency (see datasheet page 53). The maximum settling time among 1217 1217 + * all filter configurations is 6291164 / fCLK. Use that formula to wait 1218 1218 + * for sufficient time whatever the filter configuration may be. 1219 1219 + */ 1220 1220 + settling_time_ms = DIV_ROUND_UP(6291164 * MILLI, st->mclk_hz); 1221 1221 + ret = wait_for_completion_timeout(&st->completion, 1222 1222 + msecs_to_jiffies(settling_time_ms)); 1223 1223 + if (!ret) 1224 1224 + dev_dbg(&st->spi->dev, 1225 1225 + "No Data Ready signal. Reading after delay.\n"); 1226 1226 + 1227 1227 + ret = regmap_read(st->regmap, AD4170_DATA_24B_REG, val); 1228 1228 + if (ret) 1229 1229 + return ret; 1230 1230 + 1231 1231 + if (chan->scan_type.sign == 's') 1232 1232 + *val = sign_extend32(*val, chan->scan_type.realbits - 1); 1233 1233 + 1234 1234 + return 0; 1235 1235 + } 1236 1236 + 1237 1237 + static int ad4170_read_sample(struct iio_dev *indio_dev, 1238 1238 + struct iio_chan_spec const *chan, int *val) 1239 1239 + { 1240 1240 + struct ad4170_state *st = iio_priv(indio_dev); 1241 1241 + struct device *dev = &st->spi->dev; 1242 1242 + int ret, ret2; 1243 1243 + 1244 1244 + /* 1245 1245 + * The ADC sequences through all enabled channels. That can lead to 1246 1246 + * incorrect channel being sampled if a previous read would have left a 1247 1247 + * different channel enabled. Thus, always enable and disable the 1248 1248 + * channel on single-shot read. 1249 1249 + */ 1250 1250 + ret = ad4170_set_channel_enable(st, chan->address, true); 1251 1251 + if (ret) 1252 1252 + return ret; 1253 1253 + 1254 1254 + ret = __ad4170_read_sample(indio_dev, chan, val); 1255 1255 + if (ret) { 1256 1256 + dev_err(dev, "failed to read sample: %d\n", ret); 1257 1257 + 1258 1258 + ret2 = ad4170_set_channel_enable(st, chan->address, false); 1259 1259 + if (ret2) 1260 1260 + dev_err(dev, "failed to disable channel: %d\n", ret2); 1261 1261 + 1262 1262 + return ret; 1263 1263 + } 1264 1264 + 1265 1265 + ret = ad4170_set_channel_enable(st, chan->address, false); 1266 1266 + if (ret) 1267 1267 + return ret; 1268 1268 + 1269 1269 + return IIO_VAL_INT; 1270 1270 + } 1271 1271 + 1272 1272 + static int ad4170_read_raw(struct iio_dev *indio_dev, 1273 1273 + struct iio_chan_spec const *chan, 1274 1274 + int *val, int *val2, long info) 1275 1275 + { 1276 1276 + struct ad4170_state *st = iio_priv(indio_dev); 1277 1277 + struct ad4170_chan_info *chan_info = &st->chan_infos[chan->address]; 1278 1278 + struct ad4170_setup *setup = &chan_info->setup; 1279 1279 + enum ad4170_filter_type f_type; 1280 1280 + unsigned int pga, fs_idx; 1281 1281 + int ret; 1282 1282 + 1283 1283 + guard(mutex)(&st->lock); 1284 1284 + switch (info) { 1285 1285 + case IIO_CHAN_INFO_RAW: 1286 1286 + if (!iio_device_claim_direct(indio_dev)) 1287 1287 + return -EBUSY; 1288 1288 + 1289 1289 + ret = ad4170_read_sample(indio_dev, chan, val); 1290 1290 + iio_device_release_direct(indio_dev); 1291 1291 + return ret; 1292 1292 + case IIO_CHAN_INFO_SCALE: 1293 1293 + pga = FIELD_GET(AD4170_AFE_PGA_GAIN_MSK, setup->afe); 1294 1294 + switch (chan->type) { 1295 1295 + case IIO_VOLTAGE: 1296 1296 + *val = chan_info->scale_tbl[pga][0]; 1297 1297 + *val2 = chan_info->scale_tbl[pga][1]; 1298 1298 + return IIO_VAL_INT_PLUS_NANO; 1299 1299 + case IIO_TEMP: 1300 1300 + /* 1301 1301 + * The scale_tbl converts output codes to mV units so 1302 1302 + * multiply by MILLI to make the factor convert to µV. 1303 1303 + * Then, apply the temperature sensor change sensitivity 1304 1304 + * of 477 μV/K. Finally, multiply the result by MILLI 1305 1305 + * again to comply with milli degrees Celsius IIO ABI. 1306 1306 + */ 1307 1307 + *val = 0; 1308 1308 + *val2 = DIV_ROUND_CLOSEST(chan_info->scale_tbl[pga][1] * MILLI, 477) * 1309 1309 + MILLI; 1310 1310 + return IIO_VAL_INT_PLUS_NANO; 1311 1311 + default: 1312 1312 + return -EINVAL; 1313 1313 + } 1314 1314 + case IIO_CHAN_INFO_OFFSET: 1315 1315 + pga = FIELD_GET(AD4170_AFE_PGA_GAIN_MSK, setup->afe); 1316 1316 + *val = chan_info->offset_tbl[pga]; 1317 1317 + return IIO_VAL_INT; 1318 1318 + case IIO_CHAN_INFO_SAMP_FREQ: 1319 1319 + f_type = __ad4170_get_filter_type(setup->filter); 1320 1320 + switch (f_type) { 1321 1321 + case AD4170_SINC5_AVG: 1322 1322 + case AD4170_SINC3: 1323 1323 + fs_idx = find_closest(setup->filter_fs, 1324 1324 + ad4170_sinc3_filt_fs_tbl, 1325 1325 + ARRAY_SIZE(ad4170_sinc3_filt_fs_tbl)); 1326 1326 + *val = st->sps_tbl[f_type][fs_idx][0]; 1327 1327 + *val2 = st->sps_tbl[f_type][fs_idx][1]; 1328 1328 + return IIO_VAL_INT_PLUS_MICRO; 1329 1329 + case AD4170_SINC5: 1330 1330 + fs_idx = find_closest(setup->filter_fs, 1331 1331 + ad4170_sinc5_filt_fs_tbl, 1332 1332 + ARRAY_SIZE(ad4170_sinc5_filt_fs_tbl)); 1333 1333 + *val = st->sps_tbl[f_type][fs_idx][0]; 1334 1334 + *val2 = st->sps_tbl[f_type][fs_idx][1]; 1335 1335 + return IIO_VAL_INT_PLUS_MICRO; 1336 1336 + default: 1337 1337 + return -EINVAL; 1338 1338 + } 1339 1339 + case IIO_CHAN_INFO_CALIBBIAS: 1340 1340 + *val = setup->offset; 1341 1341 + return IIO_VAL_INT; 1342 1342 + case IIO_CHAN_INFO_CALIBSCALE: 1343 1343 + *val = setup->gain; 1344 1344 + return IIO_VAL_INT; 1345 1345 + default: 1346 1346 + return -EINVAL; 1347 1347 + } 1348 1348 + } 1349 1349 + 1350 1350 + static int ad4170_fill_scale_tbl(struct iio_dev *indio_dev, 1351 1351 + struct iio_chan_spec const *chan) 1352 1352 + { 1353 1353 + struct ad4170_state *st = iio_priv(indio_dev); 1354 1354 + struct ad4170_chan_info *chan_info = &st->chan_infos[chan->address]; 1355 1355 + struct device *dev = &st->spi->dev; 1356 1356 + int bipolar = chan->scan_type.sign == 's' ? 1 : 0; 1357 1357 + int precision_bits = chan->scan_type.realbits; 1358 1358 + int pga, ainm_voltage, ret; 1359 1359 + unsigned long long offset; 1360 1360 + 1361 1361 + ainm_voltage = 0; 1362 1362 + ret = ad4170_get_ain_voltage_uv(st, chan->channel2, &ainm_voltage); 1363 1363 + if (ret < 0) 1364 1364 + return dev_err_probe(dev, ret, "Failed to fill scale table\n"); 1365 1365 + 1366 1366 + for (pga = 0; pga < AD4170_NUM_PGA_OPTIONS; pga++) { 1367 1367 + u64 nv; 1368 1368 + unsigned int lshift, rshift; 1369 1369 + 1370 1370 + /* 1371 1371 + * The PGA options are numbered from 0 to 9, with option 0 being 1372 1372 + * a gain of 2^0 (no actual gain), and 7 meaning a gain of 2^7. 1373 1373 + * Option 8, though, sets a gain of 0.5, so the input signal can 1374 1374 + * be attenuated by 2 rather than amplified. Option 9, allows 1375 1375 + * the signal to bypass the PGA circuitry (no gain). 1376 1376 + * 1377 1377 + * The scale factor to get ADC output codes to values in mV 1378 1378 + * units is given by: 1379 1379 + * _scale = (input_range / gain) / 2^precision 1380 1380 + * AD4170 gain is a power of 2 so the above can be written as 1381 1381 + * _scale = input_range / 2^(precision + gain) 1382 1382 + * Keep the input range in µV to avoid truncating the less 1383 1383 + * significant bits when right shifting it so to preserve scale 1384 1384 + * precision. 1385 1385 + */ 1386 1386 + nv = (u64)chan_info->input_range_uv * NANO; 1387 1387 + lshift = !!(pga & BIT(3)); /* handle PGA options 8 and 9 */ 1388 1388 + rshift = precision_bits - bipolar + (pga & GENMASK(2, 0)) - lshift; 1389 1389 + chan_info->scale_tbl[pga][0] = 0; 1390 1390 + chan_info->scale_tbl[pga][1] = div_u64(nv >> rshift, MILLI); 1391 1391 + 1392 1392 + /* 1393 1393 + * If the negative input is not at GND, the conversion result 1394 1394 + * (which is relative to IN-) will be offset by the level at IN-. 1395 1395 + * Use the scale factor the other way around to go from a known 1396 1396 + * voltage to the corresponding ADC output code. 1397 1397 + * With that, we are able to get to what would be the output 1398 1398 + * code for the voltage at the negative input. 1399 1399 + * If the negative input is not fixed, there is no offset. 1400 1400 + */ 1401 1401 + offset = ((unsigned long long)abs(ainm_voltage)) * MICRO; 1402 1402 + offset = DIV_ROUND_CLOSEST_ULL(offset, chan_info->scale_tbl[pga][1]); 1403 1403 + 1404 1404 + /* 1405 1405 + * After divided by the scale, offset will always fit into 31 1406 1406 + * bits. For _raw + _offset to be relative to GND, the value 1407 1407 + * provided as _offset is of opposite sign than the real offset. 1408 1408 + */ 1409 1409 + if (ainm_voltage > 0) 1410 1410 + chan_info->offset_tbl[pga] = -(int)(offset); 1411 1411 + else 1412 1412 + chan_info->offset_tbl[pga] = (int)(offset); 1413 1413 + } 1414 1414 + return 0; 1415 1415 + } 1416 1416 + 1417 1417 + static int ad4170_read_avail(struct iio_dev *indio_dev, 1418 1418 + struct iio_chan_spec const *chan, 1419 1419 + const int **vals, int *type, int *length, 1420 1420 + long info) 1421 1421 + { 1422 1422 + struct ad4170_state *st = iio_priv(indio_dev); 1423 1423 + struct ad4170_chan_info *chan_info = &st->chan_infos[chan->address]; 1424 1424 + enum ad4170_filter_type f_type; 1425 1425 + 1426 1426 + switch (info) { 1427 1427 + case IIO_CHAN_INFO_SCALE: 1428 1428 + *vals = (int *)chan_info->scale_tbl; 1429 1429 + *length = ARRAY_SIZE(chan_info->scale_tbl) * 2; 1430 1430 + *type = IIO_VAL_INT_PLUS_NANO; 1431 1431 + return IIO_AVAIL_LIST; 1432 1432 + case IIO_CHAN_INFO_SAMP_FREQ: 1433 1433 + *type = IIO_VAL_INT_PLUS_MICRO; 1434 1434 + f_type = ad4170_get_filter_type(indio_dev, chan); 1435 1435 + switch (f_type) { 1436 1436 + case AD4170_SINC5_AVG: 1437 1437 + case AD4170_SINC3: 1438 1438 + /* Read sps_tbl here to ensure in bounds array access */ 1439 1439 + *vals = (int *)st->sps_tbl[f_type]; 1440 1440 + *length = ARRAY_SIZE(ad4170_sinc3_filt_fs_tbl) * 2; 1441 1441 + return IIO_AVAIL_LIST; 1442 1442 + case AD4170_SINC5: 1443 1443 + /* Read sps_tbl here to ensure in bounds array access */ 1444 1444 + *vals = (int *)st->sps_tbl[f_type]; 1445 1445 + *length = ARRAY_SIZE(ad4170_sinc5_filt_fs_tbl) * 2; 1446 1446 + return IIO_AVAIL_LIST; 1447 1447 + default: 1448 1448 + return -EINVAL; 1449 1449 + } 1450 1450 + default: 1451 1451 + return -EINVAL; 1452 1452 + } 1453 1453 + } 1454 1454 + 1455 1455 + static int ad4170_set_pga(struct ad4170_state *st, 1456 1456 + struct iio_chan_spec const *chan, int val, int val2) 1457 1457 + { 1458 1458 + struct ad4170_chan_info *chan_info = &st->chan_infos[chan->address]; 1459 1459 + struct ad4170_setup *setup = &chan_info->setup; 1460 1460 + unsigned int pga; 1461 1461 + 1462 1462 + for (pga = 0; pga < AD4170_NUM_PGA_OPTIONS; pga++) { 1463 1463 + if (val == chan_info->scale_tbl[pga][0] && 1464 1464 + val2 == chan_info->scale_tbl[pga][1]) 1465 1465 + break; 1466 1466 + } 1467 1467 + 1468 1468 + if (pga == AD4170_NUM_PGA_OPTIONS) 1469 1469 + return -EINVAL; 1470 1470 + 1471 1471 + guard(mutex)(&st->lock); 1472 1472 + setup->afe &= ~AD4170_AFE_PGA_GAIN_MSK; 1473 1473 + setup->afe |= FIELD_PREP(AD4170_AFE_PGA_GAIN_MSK, pga); 1474 1474 + 1475 1475 + return ad4170_write_channel_setup(st, chan->address, false); 1476 1476 + } 1477 1477 + 1478 1478 + static int ad4170_set_channel_freq(struct ad4170_state *st, 1479 1479 + struct iio_chan_spec const *chan, int val, 1480 1480 + int val2) 1481 1481 + { 1482 1482 + struct ad4170_chan_info *chan_info = &st->chan_infos[chan->address]; 1483 1483 + struct ad4170_setup *setup = &chan_info->setup; 1484 1484 + enum ad4170_filter_type f_type = __ad4170_get_filter_type(setup->filter); 1485 1485 + unsigned int filt_fs_tbl_size, i; 1486 1486 + 1487 1487 + switch (f_type) { 1488 1488 + case AD4170_SINC5_AVG: 1489 1489 + case AD4170_SINC3: 1490 1490 + filt_fs_tbl_size = ARRAY_SIZE(ad4170_sinc3_filt_fs_tbl); 1491 1491 + break; 1492 1492 + case AD4170_SINC5: 1493 1493 + filt_fs_tbl_size = ARRAY_SIZE(ad4170_sinc5_filt_fs_tbl); 1494 1494 + break; 1495 1495 + } 1496 1496 + 1497 1497 + for (i = 0; i < filt_fs_tbl_size; i++) { 1498 1498 + if (st->sps_tbl[f_type][i][0] == val && 1499 1499 + st->sps_tbl[f_type][i][1] == val2) 1500 1500 + break; 1501 1501 + } 1502 1502 + if (i == filt_fs_tbl_size) 1503 1503 + return -EINVAL; 1504 1504 + 1505 1505 + guard(mutex)(&st->lock); 1506 1506 + if (f_type == AD4170_SINC5) 1507 1507 + setup->filter_fs = ad4170_sinc5_filt_fs_tbl[i]; 1508 1508 + else 1509 1509 + setup->filter_fs = ad4170_sinc3_filt_fs_tbl[i]; 1510 1510 + 1511 1511 + return ad4170_write_channel_setup(st, chan->address, false); 1512 1512 + } 1513 1513 + 1514 1514 + static int ad4170_set_calib_offset(struct ad4170_state *st, 1515 1515 + struct iio_chan_spec const *chan, int val) 1516 1516 + { 1517 1517 + struct ad4170_chan_info *chan_info = &st->chan_infos[chan->address]; 1518 1518 + struct ad4170_setup *setup = &chan_info->setup; 1519 1519 + 1520 1520 + guard(mutex)(&st->lock); 1521 1521 + setup->offset = val; 1522 1522 + 1523 1523 + return ad4170_write_channel_setup(st, chan->address, false); 1524 1524 + } 1525 1525 + 1526 1526 + static int ad4170_set_calib_gain(struct ad4170_state *st, 1527 1527 + struct iio_chan_spec const *chan, int val) 1528 1528 + { 1529 1529 + struct ad4170_chan_info *chan_info = &st->chan_infos[chan->address]; 1530 1530 + struct ad4170_setup *setup = &chan_info->setup; 1531 1531 + 1532 1532 + guard(mutex)(&st->lock); 1533 1533 + setup->gain = val; 1534 1534 + 1535 1535 + return ad4170_write_channel_setup(st, chan->address, false); 1536 1536 + } 1537 1537 + 1538 1538 + static int __ad4170_write_raw(struct iio_dev *indio_dev, 1539 1539 + struct iio_chan_spec const *chan, int val, 1540 1540 + int val2, long info) 1541 1541 + { 1542 1542 + struct ad4170_state *st = iio_priv(indio_dev); 1543 1543 + 1544 1544 + switch (info) { 1545 1545 + case IIO_CHAN_INFO_SCALE: 1546 1546 + return ad4170_set_pga(st, chan, val, val2); 1547 1547 + case IIO_CHAN_INFO_SAMP_FREQ: 1548 1548 + return ad4170_set_channel_freq(st, chan, val, val2); 1549 1549 + case IIO_CHAN_INFO_CALIBBIAS: 1550 1550 + return ad4170_set_calib_offset(st, chan, val); 1551 1551 + case IIO_CHAN_INFO_CALIBSCALE: 1552 1552 + return ad4170_set_calib_gain(st, chan, val); 1553 1553 + default: 1554 1554 + return -EINVAL; 1555 1555 + } 1556 1556 + } 1557 1557 + 1558 1558 + static int ad4170_write_raw(struct iio_dev *indio_dev, 1559 1559 + struct iio_chan_spec const *chan, int val, 1560 1560 + int val2, long info) 1561 1561 + { 1562 1562 + int ret; 1563 1563 + 1564 1564 + if (!iio_device_claim_direct(indio_dev)) 1565 1565 + return -EBUSY; 1566 1566 + 1567 1567 + ret = __ad4170_write_raw(indio_dev, chan, val, val2, info); 1568 1568 + iio_device_release_direct(indio_dev); 1569 1569 + return ret; 1570 1570 + } 1571 1571 + 1572 1572 + static int ad4170_write_raw_get_fmt(struct iio_dev *indio_dev, 1573 1573 + struct iio_chan_spec const *chan, 1574 1574 + long info) 1575 1575 + { 1576 1576 + switch (info) { 1577 1577 + case IIO_CHAN_INFO_SCALE: 1578 1578 + return IIO_VAL_INT_PLUS_NANO; 1579 1579 + case IIO_CHAN_INFO_SAMP_FREQ: 1580 1580 + return IIO_VAL_INT_PLUS_MICRO; 1581 1581 + case IIO_CHAN_INFO_CALIBBIAS: 1582 1582 + case IIO_CHAN_INFO_CALIBSCALE: 1583 1583 + return IIO_VAL_INT; 1584 1584 + default: 1585 1585 + return -EINVAL; 1586 1586 + } 1587 1587 + } 1588 1588 + 1589 1589 + static int ad4170_update_scan_mode(struct iio_dev *indio_dev, 1590 1590 + const unsigned long *active_scan_mask) 1591 1591 + { 1592 1592 + struct ad4170_state *st = iio_priv(indio_dev); 1593 1593 + unsigned int chan_index; 1594 1594 + int ret; 1595 1595 + 1596 1596 + iio_for_each_active_channel(indio_dev, chan_index) { 1597 1597 + ret = ad4170_set_channel_enable(st, chan_index, true); 1598 1598 + if (ret) 1599 1599 + return ret; 1600 1600 + } 1601 1601 + return 0; 1602 1602 + } 1603 1603 + 1604 1604 + static const struct iio_info ad4170_info = { 1605 1605 + .read_raw = ad4170_read_raw, 1606 1606 + .read_avail = ad4170_read_avail, 1607 1607 + .write_raw = ad4170_write_raw, 1608 1608 + .write_raw_get_fmt = ad4170_write_raw_get_fmt, 1609 1609 + .update_scan_mode = ad4170_update_scan_mode, 1610 1610 + .debugfs_reg_access = ad4170_debugfs_reg_access, 1611 1611 + }; 1612 1612 + 1613 1613 + static int ad4170_soft_reset(struct ad4170_state *st) 1614 1614 + { 1615 1615 + int ret; 1616 1616 + 1617 1617 + ret = regmap_write(st->regmap, AD4170_CONFIG_A_REG, 1618 1618 + AD4170_SW_RESET_MSK); 1619 1619 + if (ret) 1620 1620 + return ret; 1621 1621 + 1622 1622 + /* AD4170-4 requires 1 ms between reset and any register access. */ 1623 1623 + fsleep(1 * USEC_PER_MSEC); 1624 1624 + 1625 1625 + return 0; 1626 1626 + } 1627 1627 + 1628 1628 + static int ad4170_gpio_get(struct gpio_chip *gc, unsigned int offset) 1629 1629 + { 1630 1630 + struct iio_dev *indio_dev = gpiochip_get_data(gc); 1631 1631 + struct ad4170_state *st = iio_priv(indio_dev); 1632 1632 + unsigned int val; 1633 1633 + int ret; 1634 1634 + 1635 1635 + if (!iio_device_claim_direct(indio_dev)) 1636 1636 + return -EBUSY; 1637 1637 + 1638 1638 + ret = regmap_read(st->regmap, AD4170_GPIO_MODE_REG, &val); 1639 1639 + if (ret) 1640 1640 + goto err_release; 1641 1641 + 1642 1642 + /* 1643 1643 + * If the GPIO is configured as an input, read the current value from 1644 1644 + * AD4170_GPIO_INPUT_REG. Otherwise, read the input value from 1645 1645 + * AD4170_GPIO_OUTPUT_REG. 1646 1646 + */ 1647 1647 + if (val & BIT(offset * 2)) 1648 1648 + ret = regmap_read(st->regmap, AD4170_GPIO_INPUT_REG, &val); 1649 1649 + else 1650 1650 + ret = regmap_read(st->regmap, AD4170_GPIO_OUTPUT_REG, &val); 1651 1651 + if (ret) 1652 1652 + goto err_release; 1653 1653 + 1654 1654 + ret = !!(val & BIT(offset)); 1655 1655 + err_release: 1656 1656 + iio_device_release_direct(indio_dev); 1657 1657 + 1658 1658 + return ret; 1659 1659 + } 1660 1660 + 1661 1661 + static int ad4170_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) 1662 1662 + { 1663 1663 + struct iio_dev *indio_dev = gpiochip_get_data(gc); 1664 1664 + struct ad4170_state *st = iio_priv(indio_dev); 1665 1665 + int ret; 1666 1666 + 1667 1667 + if (!iio_device_claim_direct(indio_dev)) 1668 1668 + return -EBUSY; 1669 1669 + 1670 1670 + ret = regmap_assign_bits(st->regmap, AD4170_GPIO_OUTPUT_REG, 1671 1671 + BIT(offset), !!value); 1672 1672 + 1673 1673 + iio_device_release_direct(indio_dev); 1674 1674 + return ret; 1675 1675 + } 1676 1676 + 1677 1677 + static int ad4170_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 1678 1678 + { 1679 1679 + struct iio_dev *indio_dev = gpiochip_get_data(gc); 1680 1680 + struct ad4170_state *st = iio_priv(indio_dev); 1681 1681 + unsigned int val; 1682 1682 + int ret; 1683 1683 + 1684 1684 + if (!iio_device_claim_direct(indio_dev)) 1685 1685 + return -EBUSY; 1686 1686 + 1687 1687 + ret = regmap_read(st->regmap, AD4170_GPIO_MODE_REG, &val); 1688 1688 + if (ret) 1689 1689 + goto err_release; 1690 1690 + 1691 1691 + if (val & BIT(offset * 2 + 1)) 1692 1692 + ret = GPIO_LINE_DIRECTION_OUT; 1693 1693 + else 1694 1694 + ret = GPIO_LINE_DIRECTION_IN; 1695 1695 + 1696 1696 + err_release: 1697 1697 + iio_device_release_direct(indio_dev); 1698 1698 + 1699 1699 + return ret; 1700 1700 + } 1701 1701 + 1702 1702 + static int ad4170_gpio_direction_input(struct gpio_chip *gc, unsigned int offset) 1703 1703 + { 1704 1704 + struct iio_dev *indio_dev = gpiochip_get_data(gc); 1705 1705 + struct ad4170_state *st = iio_priv(indio_dev); 1706 1706 + unsigned long gpio_mask; 1707 1707 + int ret; 1708 1708 + 1709 1709 + if (!iio_device_claim_direct(indio_dev)) 1710 1710 + return -EBUSY; 1711 1711 + 1712 1712 + switch (offset) { 1713 1713 + case 0: 1714 1714 + gpio_mask = AD4170_GPIO_MODE_GPIO0_MSK; 1715 1715 + break; 1716 1716 + case 1: 1717 1717 + gpio_mask = AD4170_GPIO_MODE_GPIO1_MSK; 1718 1718 + break; 1719 1719 + case 2: 1720 1720 + gpio_mask = AD4170_GPIO_MODE_GPIO2_MSK; 1721 1721 + break; 1722 1722 + case 3: 1723 1723 + gpio_mask = AD4170_GPIO_MODE_GPIO3_MSK; 1724 1724 + break; 1725 1725 + default: 1726 1726 + ret = -EINVAL; 1727 1727 + goto err_release; 1728 1728 + } 1729 1729 + ret = regmap_update_bits(st->regmap, AD4170_GPIO_MODE_REG, gpio_mask, 1730 1730 + AD4170_GPIO_MODE_GPIO_INPUT << (2 * offset)); 1731 1731 + 1732 1732 + err_release: 1733 1733 + iio_device_release_direct(indio_dev); 1734 1734 + 1735 1735 + return ret; 1736 1736 + } 1737 1737 + 1738 1738 + static int ad4170_gpio_direction_output(struct gpio_chip *gc, 1739 1739 + unsigned int offset, int value) 1740 1740 + { 1741 1741 + struct iio_dev *indio_dev = gpiochip_get_data(gc); 1742 1742 + struct ad4170_state *st = iio_priv(indio_dev); 1743 1743 + unsigned long gpio_mask; 1744 1744 + int ret; 1745 1745 + 1746 1746 + ret = ad4170_gpio_set(gc, offset, value); 1747 1747 + if (ret) 1748 1748 + return ret; 1749 1749 + 1750 1750 + if (!iio_device_claim_direct(indio_dev)) 1751 1751 + return -EBUSY; 1752 1752 + 1753 1753 + switch (offset) { 1754 1754 + case 0: 1755 1755 + gpio_mask = AD4170_GPIO_MODE_GPIO0_MSK; 1756 1756 + break; 1757 1757 + case 1: 1758 1758 + gpio_mask = AD4170_GPIO_MODE_GPIO1_MSK; 1759 1759 + break; 1760 1760 + case 2: 1761 1761 + gpio_mask = AD4170_GPIO_MODE_GPIO2_MSK; 1762 1762 + break; 1763 1763 + case 3: 1764 1764 + gpio_mask = AD4170_GPIO_MODE_GPIO3_MSK; 1765 1765 + break; 1766 1766 + default: 1767 1767 + ret = -EINVAL; 1768 1768 + goto err_release; 1769 1769 + } 1770 1770 + ret = regmap_update_bits(st->regmap, AD4170_GPIO_MODE_REG, gpio_mask, 1771 1771 + AD4170_GPIO_MODE_GPIO_OUTPUT << (2 * offset)); 1772 1772 + 1773 1773 + err_release: 1774 1774 + iio_device_release_direct(indio_dev); 1775 1775 + 1776 1776 + return ret; 1777 1777 + } 1778 1778 + 1779 1779 + static int ad4170_gpio_init_valid_mask(struct gpio_chip *gc, 1780 1780 + unsigned long *valid_mask, 1781 1781 + unsigned int ngpios) 1782 1782 + { 1783 1783 + struct ad4170_state *st = gpiochip_get_data(gc); 1784 1784 + unsigned int i; 1785 1785 + 1786 1786 + /* Only expose GPIOs that were not assigned any other function. */ 1787 1787 + for (i = 0; i < ngpios; i++) { 1788 1788 + bool valid = st->gpio_fn[i] == AD4170_GPIO_UNASSIGNED; 1789 1789 + 1790 1790 + __assign_bit(i, valid_mask, valid); 1791 1791 + } 1792 1792 + 1793 1793 + return 0; 1794 1794 + } 1795 1795 + 1796 1796 + static int ad4170_gpio_init(struct iio_dev *indio_dev) 1797 1797 + { 1798 1798 + struct ad4170_state *st = iio_priv(indio_dev); 1799 1799 + 1800 1800 + st->gpiochip.label = "ad4170_gpios"; 1801 1801 + st->gpiochip.base = -1; 1802 1802 + st->gpiochip.ngpio = AD4170_NUM_GPIO_PINS; 1803 1803 + st->gpiochip.parent = &st->spi->dev; 1804 1804 + st->gpiochip.can_sleep = true; 1805 1805 + st->gpiochip.init_valid_mask = ad4170_gpio_init_valid_mask; 1806 1806 + st->gpiochip.get_direction = ad4170_gpio_get_direction; 1807 1807 + st->gpiochip.direction_input = ad4170_gpio_direction_input; 1808 1808 + st->gpiochip.direction_output = ad4170_gpio_direction_output; 1809 1809 + st->gpiochip.get = ad4170_gpio_get; 1810 1810 + st->gpiochip.set_rv = ad4170_gpio_set; 1811 1811 + st->gpiochip.owner = THIS_MODULE; 1812 1812 + 1813 1813 + return devm_gpiochip_add_data(&st->spi->dev, &st->gpiochip, indio_dev); 1814 1814 + } 1815 1815 + 1816 1816 + static int ad4170_validate_excitation_pin(struct ad4170_state *st, u32 pin) 1817 1817 + { 1818 1818 + struct device *dev = &st->spi->dev; 1819 1819 + unsigned int i; 1820 1820 + 1821 1821 + /* Check the pin number is valid */ 1822 1822 + for (i = 0; i < ARRAY_SIZE(ad4170_iout_pin_tbl); i++) 1823 1823 + if (ad4170_iout_pin_tbl[i] == pin) 1824 1824 + break; 1825 1825 + 1826 1826 + if (i == ARRAY_SIZE(ad4170_iout_pin_tbl)) 1827 1827 + return dev_err_probe(dev, -EINVAL, 1828 1828 + "Invalid excitation pin: %u\n", 1829 1829 + pin); 1830 1830 + 1831 1831 + /* Check the pin is available */ 1832 1832 + if (pin <= AD4170_MAX_ANALOG_PINS) { 1833 1833 + if (st->pins_fn[pin] != AD4170_PIN_UNASSIGNED) 1834 1834 + return dev_err_probe(dev, -EINVAL, 1835 1835 + "Pin %u already used with fn %u\n", 1836 1836 + pin, st->pins_fn[pin]); 1837 1837 + 1838 1838 + st->pins_fn[pin] |= AD4170_PIN_CURRENT_OUT; 1839 1839 + } else { 1840 1840 + unsigned int gpio = pin - AD4170_CURRENT_SRC_I_OUT_PIN_GPIO(0); 1841 1841 + 1842 1842 + if (st->gpio_fn[gpio] != AD4170_GPIO_UNASSIGNED) 1843 1843 + return dev_err_probe(dev, -EINVAL, 1844 1844 + "GPIO %u already used with fn %u\n", 1845 1845 + gpio, st->gpio_fn[gpio]); 1846 1846 + 1847 1847 + st->gpio_fn[gpio] |= AD4170_GPIO_AC_EXCITATION; 1848 1848 + } 1849 1849 + 1850 1850 + return 0; 1851 1851 + } 1852 1852 + 1853 1853 + static int ad4170_validate_excitation_pins(struct ad4170_state *st, 1854 1854 + u32 *exc_pins, int num_exc_pins) 1855 1855 + { 1856 1856 + unsigned int i; 1857 1857 + int ret; 1858 1858 + 1859 1859 + for (i = 0; i < num_exc_pins; i++) { 1860 1860 + ret = ad4170_validate_excitation_pin(st, exc_pins[i]); 1861 1861 + if (ret) 1862 1862 + return ret; 1863 1863 + } 1864 1864 + return 0; 1865 1865 + } 1866 1866 + 1867 1867 + static const char *const ad4170_i_out_pin_dt_props[] = { 1868 1868 + "adi,excitation-pin-0", 1869 1869 + "adi,excitation-pin-1", 1870 1870 + "adi,excitation-pin-2", 1871 1871 + "adi,excitation-pin-3", 1872 1872 + }; 1873 1873 + 1874 1874 + static const char *const ad4170_i_out_val_dt_props[] = { 1875 1875 + "adi,excitation-current-0-microamp", 1876 1876 + "adi,excitation-current-1-microamp", 1877 1877 + "adi,excitation-current-2-microamp", 1878 1878 + "adi,excitation-current-3-microamp", 1879 1879 + }; 1880 1880 + 1881 1881 + /* 1882 1882 + * Parses firmware data describing output current source setup. There are 4 1883 1883 + * excitation currents (IOUT0 to IOUT3) that can be configured independently. 1884 1884 + * Excitation currents are added if they are output on the same pin. 1885 1885 + */ 1886 1886 + static int ad4170_parse_exc_current(struct ad4170_state *st, 1887 1887 + struct fwnode_handle *child, 1888 1888 + unsigned int *exc_pins, 1889 1889 + unsigned int *exc_curs, 1890 1890 + unsigned int *num_exc_pins) 1891 1891 + { 1892 1892 + struct device *dev = &st->spi->dev; 1893 1893 + unsigned int num_pins, i, j; 1894 1894 + u32 pin, val; 1895 1895 + int ret; 1896 1896 + 1897 1897 + num_pins = 0; 1898 1898 + for (i = 0; i < AD4170_NUM_CURRENT_SRC; i++) { 1899 1899 + /* Parse excitation current output pin properties. */ 1900 1900 + pin = AD4170_CURRENT_SRC_I_OUT_PIN_AIN(0); 1901 1901 + ret = fwnode_property_read_u32(child, ad4170_i_out_pin_dt_props[i], 1902 1902 + &pin); 1903 1903 + if (ret) 1904 1904 + continue; 1905 1905 + 1906 1906 + exc_pins[num_pins] = pin; 1907 1907 + 1908 1908 + /* Parse excitation current value properties. */ 1909 1909 + val = ad4170_iout_current_ua_tbl[0]; 1910 1910 + fwnode_property_read_u32(child, 1911 1911 + ad4170_i_out_val_dt_props[i], &val); 1912 1912 + 1913 1913 + for (j = 0; j < ARRAY_SIZE(ad4170_iout_current_ua_tbl); j++) 1914 1914 + if (ad4170_iout_current_ua_tbl[j] == val) 1915 1915 + break; 1916 1916 + 1917 1917 + if (j == ARRAY_SIZE(ad4170_iout_current_ua_tbl)) 1918 1918 + return dev_err_probe(dev, -EINVAL, "Invalid %s: %uuA\n", 1919 1919 + ad4170_i_out_val_dt_props[i], val); 1920 1920 + 1921 1921 + exc_curs[num_pins] = j; 1922 1922 + num_pins++; 1923 1923 + } 1924 1924 + *num_exc_pins = num_pins; 1925 1925 + 1926 1926 + return 0; 1927 1927 + } 1928 1928 + 1929 1929 + static int ad4170_setup_current_src(struct ad4170_state *st, 1930 1930 + struct fwnode_handle *child, 1931 1931 + struct ad4170_setup *setup, u32 *exc_pins, 1932 1932 + unsigned int *exc_curs, int num_exc_pins, 1933 1933 + bool ac_excited) 1934 1934 + { 1935 1935 + unsigned int exc_cur_pair, i, j; 1936 1936 + int ret; 1937 1937 + 1938 1938 + for (i = 0; i < num_exc_pins; i++) { 1939 1939 + unsigned int exc_cur = exc_curs[i]; 1940 1940 + unsigned int pin = exc_pins[i]; 1941 1941 + unsigned int current_src = 0; 1942 1942 + 1943 1943 + for (j = 0; j < AD4170_NUM_CURRENT_SRC; j++) 1944 1944 + if (st->cur_src_pins[j] == AD4170_CURRENT_SRC_DISABLED) 1945 1945 + break; 1946 1946 + 1947 1947 + if (j == AD4170_NUM_CURRENT_SRC) 1948 1948 + return dev_err_probe(&st->spi->dev, -EINVAL, 1949 1949 + "Too many excitation current sources\n"); 1950 1950 + 1951 1951 + current_src |= FIELD_PREP(AD4170_CURRENT_SRC_I_OUT_PIN_MSK, pin); 1952 1952 + current_src |= FIELD_PREP(AD4170_CURRENT_SRC_I_OUT_VAL_MSK, exc_cur); 1953 1953 + st->cur_src_pins[j] = pin; 1954 1954 + ret = regmap_write(st->regmap, AD4170_CURRENT_SRC_REG(j), 1955 1955 + current_src); 1956 1956 + if (ret) 1957 1957 + return ret; 1958 1958 + } 1959 1959 + 1960 1960 + if (!ac_excited) 1961 1961 + return 0; 1962 1962 + 1963 1963 + if (num_exc_pins < 2) 1964 1964 + return dev_err_probe(&st->spi->dev, -EINVAL, 1965 1965 + "Current chopping requested but only one pin provided: %u\n", 1966 1966 + exc_pins[0]); 1967 1967 + 1968 1968 + /* 1969 1969 + * Two use cases to handle here: 1970 1970 + * - 2 pairs of excitation currents; 1971 1971 + * - 1 pair of excitation currents. 1972 1972 + */ 1973 1973 + if (num_exc_pins == 4) { 1974 1974 + for (i = 0; i < AD4170_NUM_CURRENT_SRC; i++) 1975 1975 + if (st->cur_src_pins[i] != exc_pins[i]) 1976 1976 + return dev_err_probe(&st->spi->dev, -EINVAL, 1977 1977 + "Unable to use 4 exc pins\n"); 1978 1978 + } else { 1979 1979 + /* 1980 1980 + * Excitation current chopping is configured in pairs. Current 1981 1981 + * sources IOUT0 and IOUT1 form pair 1, IOUT2 and IOUT3 make up 1982 1982 + * pair 2. So, if current chopping was requested, check if the 1983 1983 + * first end of the first pair of excitation currents is 1984 1984 + * available. Try the next pair if IOUT0 has already been 1985 1985 + * configured for another channel. 1986 1986 + */ 1987 1987 + i = st->cur_src_pins[0] == exc_pins[0] ? 0 : 2; 1988 1988 + 1989 1989 + if (st->cur_src_pins[i] != exc_pins[0] || 1990 1990 + st->cur_src_pins[i + 1] != exc_pins[1]) 1991 1991 + return dev_err_probe(&st->spi->dev, -EINVAL, 1992 1992 + "Failed to setup current chopping\n"); 1993 1993 + 1994 1994 + st->cur_src_pins[i] = exc_pins[0]; 1995 1995 + st->cur_src_pins[i + 1] = exc_pins[1]; 1996 1996 + 1997 1997 + if (i == 0) 1998 1998 + exc_cur_pair = AD4170_MISC_CHOP_IEXC_PAIR1; 1999 1999 + else 2000 2000 + exc_cur_pair = AD4170_MISC_CHOP_IEXC_PAIR2; 2001 2001 + } 2002 2002 + 2003 2003 + /* 2004 2004 + * Configure excitation current chopping. 2005 2005 + * Chop both pairs if using four excitation pins. 2006 2006 + */ 2007 2007 + setup->misc |= FIELD_PREP(AD4170_MISC_CHOP_IEXC_MSK, 2008 2008 + num_exc_pins == 2 ? 2009 2009 + exc_cur_pair : 2010 2010 + AD4170_MISC_CHOP_IEXC_BOTH); 2011 2011 + 2012 2012 + return 0; 2013 2013 + } 2014 2014 + 2015 2015 + static int ad4170_setup_bridge(struct ad4170_state *st, 2016 2016 + struct fwnode_handle *child, 2017 2017 + struct ad4170_setup *setup, u32 *exc_pins, 2018 2018 + unsigned int *exc_curs, int num_exc_pins, 2019 2019 + bool ac_excited) 2020 2020 + { 2021 2021 + unsigned long gpio_mask; 2022 2022 + unsigned int i; 2023 2023 + int ret; 2024 2024 + 2025 2025 + /* 2026 2026 + * If a specific current is provided through 2027 2027 + * adi,excitation-current-n-microamp, set excitation pins provided 2028 2028 + * through adi,excitation-pin-n to excite the bridge circuit. 2029 2029 + */ 2030 2030 + for (i = 0; i < num_exc_pins; i++) 2031 2031 + if (exc_curs[i] > 0) 2032 2032 + return ad4170_setup_current_src(st, child, setup, exc_pins, 2033 2033 + exc_curs, num_exc_pins, 2034 2034 + ac_excited); 2035 2035 + 2036 2036 + /* 2037 2037 + * Else, use predefined ACX1, ACX1 negated, ACX2, ACX2 negated signals 2038 2038 + * to AC excite the bridge. Those signals are output on GPIO2, GPIO0, 2039 2039 + * GPIO3, and GPIO1, respectively. If only two pins are specified for AC 2040 2040 + * excitation, use ACX1 and ACX2 (GPIO2 and GPIO3). 2041 2041 + * 2042 2042 + * Also, to avoid any short-circuit condition when more than one channel 2043 2043 + * is enabled, set GPIO2 and GPIO0 high, and set GPIO1 and GPIO3 low to 2044 2044 + * DC excite the bridge whenever a channel without AC excitation is 2045 2045 + * selected. That is needed because GPIO pins are controlled by the next 2046 2046 + * highest priority GPIO function when a channel doesn't enable AC 2047 2047 + * excitation. See datasheet Figure 113 Weigh Scale (AC Excitation) for 2048 2048 + * the reference circuit diagram. 2049 2049 + */ 2050 2050 + if (num_exc_pins == 2) { 2051 2051 + setup->misc |= FIELD_PREP(AD4170_MISC_CHOP_ADC_MSK, 0x3); 2052 2052 + 2053 2053 + gpio_mask = AD4170_GPIO_MODE_GPIO3_MSK | AD4170_GPIO_MODE_GPIO2_MSK; 2054 2054 + ret = regmap_update_bits(st->regmap, AD4170_GPIO_MODE_REG, gpio_mask, 2055 2055 + FIELD_PREP(AD4170_GPIO_MODE_GPIO3_MSK, 2056 2056 + AD4170_GPIO_MODE_GPIO_OUTPUT) | 2057 2057 + FIELD_PREP(AD4170_GPIO_MODE_GPIO2_MSK, 2058 2058 + AD4170_GPIO_MODE_GPIO_OUTPUT)); 2059 2059 + if (ret) 2060 2060 + return ret; 2061 2061 + 2062 2062 + /* 2063 2063 + * Set GPIO2 high and GPIO3 low to DC excite the bridge when 2064 2064 + * a different channel is selected. 2065 2065 + */ 2066 2066 + gpio_mask = AD4170_GPIO_OUTPUT_GPIO_MSK(3) | 2067 2067 + AD4170_GPIO_OUTPUT_GPIO_MSK(2); 2068 2068 + ret = regmap_update_bits(st->regmap, AD4170_GPIO_OUTPUT_REG, gpio_mask, 2069 2069 + FIELD_PREP(AD4170_GPIO_OUTPUT_GPIO_MSK(3), 0) | 2070 2070 + FIELD_PREP(AD4170_GPIO_OUTPUT_GPIO_MSK(2), 1)); 2071 2071 + if (ret) 2072 2072 + return ret; 2073 2073 + 2074 2074 + st->gpio_fn[3] |= AD4170_GPIO_OUTPUT; 2075 2075 + st->gpio_fn[2] |= AD4170_GPIO_OUTPUT; 2076 2076 + } else { 2077 2077 + setup->misc |= FIELD_PREP(AD4170_MISC_CHOP_ADC_MSK, 0x2); 2078 2078 + 2079 2079 + gpio_mask = AD4170_GPIO_MODE_GPIO3_MSK | AD4170_GPIO_MODE_GPIO2_MSK | 2080 2080 + AD4170_GPIO_MODE_GPIO1_MSK | AD4170_GPIO_MODE_GPIO0_MSK; 2081 2081 + ret = regmap_update_bits(st->regmap, AD4170_GPIO_MODE_REG, gpio_mask, 2082 2082 + FIELD_PREP(AD4170_GPIO_MODE_GPIO3_MSK, 2083 2083 + AD4170_GPIO_MODE_GPIO_OUTPUT) | 2084 2084 + FIELD_PREP(AD4170_GPIO_MODE_GPIO2_MSK, 2085 2085 + AD4170_GPIO_MODE_GPIO_OUTPUT) | 2086 2086 + FIELD_PREP(AD4170_GPIO_MODE_GPIO1_MSK, 2087 2087 + AD4170_GPIO_MODE_GPIO_OUTPUT) | 2088 2088 + FIELD_PREP(AD4170_GPIO_MODE_GPIO0_MSK, 2089 2089 + AD4170_GPIO_MODE_GPIO_OUTPUT)); 2090 2090 + if (ret) 2091 2091 + return ret; 2092 2092 + 2093 2093 + /* 2094 2094 + * Set GPIO2 and GPIO0 high, and set GPIO1 and GPIO3 low to DC 2095 2095 + * excite the bridge when a different channel is selected. 2096 2096 + */ 2097 2097 + gpio_mask = AD4170_GPIO_OUTPUT_GPIO_MSK(3) | 2098 2098 + AD4170_GPIO_OUTPUT_GPIO_MSK(2) | 2099 2099 + AD4170_GPIO_OUTPUT_GPIO_MSK(1) | 2100 2100 + AD4170_GPIO_OUTPUT_GPIO_MSK(0); 2101 2101 + ret = regmap_update_bits(st->regmap, AD4170_GPIO_OUTPUT_REG, gpio_mask, 2102 2102 + FIELD_PREP(AD4170_GPIO_OUTPUT_GPIO_MSK(3), 0) | 2103 2103 + FIELD_PREP(AD4170_GPIO_OUTPUT_GPIO_MSK(2), 1) | 2104 2104 + FIELD_PREP(AD4170_GPIO_OUTPUT_GPIO_MSK(1), 0) | 2105 2105 + FIELD_PREP(AD4170_GPIO_OUTPUT_GPIO_MSK(0), 1)); 2106 2106 + if (ret) 2107 2107 + return ret; 2108 2108 + 2109 2109 + st->gpio_fn[3] |= AD4170_GPIO_OUTPUT; 2110 2110 + st->gpio_fn[2] |= AD4170_GPIO_OUTPUT; 2111 2111 + st->gpio_fn[1] |= AD4170_GPIO_OUTPUT; 2112 2112 + st->gpio_fn[0] |= AD4170_GPIO_OUTPUT; 2113 2113 + } 2114 2114 + 2115 2115 + return 0; 2116 2116 + } 2117 2117 + 2118 2118 + static int ad4170_setup_rtd(struct ad4170_state *st, 2119 2119 + struct fwnode_handle *child, 2120 2120 + struct ad4170_setup *setup, u32 *exc_pins, 2121 2121 + unsigned int *exc_curs, int num_exc_pins, bool ac_excited) 2122 2122 + { 2123 2123 + return ad4170_setup_current_src(st, child, setup, exc_pins, 2124 2124 + exc_curs, num_exc_pins, ac_excited); 2125 2125 + } 2126 2126 + 2127 2127 + static int ad4170_parse_external_sensor(struct ad4170_state *st, 2128 2128 + struct fwnode_handle *child, 2129 2129 + struct ad4170_setup *setup, 2130 2130 + struct iio_chan_spec *chan, 2131 2131 + unsigned int s_type) 2132 2132 + { 2133 2133 + unsigned int num_exc_pins, reg_val; 2134 2134 + struct device *dev = &st->spi->dev; 2135 2135 + u32 pins[2], exc_pins[4], exc_curs[4]; 2136 2136 + bool ac_excited; 2137 2137 + int ret; 2138 2138 + 2139 2139 + ret = fwnode_property_read_u32_array(child, "diff-channels", pins, 2140 2140 + ARRAY_SIZE(pins)); 2141 2141 + if (ret) 2142 2142 + return dev_err_probe(dev, ret, 2143 2143 + "Failed to read sensor diff-channels\n"); 2144 2144 + 2145 2145 + chan->differential = true; 2146 2146 + chan->channel = pins[0]; 2147 2147 + chan->channel2 = pins[1]; 2148 2148 + 2149 2149 + ret = ad4170_parse_exc_current(st, child, exc_pins, exc_curs, &num_exc_pins); 2150 2150 + if (ret) 2151 2151 + return ret; 2152 2152 + 2153 2153 + /* The external sensor may not need excitation from the ADC chip. */ 2154 2154 + if (num_exc_pins == 0) 2155 2155 + return 0; 2156 2156 + 2157 2157 + ret = ad4170_validate_excitation_pins(st, exc_pins, num_exc_pins); 2158 2158 + if (ret) 2159 2159 + return ret; 2160 2160 + 2161 2161 + ac_excited = fwnode_property_read_bool(child, "adi,excitation-ac"); 2162 2162 + 2163 2163 + if (s_type == AD4170_THERMOCOUPLE_SENSOR) { 2164 2164 + if (st->pins_fn[chan->channel2] & AD4170_PIN_VBIAS) { 2165 2165 + reg_val = BIT(chan->channel2); 2166 2166 + ret = regmap_write(st->regmap, AD4170_V_BIAS_REG, reg_val); 2167 2167 + if (ret) 2168 2168 + dev_err_probe(dev, ret, "Failed to set vbias\n"); 2169 2169 + } 2170 2170 + } 2171 2171 + if (s_type == AD4170_WEIGH_SCALE_SENSOR) 2172 2172 + ret = ad4170_setup_bridge(st, child, setup, exc_pins, exc_curs, 2173 2173 + num_exc_pins, ac_excited); 2174 2174 + else 2175 2175 + ret = ad4170_setup_rtd(st, child, setup, exc_pins, exc_curs, 2176 2176 + num_exc_pins, ac_excited); 2177 2177 + 2178 2178 + return ret; 2179 2179 + } 2180 2180 + 2181 2181 + static int ad4170_parse_reference(struct ad4170_state *st, 2182 2182 + struct fwnode_handle *child, 2183 2183 + struct ad4170_setup *setup) 2184 2184 + { 2185 2185 + struct device *dev = &st->spi->dev; 2186 2186 + const char *propname; 2187 2187 + u32 aux; 2188 2188 + int ret; 2189 2189 + 2190 2190 + /* Optional positive reference buffering */ 2191 2191 + propname = "adi,positive-reference-buffer"; 2192 2192 + ret = device_property_match_property_string(dev, propname, 2193 2193 + ad4170_ref_buf_str, 2194 2194 + ARRAY_SIZE(ad4170_ref_buf_str)); 2195 2195 + 2196 2196 + /* Default to full precharge buffer enabled. */ 2197 2197 + setup->afe |= FIELD_PREP(AD4170_AFE_REF_BUF_P_MSK, 2198 2198 + ret >= 0 ? ret : AD4170_REF_BUF_FULL); 2199 2199 + 2200 2200 + /* Optional negative reference buffering */ 2201 2201 + propname = "adi,negative-reference-buffer"; 2202 2202 + ret = device_property_match_property_string(dev, propname, 2203 2203 + ad4170_ref_buf_str, 2204 2204 + ARRAY_SIZE(ad4170_ref_buf_str)); 2205 2205 + 2206 2206 + /* Default to full precharge buffer enabled. */ 2207 2207 + setup->afe |= FIELD_PREP(AD4170_AFE_REF_BUF_M_MSK, 2208 2208 + ret >= 0 ? ret : AD4170_REF_BUF_FULL); 2209 2209 + 2210 2210 + /* Optional voltage reference selection */ 2211 2211 + propname = "adi,reference-select"; 2212 2212 + aux = AD4170_REF_REFOUT; /* Default reference selection. */ 2213 2213 + fwnode_property_read_u32(child, propname, &aux); 2214 2214 + if (aux > AD4170_REF_AVDD) 2215 2215 + return dev_err_probe(dev, -EINVAL, "Invalid %s: %u\n", 2216 2216 + propname, aux); 2217 2217 + 2218 2218 + setup->afe |= FIELD_PREP(AD4170_AFE_REF_SELECT_MSK, aux); 2219 2219 + 2220 2220 + return 0; 2221 2221 + } 2222 2222 + 2223 2223 + static int ad4170_parse_adc_channel_type(struct device *dev, 2224 2224 + struct fwnode_handle *child, 2225 2225 + struct iio_chan_spec *chan) 2226 2226 + { 2227 2227 + const char *propname, *propname2; 2228 2228 + int ret, ret2; 2229 2229 + u32 pins[2]; 2230 2230 + 2231 2231 + propname = "single-channel"; 2232 2232 + propname2 = "diff-channels"; 2233 2233 + if (!fwnode_property_present(child, propname) && 2234 2234 + !fwnode_property_present(child, propname2)) 2235 2235 + return dev_err_probe(dev, -EINVAL, 2236 2236 + "Channel must define one of %s or %s.\n", 2237 2237 + propname, propname2); 2238 2238 + 2239 2239 + /* Parse differential channel configuration */ 2240 2240 + ret = fwnode_property_read_u32_array(child, propname2, pins, 2241 2241 + ARRAY_SIZE(pins)); 2242 2242 + if (!ret) { 2243 2243 + chan->differential = true; 2244 2244 + chan->channel = pins[0]; 2245 2245 + chan->channel2 = pins[1]; 2246 2246 + return 0; 2247 2247 + } 2248 2248 + /* Failed to parse diff chan so try pseudo-diff chan props */ 2249 2249 + 2250 2250 + propname2 = "common-mode-channel"; 2251 2251 + if (fwnode_property_present(child, propname) && 2252 2252 + !fwnode_property_present(child, propname2)) 2253 2253 + return dev_err_probe(dev, -EINVAL, 2254 2254 + "When %s is defined, %s must be defined too\n", 2255 2255 + propname, propname2); 2256 2256 + 2257 2257 + /* Parse pseudo-differential channel configuration */ 2258 2258 + ret = fwnode_property_read_u32(child, propname, &pins[0]); 2259 2259 + ret2 = fwnode_property_read_u32(child, propname2, &pins[1]); 2260 2260 + 2261 2261 + if (!ret && !ret2) { 2262 2262 + chan->differential = false; 2263 2263 + chan->channel = pins[0]; 2264 2264 + chan->channel2 = pins[1]; 2265 2265 + return 0; 2266 2266 + } 2267 2267 + return dev_err_probe(dev, -EINVAL, 2268 2268 + "Failed to parse channel %lu input. %d, %d\n", 2269 2269 + chan->address, ret, ret2); 2270 2270 + } 2271 2271 + 2272 2272 + static int ad4170_parse_channel_node(struct iio_dev *indio_dev, 2273 2273 + struct fwnode_handle *child, 2274 2274 + unsigned int chan_num) 2275 2275 + { 2276 2276 + struct ad4170_state *st = iio_priv(indio_dev); 2277 2277 + unsigned int s_type = AD4170_ADC_SENSOR; 2278 2278 + struct device *dev = &st->spi->dev; 2279 2279 + struct ad4170_chan_info *chan_info; 2280 2280 + struct ad4170_setup *setup; 2281 2281 + struct iio_chan_spec *chan; 2282 2282 + unsigned int ref_select; 2283 2283 + unsigned int ch_reg; 2284 2284 + bool bipolar; 2285 2285 + int ret; 2286 2286 + 2287 2287 + ret = fwnode_property_read_u32(child, "reg", &ch_reg); 2288 2288 + if (ret) 2289 2289 + return dev_err_probe(dev, ret, "Failed to read channel reg\n"); 2290 2290 + 2291 2291 + if (ch_reg >= AD4170_MAX_ADC_CHANNELS) 2292 2292 + return dev_err_probe(dev, -EINVAL, 2293 2293 + "Channel idx greater than no of channels\n"); 2294 2294 + 2295 2295 + chan = &st->chans[chan_num]; 2296 2296 + *chan = ad4170_channel_template; 2297 2297 + 2298 2298 + chan->address = ch_reg; 2299 2299 + chan->scan_index = ch_reg; 2300 2300 + chan_info = &st->chan_infos[chan->address]; 2301 2301 + 2302 2302 + chan_info->setup_num = AD4170_INVALID_SETUP; 2303 2303 + chan_info->initialized = true; 2304 2304 + 2305 2305 + setup = &chan_info->setup; 2306 2306 + ret = ad4170_parse_reference(st, child, setup); 2307 2307 + if (ret) 2308 2308 + return ret; 2309 2309 + 2310 2310 + ret = fwnode_property_match_property_string(child, "adi,sensor-type", 2311 2311 + ad4170_sensor_type, 2312 2312 + ARRAY_SIZE(ad4170_sensor_type)); 2313 2313 + 2314 2314 + /* Default to conventional ADC channel if sensor type not present */ 2315 2315 + s_type = ret < 0 ? AD4170_ADC_SENSOR : ret; 2316 2316 + switch (s_type) { 2317 2317 + case AD4170_ADC_SENSOR: 2318 2318 + ret = ad4170_parse_adc_channel_type(dev, child, chan); 2319 2319 + if (ret) 2320 2320 + return ret; 2321 2321 + 2322 2322 + break; 2323 2323 + case AD4170_WEIGH_SCALE_SENSOR: 2324 2324 + case AD4170_THERMOCOUPLE_SENSOR: 2325 2325 + case AD4170_RTD_SENSOR: 2326 2326 + ret = ad4170_parse_external_sensor(st, child, setup, chan, s_type); 2327 2327 + if (ret) 2328 2328 + return ret; 2329 2329 + 2330 2330 + break; 2331 2331 + default: 2332 2332 + return -EINVAL; 2333 2333 + } 2334 2334 + 2335 2335 + bipolar = fwnode_property_read_bool(child, "bipolar"); 2336 2336 + setup->afe |= FIELD_PREP(AD4170_AFE_BIPOLAR_MSK, bipolar); 2337 2337 + if (bipolar) 2338 2338 + chan->scan_type.sign = 's'; 2339 2339 + else 2340 2340 + chan->scan_type.sign = 'u'; 2341 2341 + 2342 2342 + ret = ad4170_validate_channel(st, chan); 2343 2343 + if (ret) 2344 2344 + return ret; 2345 2345 + 2346 2346 + ref_select = FIELD_GET(AD4170_AFE_REF_SELECT_MSK, setup->afe); 2347 2347 + ret = ad4170_get_input_range(st, chan, ch_reg, ref_select); 2348 2348 + if (ret < 0) 2349 2349 + return dev_err_probe(dev, ret, "Invalid input config\n"); 2350 2350 + 2351 2351 + chan_info->input_range_uv = ret; 2352 2352 + return 0; 2353 2353 + } 2354 2354 + 2355 2355 + static int ad4170_parse_channels(struct iio_dev *indio_dev) 2356 2356 + { 2357 2357 + struct ad4170_state *st = iio_priv(indio_dev); 2358 2358 + struct device *dev = &st->spi->dev; 2359 2359 + unsigned int num_channels; 2360 2360 + unsigned int chan_num; 2361 2361 + int ret; 2362 2362 + 2363 2363 + num_channels = device_get_child_node_count(dev); 2364 2364 + 2365 2365 + if (num_channels > AD4170_MAX_ADC_CHANNELS) 2366 2366 + return dev_err_probe(dev, -EINVAL, "Too many channels\n"); 2367 2367 + 2368 2368 + /* Add one for temperature */ 2369 2369 + num_channels = min(num_channels + 1, AD4170_MAX_ADC_CHANNELS); 2370 2370 + 2371 2371 + chan_num = 0; 2372 2372 + device_for_each_child_node_scoped(dev, child) { 2373 2373 + ret = ad4170_parse_channel_node(indio_dev, child, chan_num++); 2374 2374 + if (ret) 2375 2375 + return ret; 2376 2376 + } 2377 2377 + 2378 2378 + /* 2379 2379 + * Add internal temperature sensor channel if the maximum number of 2380 2380 + * channels has not been reached. 2381 2381 + */ 2382 2382 + if (num_channels < AD4170_MAX_ADC_CHANNELS) { 2383 2383 + struct ad4170_setup *setup = &st->chan_infos[chan_num].setup; 2384 2384 + 2385 2385 + st->chans[chan_num] = ad4170_temp_channel_template; 2386 2386 + st->chans[chan_num].address = chan_num; 2387 2387 + st->chans[chan_num].scan_index = chan_num; 2388 2388 + 2389 2389 + st->chan_infos[chan_num].setup_num = AD4170_INVALID_SETUP; 2390 2390 + st->chan_infos[chan_num].initialized = true; 2391 2391 + 2392 2392 + setup->afe |= FIELD_PREP(AD4170_AFE_REF_SELECT_MSK, 2393 2393 + AD4170_REF_AVDD); 2394 2394 + 2395 2395 + ret = ad4170_get_input_range(st, &st->chans[chan_num], chan_num, 2396 2396 + AD4170_REF_AVDD); 2397 2397 + if (ret < 0) 2398 2398 + return dev_err_probe(dev, ret, "Invalid input config\n"); 2399 2399 + 2400 2400 + st->chan_infos[chan_num].input_range_uv = ret; 2401 2401 + chan_num++; 2402 2402 + } 2403 2403 + 2404 2404 + /* Add timestamp channel */ 2405 2405 + struct iio_chan_spec ts_chan = IIO_CHAN_SOFT_TIMESTAMP(chan_num); 2406 2406 + 2407 2407 + st->chans[chan_num] = ts_chan; 2408 2408 + num_channels = num_channels + 1; 2409 2409 + 2410 2410 + indio_dev->num_channels = num_channels; 2411 2411 + indio_dev->channels = st->chans; 2412 2412 + 2413 2413 + return 0; 2414 2414 + } 2415 2415 + 2416 2416 + static struct ad4170_state *clk_hw_to_ad4170(struct clk_hw *hw) 2417 2417 + { 2418 2418 + return container_of(hw, struct ad4170_state, int_clk_hw); 2419 2419 + } 2420 2420 + 2421 2421 + static unsigned long ad4170_sel_clk(struct ad4170_state *st, 2422 2422 + unsigned int clk_sel) 2423 2423 + { 2424 2424 + st->clock_ctrl &= ~AD4170_CLOCK_CTRL_CLOCKSEL_MSK; 2425 2425 + st->clock_ctrl |= FIELD_PREP(AD4170_CLOCK_CTRL_CLOCKSEL_MSK, clk_sel); 2426 2426 + return regmap_write(st->regmap, AD4170_CLOCK_CTRL_REG, st->clock_ctrl); 2427 2427 + } 2428 2428 + 2429 2429 + static unsigned long ad4170_clk_recalc_rate(struct clk_hw *hw, 2430 2430 + unsigned long parent_rate) 2431 2431 + { 2432 2432 + return AD4170_INT_CLOCK_16MHZ; 2433 2433 + } 2434 2434 + 2435 2435 + static int ad4170_clk_output_is_enabled(struct clk_hw *hw) 2436 2436 + { 2437 2437 + struct ad4170_state *st = clk_hw_to_ad4170(hw); 2438 2438 + u32 clk_sel; 2439 2439 + 2440 2440 + clk_sel = FIELD_GET(AD4170_CLOCK_CTRL_CLOCKSEL_MSK, st->clock_ctrl); 2441 2441 + return clk_sel == AD4170_CLOCK_CTRL_CLOCKSEL_INT_OUT; 2442 2442 + } 2443 2443 + 2444 2444 + static int ad4170_clk_output_prepare(struct clk_hw *hw) 2445 2445 + { 2446 2446 + struct ad4170_state *st = clk_hw_to_ad4170(hw); 2447 2447 + 2448 2448 + return ad4170_sel_clk(st, AD4170_CLOCK_CTRL_CLOCKSEL_INT_OUT); 2449 2449 + } 2450 2450 + 2451 2451 + static void ad4170_clk_output_unprepare(struct clk_hw *hw) 2452 2452 + { 2453 2453 + struct ad4170_state *st = clk_hw_to_ad4170(hw); 2454 2454 + 2455 2455 + ad4170_sel_clk(st, AD4170_CLOCK_CTRL_CLOCKSEL_INT); 2456 2456 + } 2457 2457 + 2458 2458 + static const struct clk_ops ad4170_int_clk_ops = { 2459 2459 + .recalc_rate = ad4170_clk_recalc_rate, 2460 2460 + .is_enabled = ad4170_clk_output_is_enabled, 2461 2461 + .prepare = ad4170_clk_output_prepare, 2462 2462 + .unprepare = ad4170_clk_output_unprepare, 2463 2463 + }; 2464 2464 + 2465 2465 + static int ad4170_register_clk_provider(struct iio_dev *indio_dev) 2466 2466 + { 2467 2467 + struct ad4170_state *st = iio_priv(indio_dev); 2468 2468 + struct device *dev = indio_dev->dev.parent; 2469 2469 + struct clk_init_data init = {}; 2470 2470 + int ret; 2471 2471 + 2472 2472 + if (device_property_read_string(dev, "clock-output-names", &init.name)) { 2473 2473 + init.name = devm_kasprintf(dev, GFP_KERNEL, "%pfw", 2474 2474 + dev_fwnode(dev)); 2475 2475 + if (!init.name) 2476 2476 + return -ENOMEM; 2477 2477 + } 2478 2478 + 2479 2479 + init.ops = &ad4170_int_clk_ops; 2480 2480 + 2481 2481 + st->int_clk_hw.init = &init; 2482 2482 + ret = devm_clk_hw_register(dev, &st->int_clk_hw); 2483 2483 + if (ret) 2484 2484 + return ret; 2485 2485 + 2486 2486 + return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, 2487 2487 + &st->int_clk_hw); 2488 2488 + } 2489 2489 + 2490 2490 + static int ad4170_clock_select(struct iio_dev *indio_dev) 2491 2491 + { 2492 2492 + struct ad4170_state *st = iio_priv(indio_dev); 2493 2493 + struct device *dev = &st->spi->dev; 2494 2494 + struct clk *ext_clk; 2495 2495 + int ret; 2496 2496 + 2497 2497 + ext_clk = devm_clk_get_optional_enabled(dev, NULL); 2498 2498 + if (IS_ERR(ext_clk)) 2499 2499 + return dev_err_probe(dev, PTR_ERR(ext_clk), 2500 2500 + "Failed to get external clock\n"); 2501 2501 + 2502 2502 + if (!ext_clk) { 2503 2503 + /* Use internal clock reference */ 2504 2504 + st->mclk_hz = AD4170_INT_CLOCK_16MHZ; 2505 2505 + st->clock_ctrl |= FIELD_PREP(AD4170_CLOCK_CTRL_CLOCKSEL_MSK, 2506 2506 + AD4170_CLOCK_CTRL_CLOCKSEL_INT_OUT); 2507 2507 + 2508 2508 + if (!device_property_present(&st->spi->dev, "#clock-cells")) 2509 2509 + return 0; 2510 2510 + 2511 2511 + return ad4170_register_clk_provider(indio_dev); 2512 2512 + } 2513 2513 + 2514 2514 + /* Read optional clock-names prop to specify the external clock type */ 2515 2515 + ret = device_property_match_property_string(dev, "clock-names", 2516 2516 + ad4170_clk_sel, 2517 2517 + ARRAY_SIZE(ad4170_clk_sel)); 2518 2518 + 2519 2519 + ret = ret < 0 ? 0 : ret; /* Default to external clock if no clock-names */ 2520 2520 + st->clock_ctrl |= FIELD_PREP(AD4170_CLOCK_CTRL_CLOCKSEL_MSK, 2521 2521 + AD4170_CLOCK_CTRL_CLOCKSEL_EXT + ret); 2522 2522 + 2523 2523 + st->mclk_hz = clk_get_rate(ext_clk); 2524 2524 + if (st->mclk_hz < AD4170_EXT_CLOCK_MHZ_MIN || 2525 2525 + st->mclk_hz > AD4170_EXT_CLOCK_MHZ_MAX) { 2526 2526 + return dev_err_probe(dev, -EINVAL, 2527 2527 + "Invalid external clock frequency %u\n", 2528 2528 + st->mclk_hz); 2529 2529 + } 2530 2530 + 2531 2531 + return 0; 2532 2532 + } 2533 2533 + 2534 2534 + static int ad4170_parse_firmware(struct iio_dev *indio_dev) 2535 2535 + { 2536 2536 + unsigned int vbias_pins[AD4170_MAX_ANALOG_PINS]; 2537 2537 + struct ad4170_state *st = iio_priv(indio_dev); 2538 2538 + struct device *dev = &st->spi->dev; 2539 2539 + unsigned int num_vbias_pins; 2540 2540 + int reg_data, ret; 2541 2541 + u32 int_pin_sel; 2542 2542 + unsigned int i; 2543 2543 + 2544 2544 + ret = ad4170_clock_select(indio_dev); 2545 2545 + if (ret) 2546 2546 + return dev_err_probe(dev, ret, "Failed to setup device clock\n"); 2547 2547 + 2548 2548 + ret = regmap_write(st->regmap, AD4170_CLOCK_CTRL_REG, st->clock_ctrl); 2549 2549 + if (ret) 2550 2550 + return ret; 2551 2551 + 2552 2552 + for (i = 0; i < AD4170_NUM_CURRENT_SRC; i++) 2553 2553 + st->cur_src_pins[i] = AD4170_CURRENT_SRC_DISABLED; 2554 2554 + 2555 2555 + /* On power on, device defaults to using SDO pin for data ready signal */ 2556 2556 + int_pin_sel = AD4170_INT_PIN_SDO; 2557 2557 + ret = device_property_match_property_string(dev, "interrupt-names", 2558 2558 + ad4170_int_pin_names, 2559 2559 + ARRAY_SIZE(ad4170_int_pin_names)); 2560 2560 + if (ret >= 0) 2561 2561 + int_pin_sel = ret; 2562 2562 + 2563 2563 + reg_data = FIELD_PREP(AD4170_PIN_MUXING_DIG_AUX1_CTRL_MSK, 2564 2564 + int_pin_sel == AD4170_INT_PIN_DIG_AUX1 ? 2565 2565 + AD4170_PIN_MUXING_DIG_AUX1_RDY : 2566 2566 + AD4170_PIN_MUXING_DIG_AUX1_DISABLED); 2567 2567 + 2568 2568 + ret = regmap_update_bits(st->regmap, AD4170_PIN_MUXING_REG, 2569 2569 + AD4170_PIN_MUXING_DIG_AUX1_CTRL_MSK, reg_data); 2570 2570 + if (ret) 2571 2571 + return ret; 2572 2572 + 2573 2573 + ret = device_property_count_u32(dev, "adi,vbias-pins"); 2574 2574 + if (ret > 0) { 2575 2575 + if (ret > AD4170_MAX_ANALOG_PINS) 2576 2576 + return dev_err_probe(dev, -EINVAL, 2577 2577 + "Too many vbias pins %u\n", ret); 2578 2578 + 2579 2579 + num_vbias_pins = ret; 2580 2580 + 2581 2581 + ret = device_property_read_u32_array(dev, "adi,vbias-pins", 2582 2582 + vbias_pins, 2583 2583 + num_vbias_pins); 2584 2584 + if (ret) 2585 2585 + return dev_err_probe(dev, ret, 2586 2586 + "Failed to read vbias pins\n"); 2587 2587 + 2588 2588 + for (i = 0; i < num_vbias_pins; i++) 2589 2589 + st->pins_fn[vbias_pins[i]] |= AD4170_PIN_VBIAS; 2590 2590 + } 2591 2591 + 2592 2592 + ret = ad4170_parse_channels(indio_dev); 2593 2593 + if (ret) 2594 2594 + return ret; 2595 2595 + 2596 2596 + /* Only create a GPIO chip if flagged for it */ 2597 2597 + if (device_property_read_bool(dev, "gpio-controller")) { 2598 2598 + ret = ad4170_gpio_init(indio_dev); 2599 2599 + if (ret) 2600 2600 + return ret; 2601 2601 + } 2602 2602 + 2603 2603 + return 0; 2604 2604 + } 2605 2605 + 2606 2606 + static int ad4170_initial_config(struct iio_dev *indio_dev) 2607 2607 + { 2608 2608 + struct ad4170_state *st = iio_priv(indio_dev); 2609 2609 + struct device *dev = &st->spi->dev; 2610 2610 + unsigned int i; 2611 2611 + int ret; 2612 2612 + 2613 2613 + ad4170_fill_sps_tbl(st); 2614 2614 + 2615 2615 + ret = regmap_update_bits(st->regmap, AD4170_ADC_CTRL_REG, 2616 2616 + AD4170_ADC_CTRL_MODE_MSK, 2617 2617 + FIELD_PREP(AD4170_ADC_CTRL_MODE_MSK, 2618 2618 + AD4170_ADC_CTRL_MODE_IDLE)); 2619 2619 + if (ret) 2620 2620 + return dev_err_probe(dev, ret, 2621 2621 + "Failed to set ADC mode to idle\n"); 2622 2622 + 2623 2623 + for (i = 0; i < indio_dev->num_channels; i++) { 2624 2624 + struct ad4170_chan_info *chan_info; 2625 2625 + struct iio_chan_spec const *chan; 2626 2626 + struct ad4170_setup *setup; 2627 2627 + unsigned int val; 2628 2628 + 2629 2629 + chan = &indio_dev->channels[i]; 2630 2630 + if (chan->type == IIO_TIMESTAMP) 2631 2631 + continue; 2632 2632 + 2633 2633 + chan_info = &st->chan_infos[chan->address]; 2634 2634 + 2635 2635 + setup = &chan_info->setup; 2636 2636 + setup->gain = AD4170_GAIN_REG_DEFAULT; 2637 2637 + ret = ad4170_write_channel_setup(st, chan->address, false); 2638 2638 + if (ret) 2639 2639 + return dev_err_probe(dev, ret, 2640 2640 + "Failed to write channel setup\n"); 2641 2641 + 2642 2642 + val = FIELD_PREP(AD4170_CHAN_MAP_AINP_MSK, chan->channel) | 2643 2643 + FIELD_PREP(AD4170_CHAN_MAP_AINM_MSK, chan->channel2); 2644 2644 + 2645 2645 + ret = regmap_write(st->regmap, AD4170_CHAN_MAP_REG(i), val); 2646 2646 + if (ret) 2647 2647 + return dev_err_probe(dev, ret, 2648 2648 + "Failed to write CHAN_MAP_REG\n"); 2649 2649 + 2650 2650 + ret = ad4170_set_channel_freq(st, chan, 2651 2651 + AD4170_DEFAULT_SAMP_RATE, 0); 2652 2652 + if (ret) 2653 2653 + return dev_err_probe(dev, ret, 2654 2654 + "Failed to set channel freq\n"); 2655 2655 + 2656 2656 + ret = ad4170_fill_scale_tbl(indio_dev, chan); 2657 2657 + if (ret) 2658 2658 + return dev_err_probe(dev, ret, 2659 2659 + "Failed to fill scale tbl\n"); 2660 2660 + } 2661 2661 + 2662 2662 + /* Disable all channels to avoid reading from unexpected channel */ 2663 2663 + ret = regmap_write(st->regmap, AD4170_CHAN_EN_REG, 0); 2664 2664 + if (ret) 2665 2665 + return dev_err_probe(dev, ret, 2666 2666 + "Failed to disable channels\n"); 2667 2667 + 2668 2668 + /* 2669 2669 + * Configure channels to share the same data output register, i.e. data 2670 2670 + * can be read from the same register address regardless of channel 2671 2671 + * number. 2672 2672 + */ 2673 2673 + return regmap_update_bits(st->regmap, AD4170_ADC_CTRL_REG, 2674 2674 + AD4170_ADC_CTRL_MULTI_DATA_REG_SEL_MSK, 2675 2675 + AD4170_ADC_CTRL_MULTI_DATA_REG_SEL_MSK); 2676 2676 + } 2677 2677 + 2678 2678 + static int ad4170_prepare_spi_message(struct ad4170_state *st) 2679 2679 + { 2680 2680 + /* 2681 2681 + * Continuous data register read is enabled on buffer postenable so 2682 2682 + * no instruction phase is needed meaning we don't need to send the 2683 2683 + * register address to read data. Transfer only needs the read buffer. 2684 2684 + */ 2685 2685 + st->xfer.rx_buf = &st->rx_buf; 2686 2686 + st->xfer.len = BITS_TO_BYTES(ad4170_channel_template.scan_type.realbits); 2687 2687 + 2688 2688 + spi_message_init_with_transfers(&st->msg, &st->xfer, 1); 2689 2689 + 2690 2690 + return devm_spi_optimize_message(&st->spi->dev, st->spi, &st->msg); 2691 2691 + } 2692 2692 + 2693 2693 + static int ad4170_buffer_postenable(struct iio_dev *indio_dev) 2694 2694 + { 2695 2695 + struct ad4170_state *st = iio_priv(indio_dev); 2696 2696 + int ret; 2697 2697 + 2698 2698 + ret = regmap_update_bits(st->regmap, AD4170_ADC_CTRL_REG, 2699 2699 + AD4170_ADC_CTRL_MODE_MSK, 2700 2700 + FIELD_PREP(AD4170_ADC_CTRL_MODE_MSK, 2701 2701 + AD4170_ADC_CTRL_MODE_CONT)); 2702 2702 + if (ret) 2703 2703 + return ret; 2704 2704 + 2705 2705 + /* 2706 2706 + * This enables continuous read of the ADC data register. The ADC must 2707 2707 + * be in continuous conversion mode. 2708 2708 + */ 2709 2709 + return regmap_update_bits(st->regmap, AD4170_ADC_CTRL_REG, 2710 2710 + AD4170_ADC_CTRL_CONT_READ_MSK, 2711 2711 + FIELD_PREP(AD4170_ADC_CTRL_CONT_READ_MSK, 2712 2712 + AD4170_ADC_CTRL_CONT_READ_ENABLE)); 2713 2713 + } 2714 2714 + 2715 2715 + static int ad4170_buffer_predisable(struct iio_dev *indio_dev) 2716 2716 + { 2717 2717 + struct ad4170_state *st = iio_priv(indio_dev); 2718 2718 + unsigned int i; 2719 2719 + int ret; 2720 2720 + 2721 2721 + /* 2722 2722 + * Use a high register address (virtual register) to request a write of 2723 2723 + * 0xA5 to the ADC during the first 8 SCLKs of the ADC data read cycle, 2724 2724 + * thus exiting continuous read. 2725 2725 + */ 2726 2726 + ret = regmap_write(st->regmap, AD4170_ADC_CTRL_CONT_READ_EXIT_REG, 0); 2727 2727 + if (ret) 2728 2728 + return ret; 2729 2729 + 2730 2730 + ret = regmap_update_bits(st->regmap, AD4170_ADC_CTRL_REG, 2731 2731 + AD4170_ADC_CTRL_CONT_READ_MSK, 2732 2732 + FIELD_PREP(AD4170_ADC_CTRL_CONT_READ_MSK, 2733 2733 + AD4170_ADC_CTRL_CONT_READ_DISABLE)); 2734 2734 + if (ret) 2735 2735 + return ret; 2736 2736 + 2737 2737 + ret = regmap_update_bits(st->regmap, AD4170_ADC_CTRL_REG, 2738 2738 + AD4170_ADC_CTRL_MODE_MSK, 2739 2739 + FIELD_PREP(AD4170_ADC_CTRL_MODE_MSK, 2740 2740 + AD4170_ADC_CTRL_MODE_IDLE)); 2741 2741 + if (ret) 2742 2742 + return ret; 2743 2743 + 2744 2744 + /* 2745 2745 + * The ADC sequences through all the enabled channels (see datasheet 2746 2746 + * page 95). That can lead to incorrect channel being read if a 2747 2747 + * single-shot read (or buffered read with different active_scan_mask) 2748 2748 + * is done after buffer disable. Disable all channels so only requested 2749 2749 + * channels will be read. 2750 2750 + */ 2751 2751 + for (i = 0; i < indio_dev->num_channels; i++) { 2752 2752 + if (indio_dev->channels[i].type == IIO_TIMESTAMP) 2753 2753 + continue; 2754 2754 + 2755 2755 + ret = ad4170_set_channel_enable(st, i, false); 2756 2756 + if (ret) 2757 2757 + return ret; 2758 2758 + } 2759 2759 + 2760 2760 + return 0; 2761 2761 + } 2762 2762 + 2763 2763 + static bool ad4170_validate_scan_mask(struct iio_dev *indio_dev, 2764 2764 + const unsigned long *scan_mask) 2765 2765 + { 2766 2766 + unsigned int masklength = iio_get_masklength(indio_dev); 2767 2767 + unsigned int enabled; 2768 2768 + 2769 2769 + /* 2770 2770 + * The channel sequencer cycles through the enabled channels in 2771 2771 + * sequential order, from channel 0 to channel 15, bypassing disabled 2772 2772 + * channels. When more than one channel is enabled, channel 0 must 2773 2773 + * always be enabled. See datasheet channel_en register description at 2774 2774 + * page 95. 2775 2775 + */ 2776 2776 + enabled = bitmap_weight(scan_mask, masklength); 2777 2777 + if (enabled > 1) 2778 2778 + return test_bit(0, scan_mask); 2779 2779 + 2780 2780 + return enabled == 1; 2781 2781 + } 2782 2782 + 2783 2783 + static const struct iio_buffer_setup_ops ad4170_buffer_ops = { 2784 2784 + .postenable = ad4170_buffer_postenable, 2785 2785 + .predisable = ad4170_buffer_predisable, 2786 2786 + .validate_scan_mask = ad4170_validate_scan_mask, 2787 2787 + }; 2788 2788 + 2789 2789 + static irqreturn_t ad4170_trigger_handler(int irq, void *p) 2790 2790 + { 2791 2791 + struct iio_poll_func *pf = p; 2792 2792 + struct iio_dev *indio_dev = pf->indio_dev; 2793 2793 + struct ad4170_state *st = iio_priv(indio_dev); 2794 2794 + unsigned int chan_index; 2795 2795 + unsigned int i = 0; 2796 2796 + int ret; 2797 2797 + 2798 2798 + iio_for_each_active_channel(indio_dev, chan_index) { 2799 2799 + ret = spi_sync(st->spi, &st->msg); 2800 2800 + if (ret) 2801 2801 + goto err_out; 2802 2802 + 2803 2803 + memcpy(&st->bounce_buffer[i++], st->rx_buf, ARRAY_SIZE(st->rx_buf)); 2804 2804 + } 2805 2805 + 2806 2806 + iio_push_to_buffers_with_ts(indio_dev, st->bounce_buffer, 2807 2807 + sizeof(st->bounce_buffer), 2808 2808 + iio_get_time_ns(indio_dev)); 2809 2809 + err_out: 2810 2810 + iio_trigger_notify_done(indio_dev->trig); 2811 2811 + return IRQ_HANDLED; 2812 2812 + } 2813 2813 + 2814 2814 + static const struct iio_trigger_ops ad4170_trigger_ops = { 2815 2815 + .validate_device = iio_trigger_validate_own_device, 2816 2816 + }; 2817 2817 + 2818 2818 + static irqreturn_t ad4170_irq_handler(int irq, void *dev_id) 2819 2819 + { 2820 2820 + struct iio_dev *indio_dev = dev_id; 2821 2821 + struct ad4170_state *st = iio_priv(indio_dev); 2822 2822 + 2823 2823 + if (iio_buffer_enabled(indio_dev)) 2824 2824 + iio_trigger_poll(st->trig); 2825 2825 + else 2826 2826 + complete(&st->completion); 2827 2827 + 2828 2828 + return IRQ_HANDLED; 2829 2829 + }; 2830 2830 + 2831 2831 + static int ad4170_trigger_setup(struct iio_dev *indio_dev) 2832 2832 + { 2833 2833 + struct ad4170_state *st = iio_priv(indio_dev); 2834 2834 + struct device *dev = &st->spi->dev; 2835 2835 + int ret; 2836 2836 + 2837 2837 + st->trig = devm_iio_trigger_alloc(dev, "%s-trig%d", 2838 2838 + indio_dev->name, 2839 2839 + iio_device_id(indio_dev)); 2840 2840 + if (!st->trig) 2841 2841 + return -ENOMEM; 2842 2842 + 2843 2843 + st->trig->ops = &ad4170_trigger_ops; 2844 2844 + 2845 2845 + iio_trigger_set_drvdata(st->trig, indio_dev); 2846 2846 + ret = devm_iio_trigger_register(dev, st->trig); 2847 2847 + if (ret) 2848 2848 + return dev_err_probe(dev, ret, "Failed to register trigger\n"); 2849 2849 + 2850 2850 + indio_dev->trig = iio_trigger_get(st->trig); 2851 2851 + 2852 2852 + return 0; 2853 2853 + } 2854 2854 + 2855 2855 + static int ad4170_regulator_setup(struct ad4170_state *st) 2856 2856 + { 2857 2857 + struct device *dev = &st->spi->dev; 2858 2858 + int ret; 2859 2859 + 2860 2860 + /* Required regulators */ 2861 2861 + ret = devm_regulator_get_enable_read_voltage(dev, "avdd"); 2862 2862 + if (ret < 0) 2863 2863 + return dev_err_probe(dev, ret, "Failed to get AVDD voltage.\n"); 2864 2864 + 2865 2865 + st->vrefs_uv[AD4170_AVDD_SUP] = ret; 2866 2866 + 2867 2867 + ret = devm_regulator_get_enable_read_voltage(dev, "iovdd"); 2868 2868 + if (ret < 0) 2869 2869 + return dev_err_probe(dev, ret, "Failed to get IOVDD voltage.\n"); 2870 2870 + 2871 2871 + st->vrefs_uv[AD4170_IOVDD_SUP] = ret; 2872 2872 + 2873 2873 + /* Optional regulators */ 2874 2874 + ret = devm_regulator_get_enable_read_voltage(dev, "avss"); 2875 2875 + if (ret < 0 && ret != -ENODEV) 2876 2876 + return dev_err_probe(dev, ret, "Failed to get AVSS voltage.\n"); 2877 2877 + 2878 2878 + /* 2879 2879 + * Assume AVSS at GND (0V) if not provided. 2880 2880 + * REVISIT: AVSS is never above system ground level (i.e. AVSS is either 2881 2881 + * GND or a negative voltage). But we currently don't have support for 2882 2882 + * reading negative voltages with the regulator framework. So, the 2883 2883 + * current AD4170 support reads a positive value from the regulator, 2884 2884 + * then inverts sign to make that negative. 2885 2885 + */ 2886 2886 + st->vrefs_uv[AD4170_AVSS_SUP] = ret == -ENODEV ? 0 : -ret; 2887 2887 + 2888 2888 + ret = devm_regulator_get_enable_read_voltage(dev, "refin1p"); 2889 2889 + if (ret < 0 && ret != -ENODEV) 2890 2890 + return dev_err_probe(dev, ret, "Failed to get REFIN+ voltage.\n"); 2891 2891 + 2892 2892 + st->vrefs_uv[AD4170_REFIN1P_SUP] = ret; 2893 2893 + 2894 2894 + ret = devm_regulator_get_enable_read_voltage(dev, "refin1n"); 2895 2895 + if (ret < 0 && ret != -ENODEV) 2896 2896 + return dev_err_probe(dev, ret, "Failed to get REFIN- voltage.\n"); 2897 2897 + 2898 2898 + /* 2899 2899 + * Negative supplies are assumed to provide negative voltage. 2900 2900 + * REVISIT when support for negative regulator voltage read be available 2901 2901 + * in the regulator framework. 2902 2902 + */ 2903 2903 + st->vrefs_uv[AD4170_REFIN1N_SUP] = ret == -ENODEV ? -ENODEV : -ret; 2904 2904 + 2905 2905 + ret = devm_regulator_get_enable_read_voltage(dev, "refin2p"); 2906 2906 + if (ret < 0 && ret != -ENODEV) 2907 2907 + return dev_err_probe(dev, ret, "Failed to get REFIN2+ voltage.\n"); 2908 2908 + 2909 2909 + st->vrefs_uv[AD4170_REFIN2P_SUP] = ret; 2910 2910 + 2911 2911 + ret = devm_regulator_get_enable_read_voltage(dev, "refin2n"); 2912 2912 + if (ret < 0 && ret != -ENODEV) 2913 2913 + return dev_err_probe(dev, ret, "Failed to get REFIN2- voltage.\n"); 2914 2914 + 2915 2915 + /* 2916 2916 + * Negative supplies are assumed to provide negative voltage. 2917 2917 + * REVISIT when support for negative regulator voltage read be available 2918 2918 + * in the regulator framework. 2919 2919 + */ 2920 2920 + st->vrefs_uv[AD4170_REFIN2N_SUP] = ret == -ENODEV ? -ENODEV : -ret; 2921 2921 + 2922 2922 + return 0; 2923 2923 + } 2924 2924 + 2925 2925 + static int ad4170_probe(struct spi_device *spi) 2926 2926 + { 2927 2927 + const struct ad4170_chip_info *chip; 2928 2928 + struct device *dev = &spi->dev; 2929 2929 + struct iio_dev *indio_dev; 2930 2930 + struct ad4170_state *st; 2931 2931 + int ret; 2932 2932 + 2933 2933 + indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 2934 2934 + if (!indio_dev) 2935 2935 + return -ENOMEM; 2936 2936 + 2937 2937 + st = iio_priv(indio_dev); 2938 2938 + st->spi = spi; 2939 2939 + 2940 2940 + ret = devm_mutex_init(dev, &st->lock); 2941 2941 + if (ret) 2942 2942 + return ret; 2943 2943 + 2944 2944 + chip = spi_get_device_match_data(spi); 2945 2945 + if (!chip) 2946 2946 + return -EINVAL; 2947 2947 + 2948 2948 + indio_dev->name = chip->name; 2949 2949 + indio_dev->info = &ad4170_info; 2950 2950 + 2951 2951 + st->regmap = devm_regmap_init(dev, NULL, st, &ad4170_regmap_config); 2952 2952 + if (IS_ERR(st->regmap)) 2953 2953 + return dev_err_probe(dev, PTR_ERR(st->regmap), 2954 2954 + "Failed to initialize regmap\n"); 2955 2955 + 2956 2956 + ret = ad4170_regulator_setup(st); 2957 2957 + if (ret) 2958 2958 + return ret; 2959 2959 + 2960 2960 + ret = ad4170_soft_reset(st); 2961 2961 + if (ret) 2962 2962 + return ret; 2963 2963 + 2964 2964 + ret = ad4170_parse_firmware(indio_dev); 2965 2965 + if (ret) 2966 2966 + return dev_err_probe(dev, ret, "Failed to parse firmware\n"); 2967 2967 + 2968 2968 + ret = ad4170_initial_config(indio_dev); 2969 2969 + if (ret) 2970 2970 + return dev_err_probe(dev, ret, "Failed to setup device\n"); 2971 2971 + 2972 2972 + init_completion(&st->completion); 2973 2973 + 2974 2974 + if (spi->irq) { 2975 2975 + ret = devm_request_irq(dev, spi->irq, &ad4170_irq_handler, 2976 2976 + IRQF_ONESHOT, indio_dev->name, indio_dev); 2977 2977 + if (ret) 2978 2978 + return ret; 2979 2979 + 2980 2980 + ret = ad4170_trigger_setup(indio_dev); 2981 2981 + if (ret) 2982 2982 + return ret; 2983 2983 + } 2984 2984 + 2985 2985 + ret = ad4170_prepare_spi_message(st); 2986 2986 + if (ret) 2987 2987 + return dev_err_probe(dev, ret, "Failed to prepare SPI message\n"); 2988 2988 + 2989 2989 + ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL, 2990 2990 + &ad4170_trigger_handler, 2991 2991 + &ad4170_buffer_ops); 2992 2992 + if (ret) 2993 2993 + return dev_err_probe(dev, ret, "Failed to setup read buffer\n"); 2994 2994 + 2995 2995 + return devm_iio_device_register(dev, indio_dev); 2996 2996 + } 2997 2997 + 2998 2998 + static const struct spi_device_id ad4170_id_table[] = { 2999 2999 + { "ad4170-4", (kernel_ulong_t)&ad4170_chip_info }, 3000 3000 + { "ad4190-4", (kernel_ulong_t)&ad4190_chip_info }, 3001 3001 + { "ad4195-4", (kernel_ulong_t)&ad4195_chip_info }, 3002 3002 + { } 3003 3003 + }; 3004 3004 + MODULE_DEVICE_TABLE(spi, ad4170_id_table); 3005 3005 + 3006 3006 + static const struct of_device_id ad4170_of_match[] = { 3007 3007 + { .compatible = "adi,ad4170-4", .data = &ad4170_chip_info }, 3008 3008 + { .compatible = "adi,ad4190-4", .data = &ad4190_chip_info }, 3009 3009 + { .compatible = "adi,ad4195-4", .data = &ad4195_chip_info }, 3010 3010 + { } 3011 3011 + }; 3012 3012 + MODULE_DEVICE_TABLE(of, ad4170_of_match); 3013 3013 + 3014 3014 + static struct spi_driver ad4170_driver = { 3015 3015 + .driver = { 3016 3016 + .name = "ad4170-4", 3017 3017 + .of_match_table = ad4170_of_match, 3018 3018 + }, 3019 3019 + .probe = ad4170_probe, 3020 3020 + .id_table = ad4170_id_table, 3021 3021 + }; 3022 3022 + module_spi_driver(ad4170_driver); 3023 3023 + 3024 3024 + MODULE_AUTHOR("Ana-Maria Cusco <ana-maria.cusco@analog.com>"); 3025 3025 + MODULE_AUTHOR("Marcelo Schmitt <marcelo.schmitt@analog.com>"); 3026 3026 + MODULE_DESCRIPTION("Analog Devices AD4170 SPI driver"); 3027 3027 + MODULE_LICENSE("GPL");

+9 -7

drivers/iio/adc/ad4851.c

reviewed

··· 294 294 } 295 295 296 296 static int ad4851_set_oversampling_ratio(struct iio_dev *indio_dev, 297 297 - const struct iio_chan_spec *chan, 298 297 unsigned int osr) 299 298 { 300 299 struct ad4851_state *st = iio_priv(indio_dev); ··· 320 321 return ret; 321 322 } 322 323 323 323 - ret = iio_backend_oversampling_ratio_set(st->back, osr); 324 324 + /* Channel is ignored by the backend being used here */ 325 325 + ret = iio_backend_oversampling_ratio_set(st->back, 0, osr); 324 326 if (ret) 325 327 return ret; 326 328 ··· 444 444 if (ret) 445 445 return ret; 446 446 447 447 - ret = regmap_write(st->regmap, AD4851_REG_INTERFACE_CONFIG_A, 448 448 - AD4851_SDO_ENABLE); 449 449 - if (ret) 450 450 - return ret; 447 447 + if (!(st->spi->mode & SPI_3WIRE)) { 448 448 + ret = regmap_write(st->regmap, AD4851_REG_INTERFACE_CONFIG_A, 449 449 + AD4851_SDO_ENABLE); 450 450 + if (ret) 451 451 + return ret; 452 452 + } 451 453 452 454 ret = regmap_read(st->regmap, AD4851_REG_PRODUCT_ID_L, &product_id); 453 455 if (ret) ··· 833 831 case IIO_CHAN_INFO_CALIBBIAS: 834 832 return ad4851_set_calibbias(st, chan->channel, val); 835 833 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 836 836 - return ad4851_set_oversampling_ratio(indio_dev, chan, val); 834 834 + return ad4851_set_oversampling_ratio(indio_dev, val); 837 835 default: 838 836 return -EINVAL; 839 837 }

+1 -1

drivers/iio/adc/ad7091r5.c

reviewed

··· 92 92 st->map = devm_regmap_init_i2c(i2c, regmap_conf); 93 93 } 94 94 95 95 - static struct ad7091r_init_info ad7091r5_init_info = { 95 95 + static const struct ad7091r_init_info ad7091r5_init_info = { 96 96 .info_irq = &ad7091r5_chip_info_irq, 97 97 .info_no_irq = &ad7091r5_chip_info_noirq, 98 98 .regmap_config = &ad7091r_regmap_config,

+3 -3

drivers/iio/adc/ad7091r8.c

reviewed

··· 206 206 return 0; 207 207 } 208 208 209 209 - static struct ad7091r_init_info ad7091r2_init_info = { 209 209 + static const struct ad7091r_init_info ad7091r2_init_info = { 210 210 .info_no_irq = &ad7091r8_infos[AD7091R2_INFO], 211 211 .regmap_config = &ad7091r2_reg_conf, 212 212 .init_adc_regmap = &ad7091r8_regmap_init, 213 213 .setup = &ad7091r8_gpio_setup 214 214 }; 215 215 216 216 - static struct ad7091r_init_info ad7091r4_init_info = { 216 216 + static const struct ad7091r_init_info ad7091r4_init_info = { 217 217 .info_no_irq = &ad7091r8_infos[AD7091R4_INFO], 218 218 .info_irq = &ad7091r8_infos[AD7091R4_INFO_IRQ], 219 219 .regmap_config = &ad7091r4_reg_conf, ··· 221 221 .setup = &ad7091r8_gpio_setup 222 222 }; 223 223 224 224 - static struct ad7091r_init_info ad7091r8_init_info = { 224 224 + static const struct ad7091r_init_info ad7091r8_init_info = { 225 225 .info_no_irq = &ad7091r8_infos[AD7091R8_INFO], 226 226 .info_irq = &ad7091r8_infos[AD7091R8_INFO_IRQ], 227 227 .regmap_config = &ad7091r8_reg_conf,

+14 -22

drivers/iio/adc/ad7124.c

reviewed

··· 94 94 95 95 /* AD7124 input sources */ 96 96 97 97 - enum ad7124_ids { 98 98 - ID_AD7124_4, 99 99 - ID_AD7124_8, 100 100 - }; 101 101 - 102 97 enum ad7124_ref_sel { 103 98 AD7124_REFIN1, 104 99 AD7124_REFIN2, ··· 188 193 DECLARE_KFIFO(live_cfgs_fifo, struct ad7124_channel_config *, AD7124_MAX_CONFIGS); 189 194 }; 190 195 191 191 - static struct ad7124_chip_info ad7124_chip_info_tbl[] = { 192 192 - [ID_AD7124_4] = { 193 193 - .name = "ad7124-4", 194 194 - .chip_id = AD7124_ID_DEVICE_ID_AD7124_4, 195 195 - .num_inputs = 8, 196 196 - }, 197 197 - [ID_AD7124_8] = { 198 198 - .name = "ad7124-8", 199 199 - .chip_id = AD7124_ID_DEVICE_ID_AD7124_8, 200 200 - .num_inputs = 16, 201 201 - }, 196 196 + static const struct ad7124_chip_info ad7124_4_chip_info = { 197 197 + .name = "ad7124-4", 198 198 + .chip_id = AD7124_ID_DEVICE_ID_AD7124_4, 199 199 + .num_inputs = 8, 200 200 + }; 201 201 + 202 202 + static const struct ad7124_chip_info ad7124_8_chip_info = { 203 203 + .name = "ad7124-8", 204 204 + .chip_id = AD7124_ID_DEVICE_ID_AD7124_8, 205 205 + .num_inputs = 16, 202 206 }; 203 207 204 208 static int ad7124_find_closest_match(const int *array, ··· 1335 1341 } 1336 1342 1337 1343 static const struct of_device_id ad7124_of_match[] = { 1338 1338 - { .compatible = "adi,ad7124-4", 1339 1339 - .data = &ad7124_chip_info_tbl[ID_AD7124_4], }, 1340 1340 - { .compatible = "adi,ad7124-8", 1341 1341 - .data = &ad7124_chip_info_tbl[ID_AD7124_8], }, 1344 1344 + { .compatible = "adi,ad7124-4", .data = &ad7124_4_chip_info }, 1345 1345 + { .compatible = "adi,ad7124-8", .data = &ad7124_8_chip_info }, 1342 1346 { } 1343 1347 }; 1344 1348 MODULE_DEVICE_TABLE(of, ad7124_of_match); 1345 1349 1346 1350 static const struct spi_device_id ad71124_ids[] = { 1347 1347 - { "ad7124-4", (kernel_ulong_t)&ad7124_chip_info_tbl[ID_AD7124_4] }, 1348 1348 - { "ad7124-8", (kernel_ulong_t)&ad7124_chip_info_tbl[ID_AD7124_8] }, 1351 1351 + { "ad7124-4", (kernel_ulong_t)&ad7124_4_chip_info }, 1352 1352 + { "ad7124-8", (kernel_ulong_t)&ad7124_8_chip_info }, 1349 1353 { } 1350 1354 }; 1351 1355 MODULE_DEVICE_TABLE(spi, ad71124_ids);

+41 -37

drivers/iio/adc/ad7173.c

reviewed

··· 228 228 struct ida cfg_slots_status; 229 229 unsigned long long config_usage_counter; 230 230 unsigned long long *config_cnts; 231 231 - struct clk *ext_clk; 232 231 struct clk_hw int_clk_hw; 233 232 struct regmap *reg_gpiocon_regmap; 234 233 struct gpio_regmap *gpio_regmap; ··· 318 319 { 319 320 struct ad7173_state *st = iio_priv(indio_dev); 320 321 321 321 - st->channels[chan->channel].syscalib_mode = mode; 322 322 + st->channels[chan->address].syscalib_mode = mode; 322 323 323 324 return 0; 324 325 } ··· 328 329 { 329 330 struct ad7173_state *st = iio_priv(indio_dev); 330 331 331 331 - return st->channels[chan->channel].syscalib_mode; 332 332 + return st->channels[chan->address].syscalib_mode; 332 333 } 333 334 334 335 static ssize_t ad7173_write_syscalib(struct iio_dev *indio_dev, ··· 347 348 if (!iio_device_claim_direct(indio_dev)) 348 349 return -EBUSY; 349 350 350 350 - mode = st->channels[chan->channel].syscalib_mode; 351 351 + mode = st->channels[chan->address].syscalib_mode; 351 352 if (sys_calib) { 352 353 if (mode == AD7173_SYSCALIB_ZERO_SCALE) 353 354 ret = ad_sd_calibrate(&st->sd, AD7173_MODE_CAL_SYS_ZERO, ··· 391 392 if (indio_dev->channels[i].type != IIO_VOLTAGE) 392 393 continue; 393 394 394 394 - ret = ad_sd_calibrate(&st->sd, AD7173_MODE_CAL_INT_ZERO, st->channels[i].ain); 395 395 + ret = ad_sd_calibrate(&st->sd, AD7173_MODE_CAL_INT_ZERO, i); 395 396 if (ret < 0) 396 397 return ret; 397 398 398 399 if (st->info->has_internal_fs_calibration) { 399 399 - ret = ad_sd_calibrate(&st->sd, AD7173_MODE_CAL_INT_FULL, 400 400 - st->channels[i].ain); 400 400 + ret = ad_sd_calibrate(&st->sd, AD7173_MODE_CAL_INT_FULL, i); 401 401 if (ret < 0) 402 402 return ret; 403 403 } ··· 770 772 .num_slots = 8, 771 773 }; 772 774 775 775 + static const struct ad_sigma_delta_info ad7173_sigma_delta_info_16_slots = { 776 776 + .set_channel = ad7173_set_channel, 777 777 + .append_status = ad7173_append_status, 778 778 + .disable_all = ad7173_disable_all, 779 779 + .disable_one = ad7173_disable_one, 780 780 + .set_mode = ad7173_set_mode, 781 781 + .has_registers = true, 782 782 + .has_named_irqs = true, 783 783 + .addr_shift = 0, 784 784 + .read_mask = BIT(6), 785 785 + .status_ch_mask = GENMASK(3, 0), 786 786 + .data_reg = AD7173_REG_DATA, 787 787 + .num_resetclks = 64, 788 788 + .num_slots = 16, 789 789 + }; 790 790 + 773 791 static const struct ad7173_device_info ad4111_device_info = { 774 792 .name = "ad4111", 775 793 .id = AD4111_ID, 776 776 - .sd_info = &ad7173_sigma_delta_info_8_slots, 794 794 + .sd_info = &ad7173_sigma_delta_info_16_slots, 777 795 .num_voltage_in_div = 8, 778 796 .num_channels = 16, 779 797 .num_configs = 8, ··· 811 797 static const struct ad7173_device_info ad4112_device_info = { 812 798 .name = "ad4112", 813 799 .id = AD4112_ID, 814 814 - .sd_info = &ad7173_sigma_delta_info_8_slots, 800 800 + .sd_info = &ad7173_sigma_delta_info_16_slots, 815 801 .num_voltage_in_div = 8, 816 802 .num_channels = 16, 817 803 .num_configs = 8, ··· 832 818 static const struct ad7173_device_info ad4113_device_info = { 833 819 .name = "ad4113", 834 820 .id = AD4113_ID, 835 835 - .sd_info = &ad7173_sigma_delta_info_8_slots, 821 821 + .sd_info = &ad7173_sigma_delta_info_16_slots, 836 822 .num_voltage_in_div = 8, 837 823 .num_channels = 16, 838 824 .num_configs = 8, ··· 851 837 static const struct ad7173_device_info ad4114_device_info = { 852 838 .name = "ad4114", 853 839 .id = AD4114_ID, 854 854 - .sd_info = &ad7173_sigma_delta_info_8_slots, 840 840 + .sd_info = &ad7173_sigma_delta_info_16_slots, 855 841 .num_voltage_in_div = 16, 856 842 .num_channels = 16, 857 843 .num_configs = 8, ··· 870 856 static const struct ad7173_device_info ad4115_device_info = { 871 857 .name = "ad4115", 872 858 .id = AD4115_ID, 873 873 - .sd_info = &ad7173_sigma_delta_info_8_slots, 859 859 + .sd_info = &ad7173_sigma_delta_info_16_slots, 874 860 .num_voltage_in_div = 16, 875 861 .num_channels = 16, 876 862 .num_configs = 8, ··· 889 875 static const struct ad7173_device_info ad4116_device_info = { 890 876 .name = "ad4116", 891 877 .id = AD4116_ID, 892 892 - .sd_info = &ad7173_sigma_delta_info_8_slots, 878 878 + .sd_info = &ad7173_sigma_delta_info_16_slots, 893 879 .num_voltage_in_div = 11, 894 880 .num_channels = 16, 895 881 .num_configs = 8, ··· 908 894 static const struct ad7173_device_info ad7172_2_device_info = { 909 895 .name = "ad7172-2", 910 896 .id = AD7172_2_ID, 911 911 - .sd_info = &ad7173_sigma_delta_info_8_slots, 897 897 + .sd_info = &ad7173_sigma_delta_info_4_slots, 912 898 .num_voltage_in = 5, 913 899 .num_channels = 4, 914 900 .num_configs = 4, ··· 941 927 static const struct ad7173_device_info ad7173_8_device_info = { 942 928 .name = "ad7173-8", 943 929 .id = AD7173_ID, 944 944 - .sd_info = &ad7173_sigma_delta_info_8_slots, 930 930 + .sd_info = &ad7173_sigma_delta_info_16_slots, 945 931 .num_voltage_in = 17, 946 932 .num_channels = 16, 947 933 .num_configs = 8, ··· 958 944 static const struct ad7173_device_info ad7175_2_device_info = { 959 945 .name = "ad7175-2", 960 946 .id = AD7175_2_ID, 961 961 - .sd_info = &ad7173_sigma_delta_info_8_slots, 947 947 + .sd_info = &ad7173_sigma_delta_info_4_slots, 962 948 .num_voltage_in = 5, 963 949 .num_channels = 4, 964 950 .num_configs = 4, ··· 975 961 static const struct ad7173_device_info ad7175_8_device_info = { 976 962 .name = "ad7175-8", 977 963 .id = AD7175_8_ID, 978 978 - .sd_info = &ad7173_sigma_delta_info_8_slots, 964 964 + .sd_info = &ad7173_sigma_delta_info_16_slots, 979 965 .num_voltage_in = 17, 980 966 .num_channels = 16, 981 967 .num_configs = 8, ··· 1358 1344 regulator_bulk_disable(ARRAY_SIZE(st->regulators), st->regulators); 1359 1345 } 1360 1346 1361 1361 - static void ad7173_clk_disable_unprepare(void *clk) 1362 1362 - { 1363 1363 - clk_disable_unprepare(clk); 1364 1364 - } 1365 1365 - 1366 1347 static unsigned long ad7173_sel_clk(struct ad7173_state *st, 1367 1348 unsigned int clk_sel) 1368 1349 { ··· 1589 1580 chan_st_priv->cfg.bipolar = false; 1590 1581 chan_st_priv->cfg.input_buf = st->info->has_input_buf; 1591 1582 chan_st_priv->cfg.ref_sel = AD7173_SETUP_REF_SEL_INT_REF; 1583 1583 + chan_st_priv->cfg.odr = st->info->odr_start_value; 1592 1584 chan_st_priv->cfg.openwire_comp_chan = -1; 1593 1585 st->adc_mode |= AD7173_ADC_MODE_REF_EN; 1594 1586 if (st->info->data_reg_only_16bit) ··· 1656 1646 chan->scan_index = chan_index; 1657 1647 chan->channel = ain[0]; 1658 1648 chan_st_priv->cfg.input_buf = st->info->has_input_buf; 1659 1659 - chan_st_priv->cfg.odr = 0; 1649 1649 + chan_st_priv->cfg.odr = st->info->odr_start_value; 1660 1650 chan_st_priv->cfg.openwire_comp_chan = -1; 1661 1651 1662 1652 chan_st_priv->cfg.bipolar = fwnode_property_read_bool(child, "bipolar"); ··· 1728 1718 AD7173_ADC_MODE_CLOCKSEL_INT); 1729 1719 ad7173_register_clk_provider(indio_dev); 1730 1720 } else { 1721 1721 + struct clk *clk; 1722 1722 + 1731 1723 st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_CLOCKSEL_MASK, 1732 1724 AD7173_ADC_MODE_CLOCKSEL_EXT + ret); 1733 1733 - st->ext_clk = devm_clk_get(dev, ad7173_clk_sel[ret]); 1734 1734 - if (IS_ERR(st->ext_clk)) 1735 1735 - return dev_err_probe(dev, PTR_ERR(st->ext_clk), 1725 1725 + clk = devm_clk_get_enabled(dev, ad7173_clk_sel[ret]); 1726 1726 + if (IS_ERR(clk)) 1727 1727 + return dev_err_probe(dev, PTR_ERR(clk), 1736 1728 "Failed to get external clock\n"); 1737 1737 - 1738 1738 - ret = clk_prepare_enable(st->ext_clk); 1739 1739 - if (ret) 1740 1740 - return dev_err_probe(dev, ret, 1741 1741 - "Failed to enable external clock\n"); 1742 1742 - 1743 1743 - ret = devm_add_action_or_reset(dev, ad7173_clk_disable_unprepare, 1744 1744 - st->ext_clk); 1745 1745 - if (ret) 1746 1746 - return ret; 1747 1729 } 1748 1730 1749 1731 return ad7173_fw_parse_channel_config(indio_dev); ··· 1767 1765 indio_dev->info = &ad7173_info; 1768 1766 1769 1767 spi->mode = SPI_MODE_3; 1770 1770 - spi_setup(spi); 1768 1768 + ret = spi_setup(spi); 1769 1769 + if (ret) 1770 1770 + return ret; 1771 1771 1772 1772 ret = ad_sd_init(&st->sd, indio_dev, spi, st->info->sd_info); 1773 1773 if (ret)

-5

drivers/iio/adc/ad7380.c

reviewed

··· 1165 1165 struct spi_transfer *xfer = &st->offload_xfer; 1166 1166 struct device *dev = &st->spi->dev; 1167 1167 const struct iio_scan_type *scan_type; 1168 1168 - int oversampling_ratio; 1169 1168 int ret; 1170 1169 1171 1170 scan_type = iio_get_current_scan_type(indio_dev, ··· 1193 1194 return ret; 1194 1195 } 1195 1196 } 1196 1196 - 1197 1197 - ret = ad7380_get_osr(st, &oversampling_ratio); 1198 1198 - if (ret) 1199 1199 - return ret; 1200 1197 1201 1198 xfer->bits_per_word = scan_type->realbits; 1202 1199 xfer->offload_flags = SPI_OFFLOAD_XFER_RX_STREAM;

+253

drivers/iio/adc/ad7405.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0-only 2 2 + /* 3 3 + * Analog Devices AD7405 driver 4 4 + * 5 5 + * Copyright 2025 Analog Devices Inc. 6 6 + */ 7 7 + 8 8 + #include <linux/clk.h> 9 9 + #include <linux/device.h> 10 10 + #include <linux/err.h> 11 11 + #include <linux/math64.h> 12 12 + #include <linux/module.h> 13 13 + #include <linux/mod_devicetable.h> 14 14 + #include <linux/platform_device.h> 15 15 + #include <linux/property.h> 16 16 + #include <linux/regulator/consumer.h> 17 17 + #include <linux/util_macros.h> 18 18 + 19 19 + #include <linux/iio/backend.h> 20 20 + #include <linux/iio/iio.h> 21 21 + 22 22 + static const unsigned int ad7405_dec_rates_range[] = { 23 23 + 32, 1, 4096, 24 24 + }; 25 25 + 26 26 + struct ad7405_chip_info { 27 27 + const char *name; 28 28 + const unsigned int full_scale_mv; 29 29 + }; 30 30 + 31 31 + struct ad7405_state { 32 32 + struct iio_backend *back; 33 33 + const struct ad7405_chip_info *info; 34 34 + unsigned int ref_frequency; 35 35 + unsigned int dec_rate; 36 36 + }; 37 37 + 38 38 + static int ad7405_set_dec_rate(struct iio_dev *indio_dev, 39 39 + const struct iio_chan_spec *chan, 40 40 + unsigned int dec_rate) 41 41 + { 42 42 + struct ad7405_state *st = iio_priv(indio_dev); 43 43 + int ret; 44 44 + 45 45 + if (dec_rate > 4096 || dec_rate < 32) 46 46 + return -EINVAL; 47 47 + 48 48 + if (!iio_device_claim_direct(indio_dev)) 49 49 + return -EBUSY; 50 50 + 51 51 + ret = iio_backend_oversampling_ratio_set(st->back, chan->scan_index, dec_rate); 52 52 + iio_device_release_direct(indio_dev); 53 53 + 54 54 + if (ret < 0) 55 55 + return ret; 56 56 + 57 57 + st->dec_rate = dec_rate; 58 58 + 59 59 + return 0; 60 60 + } 61 61 + 62 62 + static int ad7405_read_raw(struct iio_dev *indio_dev, 63 63 + const struct iio_chan_spec *chan, int *val, 64 64 + int *val2, long info) 65 65 + { 66 66 + struct ad7405_state *st = iio_priv(indio_dev); 67 67 + 68 68 + switch (info) { 69 69 + case IIO_CHAN_INFO_SCALE: 70 70 + *val = st->info->full_scale_mv; 71 71 + *val2 = indio_dev->channels[0].scan_type.realbits - 1; 72 72 + return IIO_VAL_FRACTIONAL_LOG2; 73 73 + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 74 74 + *val = st->dec_rate; 75 75 + return IIO_VAL_INT; 76 76 + case IIO_CHAN_INFO_SAMP_FREQ: 77 77 + *val = DIV_ROUND_CLOSEST_ULL(st->ref_frequency, st->dec_rate); 78 78 + return IIO_VAL_INT; 79 79 + case IIO_CHAN_INFO_OFFSET: 80 80 + *val = -(1 << (indio_dev->channels[0].scan_type.realbits - 1)); 81 81 + return IIO_VAL_INT; 82 82 + default: 83 83 + return -EINVAL; 84 84 + } 85 85 + } 86 86 + 87 87 + static int ad7405_write_raw(struct iio_dev *indio_dev, 88 88 + struct iio_chan_spec const *chan, int val, 89 89 + int val2, long info) 90 90 + { 91 91 + switch (info) { 92 92 + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 93 93 + if (val < 0) 94 94 + return -EINVAL; 95 95 + return ad7405_set_dec_rate(indio_dev, chan, val); 96 96 + default: 97 97 + return -EINVAL; 98 98 + } 99 99 + } 100 100 + 101 101 + static int ad7405_read_avail(struct iio_dev *indio_dev, 102 102 + struct iio_chan_spec const *chan, 103 103 + const int **vals, int *type, int *length, 104 104 + long info) 105 105 + { 106 106 + switch (info) { 107 107 + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 108 108 + *vals = ad7405_dec_rates_range; 109 109 + *type = IIO_VAL_INT; 110 110 + return IIO_AVAIL_RANGE; 111 111 + default: 112 112 + return -EINVAL; 113 113 + } 114 114 + } 115 115 + 116 116 + static const struct iio_info ad7405_iio_info = { 117 117 + .read_raw = &ad7405_read_raw, 118 118 + .write_raw = &ad7405_write_raw, 119 119 + .read_avail = &ad7405_read_avail, 120 120 + }; 121 121 + 122 122 + static const struct iio_chan_spec ad7405_channel = { 123 123 + .type = IIO_VOLTAGE, 124 124 + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | 125 125 + BIT(IIO_CHAN_INFO_OFFSET), 126 126 + .info_mask_shared_by_all = IIO_CHAN_INFO_SAMP_FREQ | 127 127 + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), 128 128 + .info_mask_shared_by_all_available = 129 129 + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), 130 130 + .indexed = 1, 131 131 + .channel = 0, 132 132 + .channel2 = 1, 133 133 + .differential = 1, 134 134 + .scan_index = 0, 135 135 + .scan_type = { 136 136 + .sign = 'u', 137 137 + .realbits = 16, 138 138 + .storagebits = 16, 139 139 + }, 140 140 + }; 141 141 + 142 142 + static const struct ad7405_chip_info ad7405_chip_info = { 143 143 + .name = "ad7405", 144 144 + .full_scale_mv = 320, 145 145 + }; 146 146 + 147 147 + static const struct ad7405_chip_info adum7701_chip_info = { 148 148 + .name = "adum7701", 149 149 + .full_scale_mv = 320, 150 150 + }; 151 151 + 152 152 + static const struct ad7405_chip_info adum7702_chip_info = { 153 153 + .name = "adum7702", 154 154 + .full_scale_mv = 64, 155 155 + }; 156 156 + 157 157 + static const struct ad7405_chip_info adum7703_chip_info = { 158 158 + .name = "adum7703", 159 159 + .full_scale_mv = 320, 160 160 + }; 161 161 + 162 162 + static const char * const ad7405_power_supplies[] = { 163 163 + "vdd1", "vdd2", 164 164 + }; 165 165 + 166 166 + static int ad7405_probe(struct platform_device *pdev) 167 167 + { 168 168 + struct device *dev = &pdev->dev; 169 169 + struct iio_dev *indio_dev; 170 170 + struct ad7405_state *st; 171 171 + struct clk *clk; 172 172 + int ret; 173 173 + 174 174 + indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 175 175 + if (!indio_dev) 176 176 + return -ENOMEM; 177 177 + 178 178 + st = iio_priv(indio_dev); 179 179 + 180 180 + st->info = device_get_match_data(dev); 181 181 + if (!st->info) 182 182 + return dev_err_probe(dev, -EINVAL, "no chip info\n"); 183 183 + 184 184 + ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(ad7405_power_supplies), 185 185 + ad7405_power_supplies); 186 186 + if (ret) 187 187 + return dev_err_probe(dev, ret, "failed to get and enable supplies"); 188 188 + 189 189 + clk = devm_clk_get_enabled(dev, NULL); 190 190 + if (IS_ERR(clk)) 191 191 + return PTR_ERR(clk); 192 192 + 193 193 + st->ref_frequency = clk_get_rate(clk); 194 194 + if (!st->ref_frequency) 195 195 + return -EINVAL; 196 196 + 197 197 + indio_dev->name = st->info->name; 198 198 + indio_dev->channels = &ad7405_channel; 199 199 + indio_dev->num_channels = 1; 200 200 + indio_dev->info = &ad7405_iio_info; 201 201 + 202 202 + st->back = devm_iio_backend_get(dev, NULL); 203 203 + if (IS_ERR(st->back)) 204 204 + return dev_err_probe(dev, PTR_ERR(st->back), 205 205 + "failed to get IIO backend"); 206 206 + 207 207 + ret = iio_backend_chan_enable(st->back, 0); 208 208 + if (ret) 209 209 + return ret; 210 210 + 211 211 + ret = devm_iio_backend_request_buffer(dev, st->back, indio_dev); 212 212 + if (ret) 213 213 + return ret; 214 214 + 215 215 + ret = devm_iio_backend_enable(dev, st->back); 216 216 + if (ret) 217 217 + return ret; 218 218 + 219 219 + /* 220 220 + * Set 256 decimation rate. The default value in the AXI_ADC register 221 221 + * is 0, so we set the register with a decimation rate value that is 222 222 + * functional for all parts. 223 223 + */ 224 224 + ret = ad7405_set_dec_rate(indio_dev, &indio_dev->channels[0], 256); 225 225 + if (ret) 226 226 + return ret; 227 227 + 228 228 + return devm_iio_device_register(dev, indio_dev); 229 229 + } 230 230 + 231 231 + static const struct of_device_id ad7405_of_match[] = { 232 232 + { .compatible = "adi,ad7405", .data = &ad7405_chip_info, }, 233 233 + { .compatible = "adi,adum7701", .data = &adum7701_chip_info, }, 234 234 + { .compatible = "adi,adum7702", .data = &adum7702_chip_info, }, 235 235 + { .compatible = "adi,adum7703", .data = &adum7703_chip_info, }, 236 236 + { } 237 237 + }; 238 238 + MODULE_DEVICE_TABLE(of, ad7405_of_match); 239 239 + 240 240 + static struct platform_driver ad7405_driver = { 241 241 + .driver = { 242 242 + .name = "ad7405", 243 243 + .of_match_table = ad7405_of_match, 244 244 + }, 245 245 + .probe = ad7405_probe, 246 246 + }; 247 247 + module_platform_driver(ad7405_driver); 248 248 + 249 249 + MODULE_AUTHOR("Dragos Bogdan <dragos.bogdan@analog.com>"); 250 250 + MODULE_AUTHOR("Pop Ioan Daniel <pop.ioan-daniel@analog.com>"); 251 251 + MODULE_DESCRIPTION("Analog Devices AD7405 driver"); 252 252 + MODULE_LICENSE("GPL"); 253 253 + MODULE_IMPORT_NS("IIO_BACKEND");

+7

drivers/iio/adc/ad7476.c

reviewed

··· 435 435 { "ads7866", ID_ADS7866 }, 436 436 { "ads7867", ID_ADS7867 }, 437 437 { "ads7868", ID_ADS7868 }, 438 438 + /* 439 439 + * The ROHM BU79100G is identical to the TI's ADS7866 from the software 440 440 + * point of view. The binding document mandates the ADS7866 to be 441 441 + * marked as a fallback for the BU79100G, but we still need the SPI ID 442 442 + * here to make the module loading work. 443 443 + */ 444 444 + { "bu79100g", ID_ADS7866 }, 438 445 { "ltc2314-14", ID_LTC2314_14 }, 439 446 { } 440 447 };

+284 -77

drivers/iio/adc/ad7606.c

reviewed

··· 33 33 34 34 #include "ad7606.h" 35 35 36 36 + #define AD7606_CALIB_GAIN_MIN 0 37 37 + #define AD7606_CALIB_GAIN_STEP 1024 38 38 + #define AD7606_CALIB_GAIN_MAX (63 * AD7606_CALIB_GAIN_STEP) 39 39 + 36 40 /* 37 41 * Scales are computed as 5000/32768 and 10000/32768 respectively, 38 42 * so that when applied to the raw values they provide mV values. ··· 97 93 98 94 static const unsigned int ad7616_oversampling_avail[8] = { 99 95 1, 2, 4, 8, 16, 32, 64, 128, 96 96 + }; 97 97 + 98 98 + static const int ad7606_calib_offset_avail[3] = { 99 99 + -128, 1, 127, 100 100 + }; 101 101 + 102 102 + static const int ad7606c_18bit_calib_offset_avail[3] = { 103 103 + -512, 4, 508, 104 104 + }; 105 105 + 106 106 + static const int ad7606b_calib_phase_avail[][2] = { 107 107 + { 0, 0 }, { 0, 1250 }, { 0, 318750 }, 108 108 + }; 109 109 + 110 110 + static const int ad7606c_calib_phase_avail[][2] = { 111 111 + { 0, 0 }, { 0, 1000 }, { 0, 255000 }, 100 112 }; 101 113 102 114 static int ad7606c_18bit_chan_scale_setup(struct iio_dev *indio_dev, ··· 184 164 .scale_setup_cb = ad7606_16bit_chan_scale_setup, 185 165 .sw_setup_cb = ad7606b_sw_mode_setup, 186 166 .offload_storagebits = 32, 167 167 + .calib_gain_avail = true, 168 168 + .calib_offset_avail = ad7606_calib_offset_avail, 169 169 + .calib_phase_avail = ad7606b_calib_phase_avail, 187 170 }; 188 171 EXPORT_SYMBOL_NS_GPL(ad7606b_info, "IIO_AD7606"); 189 172 ··· 200 177 .scale_setup_cb = ad7606c_16bit_chan_scale_setup, 201 178 .sw_setup_cb = ad7606b_sw_mode_setup, 202 179 .offload_storagebits = 32, 180 180 + .calib_gain_avail = true, 181 181 + .calib_offset_avail = ad7606_calib_offset_avail, 182 182 + .calib_phase_avail = ad7606c_calib_phase_avail, 203 183 }; 204 184 EXPORT_SYMBOL_NS_GPL(ad7606c_16_info, "IIO_AD7606"); 205 185 ··· 252 226 .scale_setup_cb = ad7606c_18bit_chan_scale_setup, 253 227 .sw_setup_cb = ad7606b_sw_mode_setup, 254 228 .offload_storagebits = 32, 229 229 + .calib_gain_avail = true, 230 230 + .calib_offset_avail = ad7606c_18bit_calib_offset_avail, 231 231 + .calib_phase_avail = ad7606c_calib_phase_avail, 255 232 }; 256 233 EXPORT_SYMBOL_NS_GPL(ad7606c_18_info, "IIO_AD7606"); 257 234 ··· 290 261 struct iio_chan_spec *chan) 291 262 { 292 263 struct ad7606_state *st = iio_priv(indio_dev); 293 293 - struct ad7606_chan_scale *cs = &st->chan_scales[chan->scan_index]; 264 264 + struct ad7606_chan_info *ci = &st->chan_info[chan->scan_index]; 294 265 295 266 if (!st->sw_mode_en) { 296 267 /* tied to logic low, analog input range is +/- 5V */ 297 297 - cs->range = 0; 298 298 - cs->scale_avail = ad7606_16bit_hw_scale_avail; 299 299 - cs->num_scales = ARRAY_SIZE(ad7606_16bit_hw_scale_avail); 268 268 + ci->range = 0; 269 269 + ci->scale_avail = ad7606_16bit_hw_scale_avail; 270 270 + ci->num_scales = ARRAY_SIZE(ad7606_16bit_hw_scale_avail); 300 271 return 0; 301 272 } 302 273 303 274 /* Scale of 0.076293 is only available in sw mode */ 304 275 /* After reset, in software mode, ±10 V is set by default */ 305 305 - cs->range = 2; 306 306 - cs->scale_avail = ad7606_16bit_sw_scale_avail; 307 307 - cs->num_scales = ARRAY_SIZE(ad7606_16bit_sw_scale_avail); 276 276 + ci->range = 2; 277 277 + ci->scale_avail = ad7606_16bit_sw_scale_avail; 278 278 + ci->num_scales = ARRAY_SIZE(ad7606_16bit_sw_scale_avail); 308 279 309 280 return 0; 310 281 } ··· 313 284 bool *bipolar, bool *differential) 314 285 { 315 286 struct ad7606_state *st = iio_priv(indio_dev); 287 287 + struct ad7606_chan_info *ci; 316 288 unsigned int num_channels = st->chip_info->num_adc_channels; 317 289 struct device *dev = st->dev; 318 290 int ret; ··· 327 297 328 298 ret = fwnode_property_read_u32(child, "reg", &reg); 329 299 if (ret) 330 330 - continue; 300 300 + return ret; 331 301 332 302 /* channel number (here) is from 1 to num_channels */ 333 333 - if (reg < 1 || reg > num_channels) { 334 334 - dev_warn(dev, 335 335 - "Invalid channel number (ignoring): %d\n", reg); 336 336 - continue; 337 337 - } 303 303 + if (reg < 1 || reg > num_channels) 304 304 + return -EINVAL; 338 305 306 306 + /* Loop until we are in the right channel. */ 339 307 if (reg != (ch + 1)) 340 308 continue; 341 309 ··· 357 329 return -EINVAL; 358 330 } 359 331 332 332 + ci = &st->chan_info[reg - 1]; 333 333 + 334 334 + ci->r_gain = 0; 335 335 + ret = fwnode_property_read_u32(child, "adi,rfilter-ohms", 336 336 + &ci->r_gain); 337 337 + if (ret == 0 && ci->r_gain > AD7606_CALIB_GAIN_MAX) 338 338 + return -EINVAL; 339 339 + 360 340 return 0; 361 341 } 362 342 ··· 375 339 struct iio_chan_spec *chan) 376 340 { 377 341 struct ad7606_state *st = iio_priv(indio_dev); 378 378 - struct ad7606_chan_scale *cs = &st->chan_scales[chan->scan_index]; 342 342 + struct ad7606_chan_info *ci = &st->chan_info[chan->scan_index]; 379 343 bool bipolar, differential; 380 344 int ret; 381 345 382 346 if (!st->sw_mode_en) { 383 383 - cs->range = 0; 384 384 - cs->scale_avail = ad7606_18bit_hw_scale_avail; 385 385 - cs->num_scales = ARRAY_SIZE(ad7606_18bit_hw_scale_avail); 347 347 + ci->range = 0; 348 348 + ci->scale_avail = ad7606_18bit_hw_scale_avail; 349 349 + ci->num_scales = ARRAY_SIZE(ad7606_18bit_hw_scale_avail); 386 350 return 0; 387 351 } 388 352 ··· 392 356 return ret; 393 357 394 358 if (differential) { 395 395 - cs->scale_avail = ad7606c_18bit_differential_bipolar_scale_avail; 396 396 - cs->num_scales = 359 359 + ci->scale_avail = ad7606c_18bit_differential_bipolar_scale_avail; 360 360 + ci->num_scales = 397 361 ARRAY_SIZE(ad7606c_18bit_differential_bipolar_scale_avail); 398 362 /* Bipolar differential ranges start at 8 (b1000) */ 399 399 - cs->reg_offset = 8; 400 400 - cs->range = 1; 363 363 + ci->reg_offset = 8; 364 364 + ci->range = 1; 401 365 chan->differential = 1; 402 366 chan->channel2 = chan->channel; 403 367 ··· 407 371 chan->differential = 0; 408 372 409 373 if (bipolar) { 410 410 - cs->scale_avail = ad7606c_18bit_single_ended_bipolar_scale_avail; 411 411 - cs->num_scales = 374 374 + ci->scale_avail = ad7606c_18bit_single_ended_bipolar_scale_avail; 375 375 + ci->num_scales = 412 376 ARRAY_SIZE(ad7606c_18bit_single_ended_bipolar_scale_avail); 413 377 /* Bipolar single-ended ranges start at 0 (b0000) */ 414 414 - cs->reg_offset = 0; 415 415 - cs->range = 3; 378 378 + ci->reg_offset = 0; 379 379 + ci->range = 3; 416 380 chan->scan_type.sign = 's'; 417 381 418 382 return 0; 419 383 } 420 384 421 421 - cs->scale_avail = ad7606c_18bit_single_ended_unipolar_scale_avail; 422 422 - cs->num_scales = 385 385 + ci->scale_avail = ad7606c_18bit_single_ended_unipolar_scale_avail; 386 386 + ci->num_scales = 423 387 ARRAY_SIZE(ad7606c_18bit_single_ended_unipolar_scale_avail); 424 388 /* Unipolar single-ended ranges start at 5 (b0101) */ 425 425 - cs->reg_offset = 5; 426 426 - cs->range = 1; 389 389 + ci->reg_offset = 5; 390 390 + ci->range = 1; 427 391 chan->scan_type.sign = 'u'; 428 392 429 393 return 0; ··· 433 397 struct iio_chan_spec *chan) 434 398 { 435 399 struct ad7606_state *st = iio_priv(indio_dev); 436 436 - struct ad7606_chan_scale *cs = &st->chan_scales[chan->scan_index]; 400 400 + struct ad7606_chan_info *ci = &st->chan_info[chan->scan_index]; 437 401 bool bipolar, differential; 438 402 int ret; 439 403 440 404 if (!st->sw_mode_en) { 441 441 - cs->range = 0; 442 442 - cs->scale_avail = ad7606_16bit_hw_scale_avail; 443 443 - cs->num_scales = ARRAY_SIZE(ad7606_16bit_hw_scale_avail); 405 405 + ci->range = 0; 406 406 + ci->scale_avail = ad7606_16bit_hw_scale_avail; 407 407 + ci->num_scales = ARRAY_SIZE(ad7606_16bit_hw_scale_avail); 444 408 return 0; 445 409 } 446 410 ··· 450 414 return ret; 451 415 452 416 if (differential) { 453 453 - cs->scale_avail = ad7606c_16bit_differential_bipolar_scale_avail; 454 454 - cs->num_scales = 417 417 + ci->scale_avail = ad7606c_16bit_differential_bipolar_scale_avail; 418 418 + ci->num_scales = 455 419 ARRAY_SIZE(ad7606c_16bit_differential_bipolar_scale_avail); 456 420 /* Bipolar differential ranges start at 8 (b1000) */ 457 457 - cs->reg_offset = 8; 458 458 - cs->range = 1; 421 421 + ci->reg_offset = 8; 422 422 + ci->range = 1; 459 423 chan->differential = 1; 460 424 chan->channel2 = chan->channel; 461 425 chan->scan_type.sign = 's'; ··· 466 430 chan->differential = 0; 467 431 468 432 if (bipolar) { 469 469 - cs->scale_avail = ad7606c_16bit_single_ended_bipolar_scale_avail; 470 470 - cs->num_scales = 433 433 + ci->scale_avail = ad7606c_16bit_single_ended_bipolar_scale_avail; 434 434 + ci->num_scales = 471 435 ARRAY_SIZE(ad7606c_16bit_single_ended_bipolar_scale_avail); 472 436 /* Bipolar single-ended ranges start at 0 (b0000) */ 473 473 - cs->reg_offset = 0; 474 474 - cs->range = 3; 437 437 + ci->reg_offset = 0; 438 438 + ci->range = 3; 475 439 chan->scan_type.sign = 's'; 476 440 477 441 return 0; 478 442 } 479 443 480 480 - cs->scale_avail = ad7606c_16bit_single_ended_unipolar_scale_avail; 481 481 - cs->num_scales = 444 444 + ci->scale_avail = ad7606c_16bit_single_ended_unipolar_scale_avail; 445 445 + ci->num_scales = 482 446 ARRAY_SIZE(ad7606c_16bit_single_ended_unipolar_scale_avail); 483 447 /* Unipolar single-ended ranges start at 5 (b0101) */ 484 484 - cs->reg_offset = 5; 485 485 - cs->range = 1; 448 448 + ci->reg_offset = 5; 449 449 + ci->range = 1; 486 450 chan->scan_type.sign = 'u'; 487 451 488 452 return 0; ··· 492 456 struct iio_chan_spec *chan) 493 457 { 494 458 struct ad7606_state *st = iio_priv(indio_dev); 495 495 - struct ad7606_chan_scale *cs = &st->chan_scales[chan->scan_index]; 459 459 + struct ad7606_chan_info *ci = &st->chan_info[chan->scan_index]; 496 460 497 497 - cs->range = 0; 498 498 - cs->scale_avail = ad7607_hw_scale_avail; 499 499 - cs->num_scales = ARRAY_SIZE(ad7607_hw_scale_avail); 461 461 + ci->range = 0; 462 462 + ci->scale_avail = ad7607_hw_scale_avail; 463 463 + ci->num_scales = ARRAY_SIZE(ad7607_hw_scale_avail); 500 464 return 0; 501 465 } 502 466 ··· 504 468 struct iio_chan_spec *chan) 505 469 { 506 470 struct ad7606_state *st = iio_priv(indio_dev); 507 507 - struct ad7606_chan_scale *cs = &st->chan_scales[chan->scan_index]; 471 471 + struct ad7606_chan_info *ci = &st->chan_info[chan->scan_index]; 508 472 509 509 - cs->range = 0; 510 510 - cs->scale_avail = ad7606_18bit_hw_scale_avail; 511 511 - cs->num_scales = ARRAY_SIZE(ad7606_18bit_hw_scale_avail); 473 473 + ci->range = 0; 474 474 + ci->scale_avail = ad7606_18bit_hw_scale_avail; 475 475 + ci->num_scales = ARRAY_SIZE(ad7606_18bit_hw_scale_avail); 512 476 return 0; 513 477 } 514 478 ··· 516 480 struct iio_chan_spec *chan) 517 481 { 518 482 struct ad7606_state *st = iio_priv(indio_dev); 519 519 - struct ad7606_chan_scale *cs = &st->chan_scales[chan->scan_index]; 483 483 + struct ad7606_chan_info *ci = &st->chan_info[chan->scan_index]; 520 484 521 521 - cs->range = 0; 522 522 - cs->scale_avail = ad7609_hw_scale_avail; 523 523 - cs->num_scales = ARRAY_SIZE(ad7609_hw_scale_avail); 485 485 + ci->range = 0; 486 486 + ci->scale_avail = ad7609_hw_scale_avail; 487 487 + ci->num_scales = ARRAY_SIZE(ad7609_hw_scale_avail); 524 488 return 0; 525 489 } 526 490 ··· 717 681 return ret; 718 682 } 719 683 684 684 + static int ad7606_get_calib_offset(struct ad7606_state *st, int ch, int *val) 685 685 + { 686 686 + int ret; 687 687 + 688 688 + ret = st->bops->reg_read(st, AD7606_CALIB_OFFSET(ch)); 689 689 + if (ret < 0) 690 690 + return ret; 691 691 + 692 692 + *val = st->chip_info->calib_offset_avail[0] + 693 693 + ret * st->chip_info->calib_offset_avail[1]; 694 694 + 695 695 + return 0; 696 696 + } 697 697 + 698 698 + static int ad7606_get_calib_phase(struct ad7606_state *st, int ch, int *val, 699 699 + int *val2) 700 700 + { 701 701 + int ret; 702 702 + 703 703 + ret = st->bops->reg_read(st, AD7606_CALIB_PHASE(ch)); 704 704 + if (ret < 0) 705 705 + return ret; 706 706 + 707 707 + *val = 0; 708 708 + 709 709 + /* 710 710 + * ad7606b: phase delay from 0 to 318.75 μs in steps of 1.25 μs. 711 711 + * ad7606c-16/18: phase delay from 0 µs to 255 µs in steps of 1 µs. 712 712 + */ 713 713 + *val2 = ret * st->chip_info->calib_phase_avail[1][1]; 714 714 + 715 715 + return 0; 716 716 + } 717 717 + 720 718 static int ad7606_read_raw(struct iio_dev *indio_dev, 721 719 struct iio_chan_spec const *chan, 722 720 int *val, ··· 759 689 { 760 690 int ret, ch = 0; 761 691 struct ad7606_state *st = iio_priv(indio_dev); 762 762 - struct ad7606_chan_scale *cs; 692 692 + struct ad7606_chan_info *ci; 763 693 struct pwm_state cnvst_pwm_state; 764 694 765 695 switch (m) { ··· 774 704 case IIO_CHAN_INFO_SCALE: 775 705 if (st->sw_mode_en) 776 706 ch = chan->scan_index; 777 777 - cs = &st->chan_scales[ch]; 778 778 - *val = cs->scale_avail[cs->range][0]; 779 779 - *val2 = cs->scale_avail[cs->range][1]; 707 707 + ci = &st->chan_info[ch]; 708 708 + *val = ci->scale_avail[ci->range][0]; 709 709 + *val2 = ci->scale_avail[ci->range][1]; 780 710 return IIO_VAL_INT_PLUS_MICRO; 781 711 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 782 712 *val = st->oversampling; ··· 785 715 pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state); 786 716 *val = DIV_ROUND_CLOSEST_ULL(NSEC_PER_SEC, cnvst_pwm_state.period); 787 717 return IIO_VAL_INT; 718 718 + case IIO_CHAN_INFO_CALIBBIAS: 719 719 + if (!iio_device_claim_direct(indio_dev)) 720 720 + return -EBUSY; 721 721 + ret = ad7606_get_calib_offset(st, chan->scan_index, val); 722 722 + iio_device_release_direct(indio_dev); 723 723 + if (ret) 724 724 + return ret; 725 725 + return IIO_VAL_INT; 726 726 + case IIO_CHAN_INFO_CONVDELAY: 727 727 + if (!iio_device_claim_direct(indio_dev)) 728 728 + return -EBUSY; 729 729 + ret = ad7606_get_calib_phase(st, chan->scan_index, val, val2); 730 730 + iio_device_release_direct(indio_dev); 731 731 + if (ret) 732 732 + return ret; 733 733 + return IIO_VAL_INT_PLUS_NANO; 788 734 } 789 735 return -EINVAL; 790 736 } ··· 811 725 { 812 726 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 813 727 struct ad7606_state *st = iio_priv(indio_dev); 814 814 - struct ad7606_chan_scale *cs = &st->chan_scales[0]; 815 815 - const unsigned int (*vals)[2] = cs->scale_avail; 728 728 + struct ad7606_chan_info *ci = &st->chan_info[0]; 729 729 + const unsigned int (*vals)[2] = ci->scale_avail; 816 730 unsigned int i; 817 731 size_t len = 0; 818 732 819 819 - for (i = 0; i < cs->num_scales; i++) 733 733 + for (i = 0; i < ci->num_scales; i++) 820 734 len += scnprintf(buf + len, PAGE_SIZE - len, "%u.%06u ", 821 735 vals[i][0], vals[i][1]); 822 736 buf[len - 1] = '\n'; ··· 851 765 return 0; 852 766 } 853 767 768 768 + static int ad7606_set_calib_offset(struct ad7606_state *st, int ch, int val) 769 769 + { 770 770 + int start_val, step_val, stop_val; 771 771 + int offset; 772 772 + 773 773 + start_val = st->chip_info->calib_offset_avail[0]; 774 774 + step_val = st->chip_info->calib_offset_avail[1]; 775 775 + stop_val = st->chip_info->calib_offset_avail[2]; 776 776 + 777 777 + if (val < start_val || val > stop_val) 778 778 + return -EINVAL; 779 779 + 780 780 + offset = (val - start_val) / step_val; 781 781 + 782 782 + return st->bops->reg_write(st, AD7606_CALIB_OFFSET(ch), offset); 783 783 + } 784 784 + 785 785 + static int ad7606_set_calib_phase(struct ad7606_state *st, int ch, int val, 786 786 + int val2) 787 787 + { 788 788 + int wreg, start_ns, step_ns, stop_ns; 789 789 + 790 790 + if (val != 0) 791 791 + return -EINVAL; 792 792 + 793 793 + start_ns = st->chip_info->calib_phase_avail[0][1]; 794 794 + step_ns = st->chip_info->calib_phase_avail[1][1]; 795 795 + stop_ns = st->chip_info->calib_phase_avail[2][1]; 796 796 + 797 797 + /* 798 798 + * ad7606b: phase delay from 0 to 318.75 μs in steps of 1.25 μs. 799 799 + * ad7606c-16/18: phase delay from 0 µs to 255 µs in steps of 1 µs. 800 800 + */ 801 801 + if (val2 < start_ns || val2 > stop_ns) 802 802 + return -EINVAL; 803 803 + 804 804 + wreg = val2 / step_ns; 805 805 + 806 806 + return st->bops->reg_write(st, AD7606_CALIB_PHASE(ch), wreg); 807 807 + } 808 808 + 809 809 + static int ad7606_write_raw_get_fmt(struct iio_dev *indio_dev, 810 810 + struct iio_chan_spec const *chan, long info) 811 811 + { 812 812 + switch (info) { 813 813 + case IIO_CHAN_INFO_SCALE: 814 814 + return IIO_VAL_INT_PLUS_MICRO; 815 815 + case IIO_CHAN_INFO_SAMP_FREQ: 816 816 + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 817 817 + case IIO_CHAN_INFO_CALIBBIAS: 818 818 + return IIO_VAL_INT; 819 819 + case IIO_CHAN_INFO_CONVDELAY: 820 820 + return IIO_VAL_INT_PLUS_NANO; 821 821 + default: 822 822 + return -EINVAL; 823 823 + } 824 824 + } 825 825 + 854 826 static int ad7606_write_raw(struct iio_dev *indio_dev, 855 827 struct iio_chan_spec const *chan, 856 828 int val, ··· 917 773 { 918 774 struct ad7606_state *st = iio_priv(indio_dev); 919 775 unsigned int scale_avail_uv[AD760X_MAX_SCALES]; 920 920 - struct ad7606_chan_scale *cs; 776 776 + struct ad7606_chan_info *ci; 921 777 int i, ret, ch = 0; 922 778 923 779 guard(mutex)(&st->lock); ··· 926 782 case IIO_CHAN_INFO_SCALE: 927 783 if (st->sw_mode_en) 928 784 ch = chan->scan_index; 929 929 - cs = &st->chan_scales[ch]; 930 930 - for (i = 0; i < cs->num_scales; i++) { 931 931 - scale_avail_uv[i] = cs->scale_avail[i][0] * MICRO + 932 932 - cs->scale_avail[i][1]; 785 785 + ci = &st->chan_info[ch]; 786 786 + for (i = 0; i < ci->num_scales; i++) { 787 787 + scale_avail_uv[i] = ci->scale_avail[i][0] * MICRO + 788 788 + ci->scale_avail[i][1]; 933 789 } 934 790 val = (val * MICRO) + val2; 935 935 - i = find_closest(val, scale_avail_uv, cs->num_scales); 791 791 + i = find_closest(val, scale_avail_uv, ci->num_scales); 936 792 937 793 if (!iio_device_claim_direct(indio_dev)) 938 794 return -EBUSY; 939 939 - ret = st->write_scale(indio_dev, ch, i + cs->reg_offset); 795 795 + ret = st->write_scale(indio_dev, ch, i + ci->reg_offset); 940 796 iio_device_release_direct(indio_dev); 941 797 if (ret < 0) 942 798 return ret; 943 943 - cs->range = i; 799 799 + ci->range = i; 944 800 945 801 return 0; 946 802 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: ··· 962 818 if (val < 0 && val2 != 0) 963 819 return -EINVAL; 964 820 return ad7606_set_sampling_freq(st, val); 821 821 + case IIO_CHAN_INFO_CALIBBIAS: 822 822 + if (!iio_device_claim_direct(indio_dev)) 823 823 + return -EBUSY; 824 824 + ret = ad7606_set_calib_offset(st, chan->scan_index, val); 825 825 + iio_device_release_direct(indio_dev); 826 826 + return ret; 827 827 + case IIO_CHAN_INFO_CONVDELAY: 828 828 + if (!iio_device_claim_direct(indio_dev)) 829 829 + return -EBUSY; 830 830 + ret = ad7606_set_calib_phase(st, chan->scan_index, val, val2); 831 831 + iio_device_release_direct(indio_dev); 832 832 + return ret; 965 833 default: 966 834 return -EINVAL; 967 835 } ··· 1131 975 long info) 1132 976 { 1133 977 struct ad7606_state *st = iio_priv(indio_dev); 1134 1134 - struct ad7606_chan_scale *cs; 978 978 + struct ad7606_chan_info *ci; 1135 979 unsigned int ch = 0; 1136 980 1137 981 switch (info) { ··· 1146 990 if (st->sw_mode_en) 1147 991 ch = chan->scan_index; 1148 992 1149 1149 - cs = &st->chan_scales[ch]; 1150 1150 - *vals = (int *)cs->scale_avail; 1151 1151 - *length = cs->num_scales * 2; 993 993 + ci = &st->chan_info[ch]; 994 994 + *vals = (int *)ci->scale_avail; 995 995 + *length = ci->num_scales * 2; 1152 996 *type = IIO_VAL_INT_PLUS_MICRO; 1153 997 1154 998 return IIO_AVAIL_LIST; 999 999 + case IIO_CHAN_INFO_CALIBBIAS: 1000 1000 + *vals = st->chip_info->calib_offset_avail; 1001 1001 + *type = IIO_VAL_INT; 1002 1002 + return IIO_AVAIL_RANGE; 1003 1003 + case IIO_CHAN_INFO_CONVDELAY: 1004 1004 + *vals = (const int *)st->chip_info->calib_phase_avail; 1005 1005 + *type = IIO_VAL_INT_PLUS_NANO; 1006 1006 + return IIO_AVAIL_RANGE; 1155 1007 } 1156 1008 return -EINVAL; 1157 1009 } ··· 1222 1058 .read_raw = &ad7606_read_raw, 1223 1059 .write_raw = &ad7606_write_raw, 1224 1060 .read_avail = &ad7606_read_avail, 1061 1061 + .write_raw_get_fmt = ad7606_write_raw_get_fmt, 1225 1062 .debugfs_reg_access = &ad7606_reg_access, 1226 1063 .validate_trigger = &ad7606_validate_trigger, 1227 1064 .update_scan_mode = &ad7606_update_scan_mode, ··· 1368 1203 return st->bops->sw_mode_config(indio_dev); 1369 1204 } 1370 1205 1206 1206 + static int ad7606_set_gain_calib(struct ad7606_state *st) 1207 1207 + { 1208 1208 + struct ad7606_chan_info *ci; 1209 1209 + int i, ret; 1210 1210 + 1211 1211 + for (i = 0; i < st->chip_info->num_adc_channels; i++) { 1212 1212 + ci = &st->chan_info[i]; 1213 1213 + ret = st->bops->reg_write(st, AD7606_CALIB_GAIN(i), 1214 1214 + DIV_ROUND_CLOSEST(ci->r_gain, 1215 1215 + AD7606_CALIB_GAIN_STEP)); 1216 1216 + if (ret) 1217 1217 + return ret; 1218 1218 + } 1219 1219 + 1220 1220 + return 0; 1221 1221 + } 1222 1222 + 1371 1223 static int ad7606_probe_channels(struct iio_dev *indio_dev) 1372 1224 { 1373 1225 struct ad7606_state *st = iio_priv(indio_dev); ··· 1431 1249 chan->info_mask_separate |= BIT(IIO_CHAN_INFO_SCALE); 1432 1250 chan->info_mask_separate_available |= 1433 1251 BIT(IIO_CHAN_INFO_SCALE); 1252 1252 + 1253 1253 + if (st->chip_info->calib_offset_avail) { 1254 1254 + chan->info_mask_separate |= 1255 1255 + BIT(IIO_CHAN_INFO_CALIBBIAS) | 1256 1256 + BIT(IIO_CHAN_INFO_CONVDELAY); 1257 1257 + chan->info_mask_separate_available |= 1258 1258 + BIT(IIO_CHAN_INFO_CALIBBIAS) | 1259 1259 + BIT(IIO_CHAN_INFO_CONVDELAY); 1260 1260 + } 1434 1261 1435 1262 /* 1436 1263 * All chips with software mode support oversampling, ··· 1520 1329 if (ret) 1521 1330 return dev_err_probe(dev, ret, 1522 1331 "Failed to enable specified AVcc supply\n"); 1332 1332 + 1333 1333 + ret = devm_regulator_get_enable(dev, "vdrive"); 1334 1334 + if (ret) 1335 1335 + return dev_err_probe(dev, ret, 1336 1336 + "Failed to enable Vdrive supply\n"); 1337 1337 + 1338 1338 + ret = devm_regulator_get_enable_optional(dev, "refin"); 1339 1339 + if (ret && ret != -ENODEV) 1340 1340 + return dev_err_probe(dev, ret, 1341 1341 + "Failed to enable REFIN supply\n"); 1523 1342 1524 1343 st->chip_info = chip_info; 1525 1344 ··· 1663 1462 st->chip_info->sw_setup_cb(indio_dev); 1664 1463 } 1665 1464 1465 1465 + if (st->sw_mode_en && st->chip_info->calib_gain_avail) { 1466 1466 + ret = ad7606_set_gain_calib(st); 1467 1467 + if (ret) 1468 1468 + return ret; 1469 1469 + } 1470 1470 + 1666 1471 return devm_iio_device_register(dev, indio_dev); 1667 1472 } 1668 1473 EXPORT_SYMBOL_NS_GPL(ad7606_probe, "IIO_AD7606"); ··· 1694 1487 struct ad7606_state *st = iio_priv(indio_dev); 1695 1488 1696 1489 if (st->gpio_standby) { 1697 1697 - gpiod_set_value(st->gpio_range, st->chan_scales[0].range); 1490 1490 + gpiod_set_value(st->gpio_range, st->chan_info[0].range); 1698 1491 gpiod_set_value(st->gpio_standby, 1); 1699 1492 ad7606_reset(st); 1700 1493 }

+18 -4

drivers/iio/adc/ad7606.h

reviewed

··· 40 40 #define AD7606_RANGE_CH_ADDR(ch) (0x03 + ((ch) >> 1)) 41 41 #define AD7606_OS_MODE 0x08 42 42 43 43 + #define AD7606_CALIB_GAIN(ch) (0x09 + (ch)) 44 44 + #define AD7606_CALIB_GAIN_MASK GENMASK(5, 0) 45 45 + #define AD7606_CALIB_OFFSET(ch) (0x11 + (ch)) 46 46 + #define AD7606_CALIB_PHASE(ch) (0x19 + (ch)) 47 47 + 43 48 struct ad7606_state; 44 49 45 50 typedef int (*ad7606_scale_setup_cb_t)(struct iio_dev *indio_dev, ··· 66 61 * @init_delay_ms: required delay in milliseconds for initialization 67 62 * after a restart 68 63 * @offload_storagebits: storage bits used by the offload hw implementation 64 64 + * @calib_gain_avail: chip supports gain calibration 65 65 + * @calib_offset_avail: pointer to offset calibration range/limits array 66 66 + * @calib_phase_avail: pointer to phase calibration range/limits array 69 67 */ 70 68 struct ad7606_chip_info { 71 69 unsigned int max_samplerate; ··· 82 74 bool os_req_reset; 83 75 unsigned long init_delay_ms; 84 76 u8 offload_storagebits; 77 77 + bool calib_gain_avail; 78 78 + const int *calib_offset_avail; 79 79 + const int (*calib_phase_avail)[2]; 85 80 }; 86 81 87 82 /** 88 88 - * struct ad7606_chan_scale - channel scale configuration 83 83 + * struct ad7606_chan_info - channel configuration 89 84 * @scale_avail: pointer to the array which stores the available scales 90 85 * @num_scales: number of elements stored in the scale_avail array 91 86 * @range: voltage range selection, selects which scale to apply 92 87 * @reg_offset: offset for the register value, to be applied when 93 88 * writing the value of 'range' to the register value 89 89 + * @r_gain: gain resistor value in ohms, to be set to match the 90 90 + * external r_filter value 94 91 */ 95 95 - struct ad7606_chan_scale { 92 92 + struct ad7606_chan_info { 96 93 #define AD760X_MAX_SCALES 16 97 94 const unsigned int (*scale_avail)[2]; 98 95 unsigned int num_scales; 99 96 unsigned int range; 100 97 unsigned int reg_offset; 98 98 + unsigned int r_gain; 101 99 }; 102 100 103 101 /** ··· 111 97 * @dev: pointer to kernel device 112 98 * @chip_info: entry in the table of chips that describes this device 113 99 * @bops: bus operations (SPI or parallel) 114 114 - * @chan_scales: scale configuration for channels 100 100 + * @chan_info: scale configuration for channels 115 101 * @oversampling: oversampling selection 116 102 * @cnvst_pwm: pointer to the PWM device connected to the cnvst pin 117 103 * @base_address: address from where to read data in parallel operation ··· 142 128 struct device *dev; 143 129 const struct ad7606_chip_info *chip_info; 144 130 const struct ad7606_bus_ops *bops; 145 145 - struct ad7606_chan_scale chan_scales[AD760X_MAX_CHANNELS]; 131 131 + struct ad7606_chan_info chan_info[AD760X_MAX_CHANNELS]; 146 132 unsigned int oversampling; 147 133 struct pwm_device *cnvst_pwm; 148 134 void __iomem *base_address;

+814 -122

drivers/iio/adc/ad7768-1.c

reviewed

··· 11 11 #include <linux/delay.h> 12 12 #include <linux/device.h> 13 13 #include <linux/err.h> 14 14 + #include <linux/gpio/driver.h> 14 15 #include <linux/gpio/consumer.h> 15 16 #include <linux/interrupt.h> 17 17 + #include <linux/minmax.h> 16 18 #include <linux/module.h> 17 19 #include <linux/regmap.h> 18 20 #include <linux/regulator/consumer.h> 21 21 + #include <linux/regulator/driver.h> 19 22 #include <linux/sysfs.h> 20 23 #include <linux/spi/spi.h> 24 24 + #include <linux/unaligned.h> 25 25 + #include <linux/units.h> 26 26 + #include <linux/util_macros.h> 21 27 22 28 #include <linux/iio/buffer.h> 23 29 #include <linux/iio/iio.h> ··· 31 25 #include <linux/iio/trigger.h> 32 26 #include <linux/iio/triggered_buffer.h> 33 27 #include <linux/iio/trigger_consumer.h> 28 28 + 29 29 + #include <dt-bindings/iio/adc/adi,ad7768-1.h> 34 30 35 31 /* AD7768 registers definition */ 36 32 #define AD7768_REG_CHIP_TYPE 0x3 ··· 81 73 #define AD7768_PWR_PWRMODE(x) FIELD_PREP(AD7768_PWR_PWRMODE_MSK, x) 82 74 83 75 /* AD7768_REG_DIGITAL_FILTER */ 76 76 + #define AD7768_DIG_FIL_EN_60HZ_REJ BIT(7) 84 77 #define AD7768_DIG_FIL_FIL_MSK GENMASK(6, 4) 85 78 #define AD7768_DIG_FIL_FIL(x) FIELD_PREP(AD7768_DIG_FIL_FIL_MSK, x) 86 79 #define AD7768_DIG_FIL_DEC_MSK GENMASK(2, 0) ··· 90 81 /* AD7768_REG_CONVERSION */ 91 82 #define AD7768_CONV_MODE_MSK GENMASK(2, 0) 92 83 #define AD7768_CONV_MODE(x) FIELD_PREP(AD7768_CONV_MODE_MSK, x) 84 84 + 85 85 + /* AD7768_REG_ANALOG2 */ 86 86 + #define AD7768_REG_ANALOG2_VCM_MSK GENMASK(2, 0) 87 87 + #define AD7768_REG_ANALOG2_VCM(x) FIELD_PREP(AD7768_REG_ANALOG2_VCM_MSK, (x)) 88 88 + 89 89 + /* AD7768_REG_GPIO_CONTROL */ 90 90 + #define AD7768_GPIO_UNIVERSAL_EN BIT(7) 91 91 + #define AD7768_GPIO_CONTROL_MSK GENMASK(3, 0) 92 92 + 93 93 + /* AD7768_REG_GPIO_WRITE */ 94 94 + #define AD7768_GPIO_WRITE_MSK GENMASK(3, 0) 95 95 + 96 96 + /* AD7768_REG_GPIO_READ */ 97 97 + #define AD7768_GPIO_READ_MSK GENMASK(3, 0) 98 98 + 99 99 + #define AD7768_VCM_OFF 0x07 100 100 + 101 101 + #define AD7768_TRIGGER_SOURCE_SYNC_IDX 0 102 102 + 103 103 + #define AD7768_MAX_CHANNELS 1 93 104 94 105 enum ad7768_conv_mode { 95 106 AD7768_CONTINUOUS, ··· 132 103 AD7768_MCLK_DIV_2 133 104 }; 134 105 135 135 - enum ad7768_dec_rate { 136 136 - AD7768_DEC_RATE_32 = 0, 137 137 - AD7768_DEC_RATE_64 = 1, 138 138 - AD7768_DEC_RATE_128 = 2, 139 139 - AD7768_DEC_RATE_256 = 3, 140 140 - AD7768_DEC_RATE_512 = 4, 141 141 - AD7768_DEC_RATE_1024 = 5, 142 142 - AD7768_DEC_RATE_8 = 9, 143 143 - AD7768_DEC_RATE_16 = 10 106 106 + enum ad7768_filter_type { 107 107 + AD7768_FILTER_SINC5, 108 108 + AD7768_FILTER_SINC3, 109 109 + AD7768_FILTER_WIDEBAND, 110 110 + AD7768_FILTER_SINC3_REJ60, 144 111 }; 145 112 146 146 - struct ad7768_clk_configuration { 147 147 - enum ad7768_mclk_div mclk_div; 148 148 - enum ad7768_dec_rate dec_rate; 149 149 - unsigned int clk_div; 150 150 - enum ad7768_pwrmode pwrmode; 113 113 + enum ad7768_filter_regval { 114 114 + AD7768_FILTER_REGVAL_SINC5 = 0, 115 115 + AD7768_FILTER_REGVAL_SINC5_X8 = 1, 116 116 + AD7768_FILTER_REGVAL_SINC5_X16 = 2, 117 117 + AD7768_FILTER_REGVAL_SINC3 = 3, 118 118 + AD7768_FILTER_REGVAL_WIDEBAND = 4, 119 119 + AD7768_FILTER_REGVAL_SINC3_REJ60 = 11, 151 120 }; 152 121 153 153 - static const struct ad7768_clk_configuration ad7768_clk_config[] = { 154 154 - { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_8, 16, AD7768_FAST_MODE }, 155 155 - { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_16, 32, AD7768_FAST_MODE }, 156 156 - { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_32, 64, AD7768_FAST_MODE }, 157 157 - { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_64, 128, AD7768_FAST_MODE }, 158 158 - { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_128, 256, AD7768_FAST_MODE }, 159 159 - { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_128, 512, AD7768_MED_MODE }, 160 160 - { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_256, 1024, AD7768_MED_MODE }, 161 161 - { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_512, 2048, AD7768_MED_MODE }, 162 162 - { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_1024, 4096, AD7768_MED_MODE }, 163 163 - { AD7768_MCLK_DIV_8, AD7768_DEC_RATE_1024, 8192, AD7768_MED_MODE }, 164 164 - { AD7768_MCLK_DIV_16, AD7768_DEC_RATE_1024, 16384, AD7768_ECO_MODE }, 122 122 + enum ad7768_scan_type { 123 123 + AD7768_SCAN_TYPE_NORMAL, 124 124 + AD7768_SCAN_TYPE_HIGH_SPEED, 165 125 }; 166 126 167 167 - static const struct iio_chan_spec ad7768_channels[] = { 168 168 - { 169 169 - .type = IIO_VOLTAGE, 170 170 - .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), 171 171 - .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), 172 172 - .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), 173 173 - .indexed = 1, 174 174 - .channel = 0, 175 175 - .scan_index = 0, 176 176 - .scan_type = { 177 177 - .sign = 's', 178 178 - .realbits = 24, 179 179 - .storagebits = 32, 180 180 - .shift = 8, 181 181 - .endianness = IIO_BE, 182 182 - }, 127 127 + /* -3dB cutoff frequency multipliers (relative to ODR) for each filter type. */ 128 128 + static const int ad7768_filter_3db_odr_multiplier[] = { 129 129 + [AD7768_FILTER_SINC5] = 204, /* 0.204 */ 130 130 + [AD7768_FILTER_SINC3] = 262, /* 0.2617 */ 131 131 + [AD7768_FILTER_SINC3_REJ60] = 262, /* 0.2617 */ 132 132 + [AD7768_FILTER_WIDEBAND] = 433, /* 0.433 */ 133 133 + }; 134 134 + 135 135 + static const int ad7768_mclk_div_rates[] = { 136 136 + 16, 8, 4, 2, 137 137 + }; 138 138 + 139 139 + static const int ad7768_dec_rate_values[8] = { 140 140 + 8, 16, 32, 64, 128, 256, 512, 1024, 141 141 + }; 142 142 + 143 143 + /* Decimation rate range for sinc3 filter */ 144 144 + static const int ad7768_sinc3_dec_rate_range[3] = { 145 145 + 32, 32, 163840, 146 146 + }; 147 147 + 148 148 + /* 149 149 + * The AD7768-1 supports three primary filter types: 150 150 + * Sinc5, Sinc3, and Wideband. 151 151 + * However, the filter register values can also encode additional parameters 152 152 + * such as decimation rates and 60Hz rejection. This utility array separates 153 153 + * the filter type from these parameters. 154 154 + */ 155 155 + static const int ad7768_filter_regval_to_type[] = { 156 156 + [AD7768_FILTER_REGVAL_SINC5] = AD7768_FILTER_SINC5, 157 157 + [AD7768_FILTER_REGVAL_SINC5_X8] = AD7768_FILTER_SINC5, 158 158 + [AD7768_FILTER_REGVAL_SINC5_X16] = AD7768_FILTER_SINC5, 159 159 + [AD7768_FILTER_REGVAL_SINC3] = AD7768_FILTER_SINC3, 160 160 + [AD7768_FILTER_REGVAL_WIDEBAND] = AD7768_FILTER_WIDEBAND, 161 161 + [AD7768_FILTER_REGVAL_SINC3_REJ60] = AD7768_FILTER_SINC3_REJ60, 162 162 + }; 163 163 + 164 164 + static const char * const ad7768_filter_enum[] = { 165 165 + [AD7768_FILTER_SINC5] = "sinc5", 166 166 + [AD7768_FILTER_SINC3] = "sinc3", 167 167 + [AD7768_FILTER_WIDEBAND] = "wideband", 168 168 + [AD7768_FILTER_SINC3_REJ60] = "sinc3+rej60", 169 169 + }; 170 170 + 171 171 + static const struct iio_scan_type ad7768_scan_type[] = { 172 172 + [AD7768_SCAN_TYPE_NORMAL] = { 173 173 + .sign = 's', 174 174 + .realbits = 24, 175 175 + .storagebits = 32, 176 176 + .shift = 8, 177 177 + .endianness = IIO_BE, 178 178 + }, 179 179 + [AD7768_SCAN_TYPE_HIGH_SPEED] = { 180 180 + .sign = 's', 181 181 + .realbits = 16, 182 182 + .storagebits = 16, 183 183 + .endianness = IIO_BE, 183 184 }, 184 185 }; 185 186 ··· 218 159 struct regmap *regmap; 219 160 struct regmap *regmap24; 220 161 struct regulator *vref; 162 162 + struct regulator_dev *vcm_rdev; 163 163 + unsigned int vcm_output_sel; 221 164 struct clk *mclk; 222 165 unsigned int mclk_freq; 166 166 + unsigned int mclk_div; 167 167 + unsigned int oversampling_ratio; 168 168 + enum ad7768_filter_type filter_type; 223 169 unsigned int samp_freq; 170 170 + unsigned int samp_freq_avail[ARRAY_SIZE(ad7768_mclk_div_rates)]; 171 171 + unsigned int samp_freq_avail_len; 224 172 struct completion completion; 225 173 struct iio_trigger *trig; 226 174 struct gpio_desc *gpio_sync_in; 227 175 struct gpio_desc *gpio_reset; 228 228 - const char *labels[ARRAY_SIZE(ad7768_channels)]; 176 176 + const char *labels[AD7768_MAX_CHANNELS]; 177 177 + struct gpio_chip gpiochip; 178 178 + bool en_spi_sync; 229 179 /* 230 180 * DMA (thus cache coherency maintenance) may require the 231 181 * transfer buffers to live in their own cache lines. ··· 320 252 .max_register = AD7768_REG24_COEFF_DATA, 321 253 }; 322 254 255 255 + static int ad7768_send_sync_pulse(struct ad7768_state *st) 256 256 + { 257 257 + if (st->en_spi_sync) 258 258 + return regmap_write(st->regmap, AD7768_REG_SYNC_RESET, 0x00); 259 259 + 260 260 + /* 261 261 + * The datasheet specifies a minimum SYNC_IN pulse width of 1.5 × Tmclk, 262 262 + * where Tmclk is the MCLK period. The supported MCLK frequencies range 263 263 + * from 0.6 MHz to 17 MHz, which corresponds to a minimum SYNC_IN pulse 264 264 + * width of approximately 2.5 µs in the worst-case scenario (0.6 MHz). 265 265 + * 266 266 + * Add a delay to ensure the pulse width is always sufficient to 267 267 + * trigger synchronization. 268 268 + */ 269 269 + gpiod_set_value_cansleep(st->gpio_sync_in, 1); 270 270 + fsleep(3); 271 271 + gpiod_set_value_cansleep(st->gpio_sync_in, 0); 272 272 + 273 273 + return 0; 274 274 + } 275 275 + 276 276 + static void ad7768_fill_samp_freq_tbl(struct ad7768_state *st) 277 277 + { 278 278 + unsigned int i, samp_freq_avail, freq_filtered; 279 279 + unsigned int len = 0; 280 280 + 281 281 + freq_filtered = DIV_ROUND_CLOSEST(st->mclk_freq, st->oversampling_ratio); 282 282 + for (i = 0; i < ARRAY_SIZE(ad7768_mclk_div_rates); i++) { 283 283 + samp_freq_avail = DIV_ROUND_CLOSEST(freq_filtered, ad7768_mclk_div_rates[i]); 284 284 + /* Sampling frequency cannot be lower than the minimum of 50 SPS */ 285 285 + if (samp_freq_avail < 50) 286 286 + continue; 287 287 + 288 288 + st->samp_freq_avail[len++] = samp_freq_avail; 289 289 + } 290 290 + 291 291 + st->samp_freq_avail_len = len; 292 292 + } 293 293 + 294 294 + static int ad7768_set_mclk_div(struct ad7768_state *st, unsigned int mclk_div) 295 295 + { 296 296 + unsigned int mclk_div_value; 297 297 + 298 298 + mclk_div_value = AD7768_PWR_MCLK_DIV(mclk_div); 299 299 + /* 300 300 + * Set power mode based on mclk_div value. 301 301 + * ECO_MODE is only recommended for MCLK_DIV = 16. 302 302 + */ 303 303 + mclk_div_value |= mclk_div > AD7768_MCLK_DIV_16 ? 304 304 + AD7768_PWR_PWRMODE(AD7768_FAST_MODE) : 305 305 + AD7768_PWR_PWRMODE(AD7768_ECO_MODE); 306 306 + 307 307 + return regmap_update_bits(st->regmap, AD7768_REG_POWER_CLOCK, 308 308 + AD7768_PWR_MCLK_DIV_MSK | AD7768_PWR_PWRMODE_MSK, 309 309 + mclk_div_value); 310 310 + } 311 311 + 323 312 static int ad7768_set_mode(struct ad7768_state *st, 324 313 enum ad7768_conv_mode mode) 325 314 { ··· 403 278 ret = regmap_read(st->regmap24, AD7768_REG24_ADC_DATA, &readval); 404 279 if (ret) 405 280 return ret; 281 281 + 282 282 + /* 283 283 + * When the decimation rate is set to x8, the ADC data precision is 284 284 + * reduced from 24 bits to 16 bits. Since the AD7768_REG_ADC_DATA 285 285 + * register provides 24-bit data, the precision is reduced by 286 286 + * right-shifting the read value by 8 bits. 287 287 + */ 288 288 + if (st->oversampling_ratio == 8) 289 289 + readval >>= 8; 406 290 407 291 /* 408 292 * Any SPI configuration of the AD7768-1 can only be ··· 457 323 return ret; 458 324 } 459 325 460 460 - static int ad7768_set_dig_fil(struct ad7768_state *st, 461 461 - enum ad7768_dec_rate dec_rate) 326 326 + static int ad7768_set_sinc3_dec_rate(struct ad7768_state *st, 327 327 + unsigned int dec_rate) 462 328 { 463 463 - unsigned int mode; 329 329 + unsigned int max_dec_rate; 330 330 + u8 dec_rate_reg[2]; 331 331 + u16 regval; 464 332 int ret; 465 333 466 466 - if (dec_rate == AD7768_DEC_RATE_8 || dec_rate == AD7768_DEC_RATE_16) 467 467 - mode = AD7768_DIG_FIL_FIL(dec_rate); 468 468 - else 469 469 - mode = AD7768_DIG_FIL_DEC_RATE(dec_rate); 334 334 + /* 335 335 + * Maximum dec_rate is limited by the MCLK_DIV value and by the ODR. 336 336 + * The edge case is for MCLK_DIV = 2, ODR = 50 SPS. 337 337 + * max_dec_rate <= MCLK / (2 * 50) 338 338 + */ 339 339 + max_dec_rate = st->mclk_freq / 100; 340 340 + dec_rate = clamp(dec_rate, 32, max_dec_rate); 341 341 + /* 342 342 + * Calculate the equivalent value to sinc3 decimation ratio 343 343 + * to be written on the SINC3_DEC_RATE register: 344 344 + * Value = (DEC_RATE / 32) - 1 345 345 + */ 346 346 + dec_rate = DIV_ROUND_UP(dec_rate, 32) - 1; 470 347 471 471 - ret = regmap_write(st->regmap, AD7768_REG_DIGITAL_FILTER, mode); 472 472 - if (ret < 0) 348 348 + /* 349 349 + * The SINC3_DEC_RATE value is a 13-bit value split across two 350 350 + * registers: MSB [12:8] and LSB [7:0]. Prepare the 13-bit value using 351 351 + * FIELD_PREP() and store it with the right endianness in dec_rate_reg. 352 352 + */ 353 353 + regval = FIELD_PREP(GENMASK(12, 0), dec_rate); 354 354 + put_unaligned_be16(regval, dec_rate_reg); 355 355 + ret = regmap_bulk_write(st->regmap, AD7768_REG_SINC3_DEC_RATE_MSB, 356 356 + dec_rate_reg, 2); 357 357 + if (ret) 473 358 return ret; 474 359 475 475 - /* A sync-in pulse is required every time the filter dec rate changes */ 476 476 - gpiod_set_value(st->gpio_sync_in, 1); 477 477 - gpiod_set_value(st->gpio_sync_in, 0); 360 360 + st->oversampling_ratio = (dec_rate + 1) * 32; 478 361 479 362 return 0; 363 363 + } 364 364 + 365 365 + static int ad7768_configure_dig_fil(struct iio_dev *dev, 366 366 + enum ad7768_filter_type filter_type, 367 367 + unsigned int dec_rate) 368 368 + { 369 369 + struct ad7768_state *st = iio_priv(dev); 370 370 + unsigned int dec_rate_idx, dig_filter_regval; 371 371 + int ret; 372 372 + 373 373 + switch (filter_type) { 374 374 + case AD7768_FILTER_SINC3: 375 375 + dig_filter_regval = AD7768_DIG_FIL_FIL(AD7768_FILTER_REGVAL_SINC3); 376 376 + break; 377 377 + case AD7768_FILTER_SINC3_REJ60: 378 378 + dig_filter_regval = AD7768_DIG_FIL_FIL(AD7768_FILTER_REGVAL_SINC3) | 379 379 + AD7768_DIG_FIL_EN_60HZ_REJ; 380 380 + break; 381 381 + case AD7768_FILTER_WIDEBAND: 382 382 + /* Skip decimations 8 and 16, not supported by the wideband filter */ 383 383 + dec_rate_idx = find_closest(dec_rate, &ad7768_dec_rate_values[2], 384 384 + ARRAY_SIZE(ad7768_dec_rate_values) - 2); 385 385 + dig_filter_regval = AD7768_DIG_FIL_FIL(AD7768_FILTER_REGVAL_WIDEBAND) | 386 386 + AD7768_DIG_FIL_DEC_RATE(dec_rate_idx); 387 387 + /* Correct the index offset */ 388 388 + dec_rate_idx += 2; 389 389 + break; 390 390 + case AD7768_FILTER_SINC5: 391 391 + dec_rate_idx = find_closest(dec_rate, ad7768_dec_rate_values, 392 392 + ARRAY_SIZE(ad7768_dec_rate_values)); 393 393 + 394 394 + /* 395 395 + * Decimations 8 (idx 0) and 16 (idx 1) are set in the 396 396 + * FILTER[6:4] field. The other decimations are set in the 397 397 + * DEC_RATE[2:0] field, and the idx needs to be offsetted by two. 398 398 + */ 399 399 + if (dec_rate_idx == 0) 400 400 + dig_filter_regval = AD7768_DIG_FIL_FIL(AD7768_FILTER_REGVAL_SINC5_X8); 401 401 + else if (dec_rate_idx == 1) 402 402 + dig_filter_regval = AD7768_DIG_FIL_FIL(AD7768_FILTER_REGVAL_SINC5_X16); 403 403 + else 404 404 + dig_filter_regval = AD7768_DIG_FIL_FIL(AD7768_FILTER_REGVAL_SINC5) | 405 405 + AD7768_DIG_FIL_DEC_RATE(dec_rate_idx - 2); 406 406 + break; 407 407 + } 408 408 + 409 409 + ret = regmap_write(st->regmap, AD7768_REG_DIGITAL_FILTER, dig_filter_regval); 410 410 + if (ret) 411 411 + return ret; 412 412 + 413 413 + st->filter_type = filter_type; 414 414 + /* 415 415 + * The decimation for SINC3 filters are configured in different 416 416 + * registers. 417 417 + */ 418 418 + if (filter_type == AD7768_FILTER_SINC3 || 419 419 + filter_type == AD7768_FILTER_SINC3_REJ60) { 420 420 + ret = ad7768_set_sinc3_dec_rate(st, dec_rate); 421 421 + if (ret) 422 422 + return ret; 423 423 + } else { 424 424 + st->oversampling_ratio = ad7768_dec_rate_values[dec_rate_idx]; 425 425 + } 426 426 + 427 427 + ad7768_fill_samp_freq_tbl(st); 428 428 + 429 429 + /* A sync-in pulse is required after every configuration change */ 430 430 + return ad7768_send_sync_pulse(st); 431 431 + } 432 432 + 433 433 + static int ad7768_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) 434 434 + { 435 435 + struct iio_dev *indio_dev = gpiochip_get_data(chip); 436 436 + struct ad7768_state *st = iio_priv(indio_dev); 437 437 + int ret; 438 438 + 439 439 + if (!iio_device_claim_direct(indio_dev)) 440 440 + return -EBUSY; 441 441 + 442 442 + ret = regmap_clear_bits(st->regmap, AD7768_REG_GPIO_CONTROL, 443 443 + BIT(offset)); 444 444 + iio_device_release_direct(indio_dev); 445 445 + 446 446 + return ret; 447 447 + } 448 448 + 449 449 + static int ad7768_gpio_direction_output(struct gpio_chip *chip, 450 450 + unsigned int offset, int value) 451 451 + { 452 452 + struct iio_dev *indio_dev = gpiochip_get_data(chip); 453 453 + struct ad7768_state *st = iio_priv(indio_dev); 454 454 + int ret; 455 455 + 456 456 + if (!iio_device_claim_direct(indio_dev)) 457 457 + return -EBUSY; 458 458 + 459 459 + ret = regmap_set_bits(st->regmap, AD7768_REG_GPIO_CONTROL, 460 460 + BIT(offset)); 461 461 + iio_device_release_direct(indio_dev); 462 462 + 463 463 + return ret; 464 464 + } 465 465 + 466 466 + static int ad7768_gpio_get(struct gpio_chip *chip, unsigned int offset) 467 467 + { 468 468 + struct iio_dev *indio_dev = gpiochip_get_data(chip); 469 469 + struct ad7768_state *st = iio_priv(indio_dev); 470 470 + unsigned int val; 471 471 + int ret; 472 472 + 473 473 + if (!iio_device_claim_direct(indio_dev)) 474 474 + return -EBUSY; 475 475 + 476 476 + ret = regmap_read(st->regmap, AD7768_REG_GPIO_CONTROL, &val); 477 477 + if (ret) 478 478 + goto err_release; 479 479 + 480 480 + /* 481 481 + * If the GPIO is configured as an output, read the current value from 482 482 + * AD7768_REG_GPIO_WRITE. Otherwise, read the input value from 483 483 + * AD7768_REG_GPIO_READ. 484 484 + */ 485 485 + if (val & BIT(offset)) 486 486 + ret = regmap_read(st->regmap, AD7768_REG_GPIO_WRITE, &val); 487 487 + else 488 488 + ret = regmap_read(st->regmap, AD7768_REG_GPIO_READ, &val); 489 489 + if (ret) 490 490 + goto err_release; 491 491 + 492 492 + ret = !!(val & BIT(offset)); 493 493 + err_release: 494 494 + iio_device_release_direct(indio_dev); 495 495 + 496 496 + return ret; 497 497 + } 498 498 + 499 499 + static int ad7768_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) 500 500 + { 501 501 + struct iio_dev *indio_dev = gpiochip_get_data(chip); 502 502 + struct ad7768_state *st = iio_priv(indio_dev); 503 503 + unsigned int val; 504 504 + int ret; 505 505 + 506 506 + if (!iio_device_claim_direct(indio_dev)) 507 507 + return -EBUSY; 508 508 + 509 509 + ret = regmap_read(st->regmap, AD7768_REG_GPIO_CONTROL, &val); 510 510 + if (ret) 511 511 + goto err_release; 512 512 + 513 513 + if (val & BIT(offset)) 514 514 + ret = regmap_assign_bits(st->regmap, AD7768_REG_GPIO_WRITE, 515 515 + BIT(offset), value); 516 516 + 517 517 + err_release: 518 518 + iio_device_release_direct(indio_dev); 519 519 + 520 520 + return ret; 521 521 + } 522 522 + 523 523 + static int ad7768_gpio_init(struct iio_dev *indio_dev) 524 524 + { 525 525 + struct ad7768_state *st = iio_priv(indio_dev); 526 526 + int ret; 527 527 + 528 528 + ret = regmap_write(st->regmap, AD7768_REG_GPIO_CONTROL, 529 529 + AD7768_GPIO_UNIVERSAL_EN); 530 530 + if (ret) 531 531 + return ret; 532 532 + 533 533 + st->gpiochip = (struct gpio_chip) { 534 534 + .label = "ad7768_1_gpios", 535 535 + .base = -1, 536 536 + .ngpio = 4, 537 537 + .parent = &st->spi->dev, 538 538 + .can_sleep = true, 539 539 + .direction_input = ad7768_gpio_direction_input, 540 540 + .direction_output = ad7768_gpio_direction_output, 541 541 + .get = ad7768_gpio_get, 542 542 + .set_rv = ad7768_gpio_set, 543 543 + .owner = THIS_MODULE, 544 544 + }; 545 545 + 546 546 + return devm_gpiochip_add_data(&st->spi->dev, &st->gpiochip, indio_dev); 480 547 } 481 548 482 549 static int ad7768_set_freq(struct ad7768_state *st, 483 550 unsigned int freq) 484 551 { 485 485 - unsigned int diff_new, diff_old, pwr_mode, i, idx; 486 486 - int res, ret; 552 552 + unsigned int idx, mclk_div; 553 553 + int ret; 487 554 488 488 - diff_old = U32_MAX; 489 489 - idx = 0; 555 555 + freq = clamp(freq, 50, 1024000); 556 556 + if (freq == 0) 557 557 + return -EINVAL; 490 558 491 491 - res = DIV_ROUND_CLOSEST(st->mclk_freq, freq); 492 492 - 559 559 + mclk_div = DIV_ROUND_CLOSEST(st->mclk_freq, freq * st->oversampling_ratio); 493 560 /* Find the closest match for the desired sampling frequency */ 494 494 - for (i = 0; i < ARRAY_SIZE(ad7768_clk_config); i++) { 495 495 - diff_new = abs(res - ad7768_clk_config[i].clk_div); 496 496 - if (diff_new < diff_old) { 497 497 - diff_old = diff_new; 498 498 - idx = i; 499 499 - } 500 500 - } 501 501 - 502 502 - /* 503 503 - * Set both the mclk_div and pwrmode with a single write to the 504 504 - * POWER_CLOCK register 505 505 - */ 506 506 - pwr_mode = AD7768_PWR_MCLK_DIV(ad7768_clk_config[idx].mclk_div) | 507 507 - AD7768_PWR_PWRMODE(ad7768_clk_config[idx].pwrmode); 508 508 - ret = regmap_write(st->regmap, AD7768_REG_POWER_CLOCK, pwr_mode); 509 509 - if (ret < 0) 510 510 - return ret; 511 511 - 512 512 - ret = ad7768_set_dig_fil(st, ad7768_clk_config[idx].dec_rate); 513 513 - if (ret < 0) 561 561 + idx = find_closest_descending(mclk_div, ad7768_mclk_div_rates, 562 562 + ARRAY_SIZE(ad7768_mclk_div_rates)); 563 563 + /* Set both the mclk_div and pwrmode */ 564 564 + ret = ad7768_set_mclk_div(st, idx); 565 565 + if (ret) 514 566 return ret; 515 567 516 568 st->samp_freq = DIV_ROUND_CLOSEST(st->mclk_freq, 517 517 - ad7768_clk_config[idx].clk_div); 569 569 + ad7768_mclk_div_rates[idx] * st->oversampling_ratio); 518 570 519 519 - return 0; 571 571 + /* A sync-in pulse is required after every configuration change */ 572 572 + return ad7768_send_sync_pulse(st); 520 573 } 521 574 522 522 - static ssize_t ad7768_sampling_freq_avail(struct device *dev, 523 523 - struct device_attribute *attr, 524 524 - char *buf) 575 575 + static int ad7768_set_filter_type_attr(struct iio_dev *dev, 576 576 + const struct iio_chan_spec *chan, 577 577 + unsigned int filter) 525 578 { 526 526 - struct iio_dev *indio_dev = dev_to_iio_dev(dev); 527 527 - struct ad7768_state *st = iio_priv(indio_dev); 528 528 - unsigned int freq; 529 529 - int i, len = 0; 579 579 + struct ad7768_state *st = iio_priv(dev); 580 580 + int ret; 530 581 531 531 - for (i = 0; i < ARRAY_SIZE(ad7768_clk_config); i++) { 532 532 - freq = DIV_ROUND_CLOSEST(st->mclk_freq, 533 533 - ad7768_clk_config[i].clk_div); 534 534 - len += scnprintf(buf + len, PAGE_SIZE - len, "%d ", freq); 535 535 - } 582 582 + ret = ad7768_configure_dig_fil(dev, filter, st->oversampling_ratio); 583 583 + if (ret) 584 584 + return ret; 536 585 537 537 - buf[len - 1] = '\n'; 538 538 - 539 539 - return len; 586 586 + /* Update sampling frequency */ 587 587 + return ad7768_set_freq(st, st->samp_freq); 540 588 } 541 589 542 542 - static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(ad7768_sampling_freq_avail); 590 590 + static int ad7768_get_filter_type_attr(struct iio_dev *dev, 591 591 + const struct iio_chan_spec *chan) 592 592 + { 593 593 + struct ad7768_state *st = iio_priv(dev); 594 594 + int ret; 595 595 + unsigned int mode, mask; 596 596 + 597 597 + ret = regmap_read(st->regmap, AD7768_REG_DIGITAL_FILTER, &mode); 598 598 + if (ret) 599 599 + return ret; 600 600 + 601 601 + mask = AD7768_DIG_FIL_EN_60HZ_REJ | AD7768_DIG_FIL_FIL_MSK; 602 602 + /* From the register value, get the corresponding filter type */ 603 603 + return ad7768_filter_regval_to_type[FIELD_GET(mask, mode)]; 604 604 + } 605 605 + 606 606 + static const struct iio_enum ad7768_filter_type_iio_enum = { 607 607 + .items = ad7768_filter_enum, 608 608 + .num_items = ARRAY_SIZE(ad7768_filter_enum), 609 609 + .set = ad7768_set_filter_type_attr, 610 610 + .get = ad7768_get_filter_type_attr, 611 611 + }; 612 612 + 613 613 + static const struct iio_chan_spec_ext_info ad7768_ext_info[] = { 614 614 + IIO_ENUM("filter_type", IIO_SHARED_BY_ALL, &ad7768_filter_type_iio_enum), 615 615 + IIO_ENUM_AVAILABLE("filter_type", IIO_SHARED_BY_ALL, &ad7768_filter_type_iio_enum), 616 616 + { } 617 617 + }; 618 618 + 619 619 + static const struct iio_chan_spec ad7768_channels[] = { 620 620 + { 621 621 + .type = IIO_VOLTAGE, 622 622 + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), 623 623 + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | 624 624 + BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | 625 625 + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), 626 626 + .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), 627 627 + .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), 628 628 + .info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_SAMP_FREQ), 629 629 + .ext_info = ad7768_ext_info, 630 630 + .indexed = 1, 631 631 + .channel = 0, 632 632 + .scan_index = 0, 633 633 + .has_ext_scan_type = 1, 634 634 + .ext_scan_type = ad7768_scan_type, 635 635 + .num_ext_scan_type = ARRAY_SIZE(ad7768_scan_type), 636 636 + }, 637 637 + }; 543 638 544 639 static int ad7768_read_raw(struct iio_dev *indio_dev, 545 640 struct iio_chan_spec const *chan, 546 641 int *val, int *val2, long info) 547 642 { 548 643 struct ad7768_state *st = iio_priv(indio_dev); 549 549 - int scale_uv, ret; 644 644 + const struct iio_scan_type *scan_type; 645 645 + int scale_uv, ret, temp; 646 646 + 647 647 + scan_type = iio_get_current_scan_type(indio_dev, chan); 648 648 + if (IS_ERR(scan_type)) 649 649 + return PTR_ERR(scan_type); 550 650 551 651 switch (info) { 552 652 case IIO_CHAN_INFO_RAW: ··· 792 424 iio_device_release_direct(indio_dev); 793 425 if (ret < 0) 794 426 return ret; 795 795 - *val = sign_extend32(ret, chan->scan_type.realbits - 1); 427 427 + *val = sign_extend32(ret, scan_type->realbits - 1); 796 428 797 429 return IIO_VAL_INT; 798 430 ··· 802 434 return scale_uv; 803 435 804 436 *val = (scale_uv * 2) / 1000; 805 805 - *val2 = chan->scan_type.realbits; 437 437 + *val2 = scan_type->realbits; 806 438 807 439 return IIO_VAL_FRACTIONAL_LOG2; 808 440 ··· 810 442 *val = st->samp_freq; 811 443 812 444 return IIO_VAL_INT; 445 445 + 446 446 + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 447 447 + *val = st->oversampling_ratio; 448 448 + 449 449 + return IIO_VAL_INT; 450 450 + 451 451 + case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 452 452 + temp = st->samp_freq * ad7768_filter_3db_odr_multiplier[st->filter_type]; 453 453 + *val = DIV_ROUND_CLOSEST(temp, MILLI); 454 454 + 455 455 + return IIO_VAL_INT; 813 456 } 814 457 815 458 return -EINVAL; 459 459 + } 460 460 + 461 461 + static int ad7768_read_avail(struct iio_dev *indio_dev, 462 462 + struct iio_chan_spec const *chan, 463 463 + const int **vals, int *type, int *length, 464 464 + long info) 465 465 + { 466 466 + struct ad7768_state *st = iio_priv(indio_dev); 467 467 + unsigned int shift; 468 468 + 469 469 + switch (info) { 470 470 + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 471 471 + /* 472 472 + * Sinc3 filter allows a wider range of OSR values, so show 473 473 + * the available values in range format. 474 474 + */ 475 475 + if (st->filter_type == AD7768_FILTER_SINC3 || 476 476 + st->filter_type == AD7768_FILTER_SINC3_REJ60) { 477 477 + *vals = (int *)ad7768_sinc3_dec_rate_range; 478 478 + *type = IIO_VAL_INT; 479 479 + return IIO_AVAIL_RANGE; 480 480 + } 481 481 + 482 482 + shift = st->filter_type == AD7768_FILTER_SINC5 ? 0 : 2; 483 483 + *vals = (int *)&ad7768_dec_rate_values[shift]; 484 484 + *length = ARRAY_SIZE(ad7768_dec_rate_values) - shift; 485 485 + *type = IIO_VAL_INT; 486 486 + return IIO_AVAIL_LIST; 487 487 + case IIO_CHAN_INFO_SAMP_FREQ: 488 488 + *vals = (int *)st->samp_freq_avail; 489 489 + *length = st->samp_freq_avail_len; 490 490 + *type = IIO_VAL_INT; 491 491 + return IIO_AVAIL_LIST; 492 492 + default: 493 493 + return -EINVAL; 494 494 + } 495 495 + } 496 496 + 497 497 + static int __ad7768_write_raw(struct iio_dev *indio_dev, 498 498 + struct iio_chan_spec const *chan, 499 499 + int val, int val2, long info) 500 500 + { 501 501 + struct ad7768_state *st = iio_priv(indio_dev); 502 502 + int ret; 503 503 + 504 504 + switch (info) { 505 505 + case IIO_CHAN_INFO_SAMP_FREQ: 506 506 + return ad7768_set_freq(st, val); 507 507 + 508 508 + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 509 509 + ret = ad7768_configure_dig_fil(indio_dev, st->filter_type, val); 510 510 + if (ret) 511 511 + return ret; 512 512 + 513 513 + /* Update sampling frequency */ 514 514 + return ad7768_set_freq(st, st->samp_freq); 515 515 + default: 516 516 + return -EINVAL; 517 517 + } 816 518 } 817 519 818 520 static int ad7768_write_raw(struct iio_dev *indio_dev, 819 521 struct iio_chan_spec const *chan, 820 522 int val, int val2, long info) 821 523 { 822 822 - struct ad7768_state *st = iio_priv(indio_dev); 524 524 + int ret; 823 525 824 824 - switch (info) { 825 825 - case IIO_CHAN_INFO_SAMP_FREQ: 826 826 - return ad7768_set_freq(st, val); 827 827 - default: 828 828 - return -EINVAL; 829 829 - } 526 526 + if (!iio_device_claim_direct(indio_dev)) 527 527 + return -EBUSY; 528 528 + 529 529 + ret = __ad7768_write_raw(indio_dev, chan, val, val2, info); 530 530 + iio_device_release_direct(indio_dev); 531 531 + 532 532 + return ret; 830 533 } 831 534 832 535 static int ad7768_read_label(struct iio_dev *indio_dev, ··· 908 469 return sprintf(label, "%s\n", st->labels[chan->channel]); 909 470 } 910 471 911 911 - static struct attribute *ad7768_attributes[] = { 912 912 - &iio_dev_attr_sampling_frequency_available.dev_attr.attr, 913 913 - NULL 914 914 - }; 472 472 + static int ad7768_get_current_scan_type(const struct iio_dev *indio_dev, 473 473 + const struct iio_chan_spec *chan) 474 474 + { 475 475 + struct ad7768_state *st = iio_priv(indio_dev); 915 476 916 916 - static const struct attribute_group ad7768_group = { 917 917 - .attrs = ad7768_attributes, 918 918 - }; 477 477 + return st->oversampling_ratio == 8 ? 478 478 + AD7768_SCAN_TYPE_HIGH_SPEED : AD7768_SCAN_TYPE_NORMAL; 479 479 + } 919 480 920 481 static const struct iio_info ad7768_info = { 921 921 - .attrs = &ad7768_group, 922 482 .read_raw = &ad7768_read_raw, 483 483 + .read_avail = &ad7768_read_avail, 923 484 .write_raw = &ad7768_write_raw, 924 485 .read_label = ad7768_read_label, 486 486 + .get_current_scan_type = &ad7768_get_current_scan_type, 925 487 .debugfs_reg_access = &ad7768_reg_access, 926 488 }; 927 489 928 928 - static int ad7768_setup(struct ad7768_state *st) 490 490 + static struct fwnode_handle * 491 491 + ad7768_fwnode_find_reference_args(const struct fwnode_handle *fwnode, 492 492 + const char *name, const char *nargs_prop, 493 493 + unsigned int nargs, unsigned int index, 494 494 + struct fwnode_reference_args *args) 929 495 { 496 496 + int ret; 497 497 + 498 498 + ret = fwnode_property_get_reference_args(fwnode, name, nargs_prop, 499 499 + nargs, index, args); 500 500 + return ret ? ERR_PTR(ret) : args->fwnode; 501 501 + } 502 502 + 503 503 + static int ad7768_trigger_sources_sync_setup(struct device *dev, 504 504 + struct fwnode_handle *fwnode, 505 505 + struct ad7768_state *st) 506 506 + { 507 507 + struct fwnode_reference_args args; 508 508 + 509 509 + struct fwnode_handle *ref __free(fwnode_handle) = 510 510 + ad7768_fwnode_find_reference_args(fwnode, "trigger-sources", 511 511 + "#trigger-source-cells", 0, 512 512 + AD7768_TRIGGER_SOURCE_SYNC_IDX, 513 513 + &args); 514 514 + if (IS_ERR(ref)) 515 515 + return PTR_ERR(ref); 516 516 + 517 517 + ref = args.fwnode; 518 518 + /* First, try getting the GPIO trigger source */ 519 519 + if (fwnode_device_is_compatible(ref, "gpio-trigger")) { 520 520 + st->gpio_sync_in = devm_fwnode_gpiod_get_index(dev, ref, NULL, 0, 521 521 + GPIOD_OUT_LOW, 522 522 + "sync-in"); 523 523 + return PTR_ERR_OR_ZERO(st->gpio_sync_in); 524 524 + } 525 525 + 526 526 + /* 527 527 + * TODO: Support the other cases when we have a trigger subsystem 528 528 + * to reliably handle other types of devices as trigger sources. 529 529 + * 530 530 + * For now, return an error message. For self triggering, omit the 531 531 + * trigger-sources property. 532 532 + */ 533 533 + return dev_err_probe(dev, -EOPNOTSUPP, "Invalid synchronization trigger source\n"); 534 534 + } 535 535 + 536 536 + static int ad7768_trigger_sources_get_sync(struct device *dev, 537 537 + struct ad7768_state *st) 538 538 + { 539 539 + struct fwnode_handle *fwnode = dev_fwnode(dev); 540 540 + 541 541 + /* 542 542 + * The AD7768-1 allows two primary methods for driving the SYNC_IN pin 543 543 + * to synchronize one or more devices: 544 544 + * 1. Using an external GPIO. 545 545 + * 2. Using a SPI command, where the SYNC_OUT pin generates a 546 546 + * synchronization pulse that drives the SYNC_IN pin. 547 547 + */ 548 548 + if (fwnode_property_present(fwnode, "trigger-sources")) 549 549 + return ad7768_trigger_sources_sync_setup(dev, fwnode, st); 550 550 + 551 551 + /* 552 552 + * In the absence of trigger-sources property, enable self 553 553 + * synchronization over SPI (SYNC_OUT). 554 554 + */ 555 555 + st->en_spi_sync = true; 556 556 + 557 557 + return 0; 558 558 + } 559 559 + 560 560 + static int ad7768_setup(struct iio_dev *indio_dev) 561 561 + { 562 562 + struct ad7768_state *st = iio_priv(indio_dev); 930 563 int ret; 931 564 932 565 st->gpio_reset = devm_gpiod_get_optional(&st->spi->dev, "reset", ··· 1026 515 return ret; 1027 516 } 1028 517 1029 1029 - st->gpio_sync_in = devm_gpiod_get(&st->spi->dev, "adi,sync-in", 1030 1030 - GPIOD_OUT_LOW); 518 518 + /* For backwards compatibility, try the adi,sync-in-gpios property */ 519 519 + st->gpio_sync_in = devm_gpiod_get_optional(&st->spi->dev, "adi,sync-in", 520 520 + GPIOD_OUT_LOW); 1031 521 if (IS_ERR(st->gpio_sync_in)) 1032 522 return PTR_ERR(st->gpio_sync_in); 523 523 + 524 524 + /* 525 525 + * If the synchronization is not defined by adi,sync-in-gpios, try the 526 526 + * trigger-sources. 527 527 + */ 528 528 + if (!st->gpio_sync_in) { 529 529 + ret = ad7768_trigger_sources_get_sync(&st->spi->dev, st); 530 530 + if (ret) 531 531 + return ret; 532 532 + } 533 533 + 534 534 + /* Only create a Chip GPIO if flagged for it */ 535 535 + if (device_property_read_bool(&st->spi->dev, "gpio-controller")) { 536 536 + ret = ad7768_gpio_init(indio_dev); 537 537 + if (ret) 538 538 + return ret; 539 539 + } 540 540 + 541 541 + /* 542 542 + * Set Default Digital Filter configuration: 543 543 + * SINC5 filter with x32 Decimation rate 544 544 + */ 545 545 + ret = ad7768_configure_dig_fil(indio_dev, AD7768_FILTER_SINC5, 32); 546 546 + if (ret) 547 547 + return ret; 1033 548 1034 549 /* Set the default sampling frequency to 32000 kSPS */ 1035 550 return ad7768_set_freq(st, 32000); ··· 1066 529 struct iio_poll_func *pf = p; 1067 530 struct iio_dev *indio_dev = pf->indio_dev; 1068 531 struct ad7768_state *st = iio_priv(indio_dev); 532 532 + const struct iio_scan_type *scan_type; 1069 533 int ret; 1070 534 1071 1071 - ret = spi_read(st->spi, &st->data.scan.chan, 3); 535 535 + scan_type = iio_get_current_scan_type(indio_dev, &indio_dev->channels[0]); 536 536 + if (IS_ERR(scan_type)) 537 537 + goto out; 538 538 + 539 539 + ret = spi_read(st->spi, &st->data.scan.chan, 540 540 + BITS_TO_BYTES(scan_type->realbits)); 1072 541 if (ret < 0) 1073 542 goto out; 1074 543 ··· 1190 647 &ad7768_buffer_ops); 1191 648 } 1192 649 650 650 + static int ad7768_vcm_enable(struct regulator_dev *rdev) 651 651 + { 652 652 + struct iio_dev *indio_dev = rdev_get_drvdata(rdev); 653 653 + struct ad7768_state *st = iio_priv(indio_dev); 654 654 + int ret, regval; 655 655 + 656 656 + if (!iio_device_claim_direct(indio_dev)) 657 657 + return -EBUSY; 658 658 + 659 659 + /* To enable, set the last selected output */ 660 660 + regval = AD7768_REG_ANALOG2_VCM(st->vcm_output_sel + 1); 661 661 + ret = regmap_update_bits(st->regmap, AD7768_REG_ANALOG2, 662 662 + AD7768_REG_ANALOG2_VCM_MSK, regval); 663 663 + iio_device_release_direct(indio_dev); 664 664 + 665 665 + return ret; 666 666 + } 667 667 + 668 668 + static int ad7768_vcm_disable(struct regulator_dev *rdev) 669 669 + { 670 670 + struct iio_dev *indio_dev = rdev_get_drvdata(rdev); 671 671 + struct ad7768_state *st = iio_priv(indio_dev); 672 672 + int ret; 673 673 + 674 674 + if (!iio_device_claim_direct(indio_dev)) 675 675 + return -EBUSY; 676 676 + 677 677 + ret = regmap_update_bits(st->regmap, AD7768_REG_ANALOG2, 678 678 + AD7768_REG_ANALOG2_VCM_MSK, AD7768_VCM_OFF); 679 679 + iio_device_release_direct(indio_dev); 680 680 + 681 681 + return ret; 682 682 + } 683 683 + 684 684 + static int ad7768_vcm_is_enabled(struct regulator_dev *rdev) 685 685 + { 686 686 + struct iio_dev *indio_dev = rdev_get_drvdata(rdev); 687 687 + struct ad7768_state *st = iio_priv(indio_dev); 688 688 + int ret, val; 689 689 + 690 690 + if (!iio_device_claim_direct(indio_dev)) 691 691 + return -EBUSY; 692 692 + 693 693 + ret = regmap_read(st->regmap, AD7768_REG_ANALOG2, &val); 694 694 + iio_device_release_direct(indio_dev); 695 695 + if (ret) 696 696 + return ret; 697 697 + 698 698 + return FIELD_GET(AD7768_REG_ANALOG2_VCM_MSK, val) != AD7768_VCM_OFF; 699 699 + } 700 700 + 701 701 + static int ad7768_set_voltage_sel(struct regulator_dev *rdev, 702 702 + unsigned int selector) 703 703 + { 704 704 + unsigned int regval = AD7768_REG_ANALOG2_VCM(selector + 1); 705 705 + struct iio_dev *indio_dev = rdev_get_drvdata(rdev); 706 706 + struct ad7768_state *st = iio_priv(indio_dev); 707 707 + int ret; 708 708 + 709 709 + if (!iio_device_claim_direct(indio_dev)) 710 710 + return -EBUSY; 711 711 + 712 712 + ret = regmap_update_bits(st->regmap, AD7768_REG_ANALOG2, 713 713 + AD7768_REG_ANALOG2_VCM_MSK, regval); 714 714 + iio_device_release_direct(indio_dev); 715 715 + if (ret) 716 716 + return ret; 717 717 + 718 718 + st->vcm_output_sel = selector; 719 719 + 720 720 + return 0; 721 721 + } 722 722 + 723 723 + static int ad7768_get_voltage_sel(struct regulator_dev *rdev) 724 724 + { 725 725 + struct iio_dev *indio_dev = rdev_get_drvdata(rdev); 726 726 + struct ad7768_state *st = iio_priv(indio_dev); 727 727 + int ret, val; 728 728 + 729 729 + if (!iio_device_claim_direct(indio_dev)) 730 730 + return -EBUSY; 731 731 + 732 732 + ret = regmap_read(st->regmap, AD7768_REG_ANALOG2, &val); 733 733 + iio_device_release_direct(indio_dev); 734 734 + if (ret) 735 735 + return ret; 736 736 + 737 737 + val = FIELD_GET(AD7768_REG_ANALOG2_VCM_MSK, val); 738 738 + 739 739 + return clamp(val, 1, rdev->desc->n_voltages) - 1; 740 740 + } 741 741 + 742 742 + static const struct regulator_ops vcm_regulator_ops = { 743 743 + .enable = ad7768_vcm_enable, 744 744 + .disable = ad7768_vcm_disable, 745 745 + .is_enabled = ad7768_vcm_is_enabled, 746 746 + .list_voltage = regulator_list_voltage_table, 747 747 + .set_voltage_sel = ad7768_set_voltage_sel, 748 748 + .get_voltage_sel = ad7768_get_voltage_sel, 749 749 + }; 750 750 + 751 751 + static const unsigned int vcm_voltage_table[] = { 752 752 + 2500000, 753 753 + 2050000, 754 754 + 1650000, 755 755 + 1900000, 756 756 + 1100000, 757 757 + 900000, 758 758 + }; 759 759 + 760 760 + static const struct regulator_desc vcm_desc = { 761 761 + .name = "ad7768-1-vcm", 762 762 + .of_match = "vcm-output", 763 763 + .regulators_node = "regulators", 764 764 + .n_voltages = ARRAY_SIZE(vcm_voltage_table), 765 765 + .volt_table = vcm_voltage_table, 766 766 + .ops = &vcm_regulator_ops, 767 767 + .type = REGULATOR_VOLTAGE, 768 768 + .owner = THIS_MODULE, 769 769 + }; 770 770 + 771 771 + static int ad7768_register_regulators(struct device *dev, struct ad7768_state *st, 772 772 + struct iio_dev *indio_dev) 773 773 + { 774 774 + struct regulator_config config = { 775 775 + .dev = dev, 776 776 + .driver_data = indio_dev, 777 777 + }; 778 778 + int ret; 779 779 + 780 780 + /* Disable the regulator before registering it */ 781 781 + ret = regmap_update_bits(st->regmap, AD7768_REG_ANALOG2, 782 782 + AD7768_REG_ANALOG2_VCM_MSK, AD7768_VCM_OFF); 783 783 + if (ret) 784 784 + return ret; 785 785 + 786 786 + st->vcm_rdev = devm_regulator_register(dev, &vcm_desc, &config); 787 787 + if (IS_ERR(st->vcm_rdev)) 788 788 + return dev_err_probe(dev, PTR_ERR(st->vcm_rdev), 789 789 + "failed to register VCM regulator\n"); 790 790 + 791 791 + return 0; 792 792 + } 793 793 + 1193 794 static int ad7768_probe(struct spi_device *spi) 1194 795 { 1195 796 struct ad7768_state *st; ··· 1398 711 indio_dev->info = &ad7768_info; 1399 712 indio_dev->modes = INDIO_DIRECT_MODE; 1400 713 1401 1401 - ret = ad7768_setup(st); 714 714 + /* Register VCM output regulator */ 715 715 + ret = ad7768_register_regulators(&spi->dev, st, indio_dev); 716 716 + if (ret) 717 717 + return ret; 718 718 + 719 719 + ret = ad7768_setup(indio_dev); 1402 720 if (ret < 0) { 1403 721 dev_err(&spi->dev, "AD7768 setup failed\n"); 1404 722 return ret;

+192 -113

drivers/iio/adc/ad_sigma_delta.c

reviewed

··· 7 7 */ 8 8 9 9 #include <linux/align.h> 10 10 - #include <linux/interrupt.h> 10 10 + #include <linux/bitmap.h> 11 11 + #include <linux/bitops.h> 12 12 + #include <linux/cleanup.h> 13 13 + #include <linux/completion.h> 11 14 #include <linux/device.h> 12 12 - #include <linux/kernel.h> 13 13 - #include <linux/slab.h> 14 14 - #include <linux/spi/spi.h> 15 15 #include <linux/err.h> 16 16 + #include <linux/export.h> 17 17 + #include <linux/find.h> 18 18 + #include <linux/gpio/consumer.h> 19 19 + #include <linux/interrupt.h> 16 20 #include <linux/module.h> 17 17 - 18 18 - #include <linux/iio/iio.h> 19 19 - #include <linux/iio/sysfs.h> 20 20 - #include <linux/iio/buffer.h> 21 21 - #include <linux/iio/trigger.h> 22 22 - #include <linux/iio/trigger_consumer.h> 23 23 - #include <linux/iio/triggered_buffer.h> 24 24 - #include <linux/iio/adc/ad_sigma_delta.h> 25 25 - 21 21 + #include <linux/property.h> 22 22 + #include <linux/slab.h> 23 23 + #include <linux/spi/offload/consumer.h> 24 24 + #include <linux/spi/spi.h> 25 25 + #include <linux/spinlock.h> 26 26 + #include <linux/string.h> 27 27 + #include <linux/types.h> 26 28 #include <linux/unaligned.h> 27 29 30 30 + #include <linux/iio/adc/ad_sigma_delta.h> 31 31 + #include <linux/iio/buffer-dmaengine.h> 32 32 + #include <linux/iio/buffer.h> 33 33 + #include <linux/iio/iio.h> 34 34 + #include <linux/iio/trigger_consumer.h> 35 35 + #include <linux/iio/trigger.h> 36 36 + #include <linux/iio/triggered_buffer.h> 28 37 29 38 #define AD_SD_COMM_CHAN_MASK 0x3 30 39 ··· 49 40 * @sigma_delta: The sigma delta device 50 41 * @comm: New value for the communications register 51 42 */ 52 52 - void ad_sd_set_comm(struct ad_sigma_delta *sigma_delta, uint8_t comm) 43 43 + void ad_sd_set_comm(struct ad_sigma_delta *sigma_delta, u8 comm) 53 44 { 54 45 /* Some variants use the lower two bits of the communications register 55 46 * to select the channel */ ··· 70 61 int ad_sd_write_reg(struct ad_sigma_delta *sigma_delta, unsigned int reg, 71 62 unsigned int size, unsigned int val) 72 63 { 73 73 - uint8_t *data = sigma_delta->tx_buf; 64 64 + u8 *data = sigma_delta->tx_buf; 74 65 struct spi_transfer t = { 75 66 .tx_buf = data, 76 67 .len = size + 1, ··· 109 100 } 110 101 EXPORT_SYMBOL_NS_GPL(ad_sd_write_reg, "IIO_AD_SIGMA_DELTA"); 111 102 112 112 - static int ad_sd_read_reg_raw(struct ad_sigma_delta *sigma_delta, 113 113 - unsigned int reg, unsigned int size, uint8_t *val) 103 103 + static void ad_sd_set_read_reg_addr(struct ad_sigma_delta *sigma_delta, u8 reg, 104 104 + u8 *data) 114 105 { 115 115 - uint8_t *data = sigma_delta->tx_buf; 106 106 + data[0] = reg << sigma_delta->info->addr_shift; 107 107 + data[0] |= sigma_delta->info->read_mask; 108 108 + data[0] |= sigma_delta->comm; 109 109 + } 110 110 + 111 111 + static int ad_sd_read_reg_raw(struct ad_sigma_delta *sigma_delta, 112 112 + unsigned int reg, unsigned int size, u8 *val) 113 113 + { 114 114 + u8 *data = sigma_delta->tx_buf; 116 115 int ret; 117 116 struct spi_transfer t[] = { 118 117 { ··· 137 120 spi_message_init(&m); 138 121 139 122 if (sigma_delta->info->has_registers) { 140 140 - data[0] = reg << sigma_delta->info->addr_shift; 141 141 - data[0] |= sigma_delta->info->read_mask; 142 142 - data[0] |= sigma_delta->comm; 123 123 + ad_sd_set_read_reg_addr(sigma_delta, reg, data); 143 124 spi_message_add_tail(&t[0], &m); 144 125 } 145 126 spi_message_add_tail(&t[1], &m); ··· 202 187 int ad_sd_reset(struct ad_sigma_delta *sigma_delta) 203 188 { 204 189 unsigned int reset_length = sigma_delta->info->num_resetclks; 205 205 - uint8_t *buf; 206 190 unsigned int size; 191 191 + u8 *buf; 207 192 int ret; 208 193 209 209 - size = DIV_ROUND_UP(reset_length, 8); 194 194 + size = BITS_TO_BYTES(reset_length); 210 195 buf = kcalloc(size, sizeof(*buf), GFP_KERNEL); 211 196 if (!buf) 212 197 return -ENOMEM; ··· 296 281 if (sigma_delta->info->has_registers) { 297 282 unsigned int data_reg = sigma_delta->info->data_reg ?: AD_SD_REG_DATA; 298 283 299 299 - data[0] = data_reg << sigma_delta->info->addr_shift; 300 300 - data[0] |= sigma_delta->info->read_mask; 301 301 - data[0] |= sigma_delta->comm; 284 284 + ad_sd_set_read_reg_addr(sigma_delta, data_reg, data); 302 285 t[0].tx_buf = data; 303 286 spi_message_add_tail(&t[0], &m); 304 287 } ··· 433 420 data_reg = AD_SD_REG_DATA; 434 421 435 422 ret = ad_sd_read_reg(sigma_delta, data_reg, 436 436 - DIV_ROUND_UP(chan->scan_type.realbits + chan->scan_type.shift, 8), 423 423 + BITS_TO_BYTES(chan->scan_type.realbits + chan->scan_type.shift), 437 424 &raw_sample); 438 425 439 426 out: ··· 467 454 static int ad_sd_buffer_postenable(struct iio_dev *indio_dev) 468 455 { 469 456 struct ad_sigma_delta *sigma_delta = iio_device_get_drvdata(indio_dev); 470 470 - unsigned int i, slot, samples_buf_size; 471 471 - unsigned int channel; 472 472 - uint8_t *samples_buf; 457 457 + const struct iio_scan_type *scan_type = &indio_dev->channels[0].scan_type; 458 458 + struct spi_transfer *xfer = sigma_delta->sample_xfer; 459 459 + unsigned int i, slot, channel; 460 460 + u8 *samples_buf; 473 461 int ret; 474 462 475 463 if (sigma_delta->num_slots == 1) { ··· 497 483 sigma_delta->active_slots = slot; 498 484 sigma_delta->current_slot = 0; 499 485 500 500 - if (sigma_delta->active_slots > 1) { 501 501 - ret = ad_sigma_delta_append_status(sigma_delta, true); 502 502 - if (ret) 503 503 - return ret; 486 486 + if (ad_sigma_delta_has_spi_offload(sigma_delta)) { 487 487 + xfer[1].offload_flags = SPI_OFFLOAD_XFER_RX_STREAM; 488 488 + xfer[1].bits_per_word = scan_type->realbits; 489 489 + xfer[1].len = spi_bpw_to_bytes(scan_type->realbits); 490 490 + } else { 491 491 + unsigned int samples_buf_size, scan_size; 492 492 + 493 493 + if (sigma_delta->active_slots > 1) { 494 494 + ret = ad_sigma_delta_append_status(sigma_delta, true); 495 495 + if (ret) 496 496 + return ret; 497 497 + } 498 498 + 499 499 + samples_buf_size = 500 500 + ALIGN(slot * BITS_TO_BYTES(scan_type->storagebits), 501 501 + sizeof(s64)); 502 502 + samples_buf_size += sizeof(s64); 503 503 + samples_buf = devm_krealloc(&sigma_delta->spi->dev, 504 504 + sigma_delta->samples_buf, 505 505 + samples_buf_size, GFP_KERNEL); 506 506 + if (!samples_buf) 507 507 + return -ENOMEM; 508 508 + 509 509 + sigma_delta->samples_buf = samples_buf; 510 510 + scan_size = BITS_TO_BYTES(scan_type->realbits + scan_type->shift); 511 511 + /* For 24-bit data, there is an extra byte of padding. */ 512 512 + xfer[1].rx_buf = &sigma_delta->rx_buf[scan_size == 3 ? 1 : 0]; 513 513 + xfer[1].len = scan_size + (sigma_delta->status_appended ? 1 : 0); 514 514 + } 515 515 + xfer[1].cs_change = 1; 516 516 + 517 517 + if (sigma_delta->info->has_registers) { 518 518 + xfer[0].tx_buf = &sigma_delta->sample_addr; 519 519 + xfer[0].len = 1; 520 520 + 521 521 + ad_sd_set_read_reg_addr(sigma_delta, 522 522 + sigma_delta->info->data_reg ?: AD_SD_REG_DATA, 523 523 + &sigma_delta->sample_addr); 524 524 + spi_message_init_with_transfers(&sigma_delta->sample_msg, xfer, 2); 525 525 + } else { 526 526 + spi_message_init_with_transfers(&sigma_delta->sample_msg, 527 527 + &xfer[1], 1); 504 528 } 505 529 506 506 - samples_buf_size = ALIGN(slot * indio_dev->channels[0].scan_type.storagebits, 8); 507 507 - samples_buf_size += sizeof(int64_t); 508 508 - samples_buf = devm_krealloc(&sigma_delta->spi->dev, sigma_delta->samples_buf, 509 509 - samples_buf_size, GFP_KERNEL); 510 510 - if (!samples_buf) 511 511 - return -ENOMEM; 530 530 + sigma_delta->sample_msg.offload = sigma_delta->offload; 512 531 513 513 - sigma_delta->samples_buf = samples_buf; 532 532 + ret = spi_optimize_message(sigma_delta->spi, &sigma_delta->sample_msg); 533 533 + if (ret) 534 534 + return ret; 514 535 515 536 spi_bus_lock(sigma_delta->spi->controller); 516 537 sigma_delta->bus_locked = true; ··· 559 510 if (ret) 560 511 goto err_unlock; 561 512 562 562 - ad_sd_enable_irq(sigma_delta); 513 513 + if (ad_sigma_delta_has_spi_offload(sigma_delta)) { 514 514 + struct spi_offload_trigger_config config = { 515 515 + .type = SPI_OFFLOAD_TRIGGER_DATA_READY, 516 516 + }; 517 517 + 518 518 + ret = spi_offload_trigger_enable(sigma_delta->offload, 519 519 + sigma_delta->offload_trigger, 520 520 + &config); 521 521 + if (ret) 522 522 + goto err_unlock; 523 523 + } else { 524 524 + ad_sd_enable_irq(sigma_delta); 525 525 + } 563 526 564 527 return 0; 565 528 566 529 err_unlock: 567 530 spi_bus_unlock(sigma_delta->spi->controller); 531 531 + spi_unoptimize_message(&sigma_delta->sample_msg); 568 532 569 533 return ret; 570 534 } 571 535 572 572 - static int ad_sd_buffer_postdisable(struct iio_dev *indio_dev) 536 536 + static int ad_sd_buffer_predisable(struct iio_dev *indio_dev) 573 537 { 574 538 struct ad_sigma_delta *sigma_delta = iio_device_get_drvdata(indio_dev); 575 539 576 576 - reinit_completion(&sigma_delta->completion); 577 577 - wait_for_completion_timeout(&sigma_delta->completion, HZ); 540 540 + if (ad_sigma_delta_has_spi_offload(sigma_delta)) { 541 541 + spi_offload_trigger_disable(sigma_delta->offload, 542 542 + sigma_delta->offload_trigger); 543 543 + } else { 544 544 + reinit_completion(&sigma_delta->completion); 545 545 + wait_for_completion_timeout(&sigma_delta->completion, HZ); 578 546 579 579 - ad_sd_disable_irq(sigma_delta); 547 547 + ad_sd_disable_irq(sigma_delta); 548 548 + } 580 549 581 550 sigma_delta->keep_cs_asserted = false; 582 551 ad_sigma_delta_set_mode(sigma_delta, AD_SD_MODE_IDLE); ··· 604 537 605 538 ad_sigma_delta_disable_all(sigma_delta); 606 539 sigma_delta->bus_locked = false; 607 607 - return spi_bus_unlock(sigma_delta->spi->controller); 540 540 + spi_bus_unlock(sigma_delta->spi->controller); 541 541 + spi_unoptimize_message(&sigma_delta->sample_msg); 542 542 + 543 543 + return 0; 608 544 } 609 545 610 546 static irqreturn_t ad_sd_trigger_handler(int irq, void *p) 611 547 { 612 548 struct iio_poll_func *pf = p; 613 549 struct iio_dev *indio_dev = pf->indio_dev; 550 550 + const struct iio_scan_type *scan_type = &indio_dev->channels[0].scan_type; 614 551 struct ad_sigma_delta *sigma_delta = iio_device_get_drvdata(indio_dev); 615 615 - uint8_t *data = sigma_delta->rx_buf; 616 616 - unsigned int transfer_size; 552 552 + u8 *data = sigma_delta->rx_buf; 617 553 unsigned int sample_size; 618 554 unsigned int sample_pos; 619 555 unsigned int status_pos; 620 556 unsigned int reg_size; 621 621 - unsigned int data_reg; 557 557 + int ret; 622 558 623 623 - reg_size = indio_dev->channels[0].scan_type.realbits + 624 624 - indio_dev->channels[0].scan_type.shift; 625 625 - reg_size = DIV_ROUND_UP(reg_size, 8); 559 559 + reg_size = BITS_TO_BYTES(scan_type->realbits + scan_type->shift); 560 560 + /* For 24-bit data, there is an extra byte of padding. */ 561 561 + status_pos = reg_size + (reg_size == 3 ? 1 : 0); 626 562 627 627 - if (sigma_delta->info->data_reg != 0) 628 628 - data_reg = sigma_delta->info->data_reg; 629 629 - else 630 630 - data_reg = AD_SD_REG_DATA; 631 631 - 632 632 - /* Status word will be appended to the sample during transfer */ 633 633 - if (sigma_delta->status_appended) 634 634 - transfer_size = reg_size + 1; 635 635 - else 636 636 - transfer_size = reg_size; 637 637 - 638 638 - switch (reg_size) { 639 639 - case 4: 640 640 - case 2: 641 641 - case 1: 642 642 - status_pos = reg_size; 643 643 - ad_sd_read_reg_raw(sigma_delta, data_reg, transfer_size, &data[0]); 644 644 - break; 645 645 - case 3: 646 646 - /* 647 647 - * Data array after transfer will look like (if status is appended): 648 648 - * data[] = { [0][sample][sample][sample][status] } 649 649 - * Keeping the first byte 0 shifts the status position by 1 byte to the right. 650 650 - */ 651 651 - status_pos = reg_size + 1; 652 652 - 653 653 - /* We store 24 bit samples in a 32 bit word. Keep the upper 654 654 - * byte set to zero. */ 655 655 - ad_sd_read_reg_raw(sigma_delta, data_reg, transfer_size, &data[1]); 656 656 - break; 657 657 - 658 658 - default: 659 659 - dev_err_ratelimited(&indio_dev->dev, "Unsupported reg_size: %u\n", reg_size); 563 563 + ret = spi_sync_locked(sigma_delta->spi, &sigma_delta->sample_msg); 564 564 + if (ret) 660 565 goto irq_handled; 661 661 - } 662 566 663 567 /* 664 568 * For devices sampling only one channel at ··· 655 617 } 656 618 } 657 619 658 658 - sample_size = indio_dev->channels[0].scan_type.storagebits / 8; 620 620 + sample_size = BITS_TO_BYTES(scan_type->storagebits); 659 621 sample_pos = sample_size * sigma_delta->current_slot; 660 622 memcpy(&sigma_delta->samples_buf[sample_pos], data, sample_size); 661 623 sigma_delta->current_slot++; ··· 682 644 683 645 static const struct iio_buffer_setup_ops ad_sd_buffer_setup_ops = { 684 646 .postenable = &ad_sd_buffer_postenable, 685 685 - .postdisable = &ad_sd_buffer_postdisable, 647 647 + .predisable = &ad_sd_buffer_predisable, 686 648 .validate_scan_mask = &ad_sd_validate_scan_mask, 687 649 }; 688 650 ··· 709 671 if ((!sigma_delta->rdy_gpiod || gpiod_get_value(sigma_delta->rdy_gpiod)) && 710 672 ad_sd_disable_irq(sigma_delta)) { 711 673 complete(&sigma_delta->completion); 712 712 - iio_trigger_poll(sigma_delta->trig); 674 674 + if (sigma_delta->trig) 675 675 + iio_trigger_poll(sigma_delta->trig); 713 676 714 677 return IRQ_HANDLED; 715 678 } ··· 743 704 unsigned long irq_flags = irq_get_trigger_type(sigma_delta->irq_line); 744 705 int ret; 745 706 746 746 - if (dev != &sigma_delta->spi->dev) { 747 747 - dev_err(dev, "Trigger parent should be '%s', got '%s'\n", 748 748 - dev_name(dev), dev_name(&sigma_delta->spi->dev)); 749 749 - return -EFAULT; 750 750 - } 751 751 - 752 752 - sigma_delta->trig = devm_iio_trigger_alloc(dev, "%s-dev%d", indio_dev->name, 753 753 - iio_device_id(indio_dev)); 754 754 - if (sigma_delta->trig == NULL) 755 755 - return -ENOMEM; 756 756 - 757 707 init_completion(&sigma_delta->completion); 758 708 759 709 sigma_delta->irq_dis = true; ··· 762 734 if (ret) 763 735 return ret; 764 736 765 765 - iio_trigger_set_drvdata(sigma_delta->trig, sigma_delta); 737 737 + if (ad_sigma_delta_has_spi_offload(sigma_delta)) { 738 738 + sigma_delta->offload_trigger = 739 739 + devm_spi_offload_trigger_get(dev, sigma_delta->offload, 740 740 + SPI_OFFLOAD_TRIGGER_DATA_READY); 741 741 + if (IS_ERR(sigma_delta->offload_trigger)) 742 742 + return dev_err_probe(dev, PTR_ERR(sigma_delta->offload_trigger), 743 743 + "Failed to get SPI offload trigger\n"); 744 744 + } else { 745 745 + if (dev != &sigma_delta->spi->dev) 746 746 + return dev_err_probe(dev, -EFAULT, 747 747 + "Trigger parent should be '%s', got '%s'\n", 748 748 + dev_name(dev), dev_name(&sigma_delta->spi->dev)); 766 749 767 767 - ret = devm_iio_trigger_register(dev, sigma_delta->trig); 768 768 - if (ret) 769 769 - return ret; 750 750 + sigma_delta->trig = devm_iio_trigger_alloc(dev, "%s-dev%d", 751 751 + indio_dev->name, iio_device_id(indio_dev)); 752 752 + if (!sigma_delta->trig) 753 753 + return -ENOMEM; 770 754 771 771 - /* select default trigger */ 772 772 - indio_dev->trig = iio_trigger_get(sigma_delta->trig); 755 755 + iio_trigger_set_drvdata(sigma_delta->trig, sigma_delta); 756 756 + 757 757 + ret = devm_iio_trigger_register(dev, sigma_delta->trig); 758 758 + if (ret) 759 759 + return ret; 760 760 + 761 761 + /* select default trigger */ 762 762 + indio_dev->trig = iio_trigger_get(sigma_delta->trig); 763 763 + } 773 764 774 765 return 0; 775 766 } ··· 808 761 if (!sigma_delta->slots) 809 762 return -ENOMEM; 810 763 811 811 - ret = devm_iio_triggered_buffer_setup(dev, indio_dev, 812 812 - &iio_pollfunc_store_time, 813 813 - &ad_sd_trigger_handler, 814 814 - &ad_sd_buffer_setup_ops); 815 815 - if (ret) 816 816 - return ret; 764 764 + if (ad_sigma_delta_has_spi_offload(sigma_delta)) { 765 765 + struct dma_chan *rx_dma; 766 766 + 767 767 + rx_dma = devm_spi_offload_rx_stream_request_dma_chan(dev, 768 768 + sigma_delta->offload); 769 769 + if (IS_ERR(rx_dma)) 770 770 + return dev_err_probe(dev, PTR_ERR(rx_dma), 771 771 + "Failed to get RX DMA channel\n"); 772 772 + 773 773 + ret = devm_iio_dmaengine_buffer_setup_with_handle(dev, indio_dev, 774 774 + rx_dma, IIO_BUFFER_DIRECTION_IN); 775 775 + if (ret) 776 776 + return dev_err_probe(dev, ret, "Cannot setup DMA buffer\n"); 777 777 + 778 778 + indio_dev->setup_ops = &ad_sd_buffer_setup_ops; 779 779 + } else { 780 780 + ret = devm_iio_triggered_buffer_setup(dev, indio_dev, 781 781 + &iio_pollfunc_store_time, 782 782 + &ad_sd_trigger_handler, 783 783 + &ad_sd_buffer_setup_ops); 784 784 + if (ret) 785 785 + return ret; 786 786 + } 817 787 818 788 return devm_ad_sd_probe_trigger(dev, indio_dev); 819 789 } ··· 893 829 return sigma_delta->irq_line; 894 830 } 895 831 832 832 + if (info->supports_spi_offload) { 833 833 + struct spi_offload_config offload_config = { 834 834 + .capability_flags = SPI_OFFLOAD_CAP_TRIGGER | 835 835 + SPI_OFFLOAD_CAP_RX_STREAM_DMA, 836 836 + }; 837 837 + int ret; 838 838 + 839 839 + sigma_delta->offload = devm_spi_offload_get(&spi->dev, spi, 840 840 + &offload_config); 841 841 + ret = PTR_ERR_OR_ZERO(sigma_delta->offload); 842 842 + if (ret && ret != -ENODEV) 843 843 + return dev_err_probe(&spi->dev, ret, "Failed to get SPI offload\n"); 844 844 + } 845 845 + 896 846 iio_device_set_drvdata(indio_dev, sigma_delta); 897 847 898 848 return 0; ··· 916 838 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>"); 917 839 MODULE_DESCRIPTION("Analog Devices Sigma-Delta ADCs"); 918 840 MODULE_LICENSE("GPL v2"); 841 841 + MODULE_IMPORT_NS("IIO_DMAENGINE_BUFFER");

+95 -1

drivers/iio/adc/adi-axi-adc.c

reviewed

··· 44 44 #define ADI_AXI_ADC_REG_CONFIG_CMOS_OR_LVDS_N BIT(7) 45 45 46 46 #define ADI_AXI_ADC_REG_CTRL 0x0044 47 47 + #define ADI_AXI_ADC_CTRL_NUM_LANES_MSK GENMASK(12, 8) 48 48 + #define ADI_AXI_ADC_CTRL_SYNC_MSK BIT(3) 47 49 #define ADI_AXI_ADC_CTRL_DDR_EDGESEL_MASK BIT(1) 48 50 49 51 #define ADI_AXI_ADC_REG_CNTRL_3 0x004c ··· 54 52 #define AXI_AD485X_PACKET_FORMAT_20BIT 0x0 55 53 #define AXI_AD485X_PACKET_FORMAT_24BIT 0x1 56 54 #define AXI_AD485X_PACKET_FORMAT_32BIT 0x2 55 55 + #define AXI_AD408X_CNTRL_3_FILTER_EN_MSK BIT(0) 56 56 + 57 57 + #define ADI_AXI_ADC_REG_SYNC_STATUS 0x0068 58 58 + #define ADI_AXI_ADC_SYNC_STATUS_ADC_SYNC_MSK BIT(0) 57 59 58 60 #define ADI_AXI_ADC_REG_DRP_STATUS 0x0074 59 61 #define ADI_AXI_ADC_DRP_LOCKED BIT(17) ··· 85 79 86 80 #define ADI_AXI_ADC_REG_CHAN_CTRL_3(c) (0x0418 + (c) * 0x40) 87 81 #define ADI_AXI_ADC_CHAN_PN_SEL_MASK GENMASK(19, 16) 82 82 + 83 83 + #define ADI_AXI_ADC_REG_CHAN_USR_CTRL_2(c) (0x0424 + (c) * 0x40) 84 84 + #define ADI_AXI_ADC_CHAN_USR_CTRL_2_DEC_RATE_N_MASK GENMASK(15, 0) 88 85 89 86 /* IO Delays */ 90 87 #define ADI_AXI_ADC_REG_DELAY(l) (0x0800 + (l) * 0x4) ··· 251 242 } 252 243 } 253 244 245 245 + static int axi_adc_oversampling_ratio_set(struct iio_backend *back, 246 246 + unsigned int chan, 247 247 + unsigned int rate) 248 248 + { 249 249 + struct adi_axi_adc_state *st = iio_backend_get_priv(back); 250 250 + 251 251 + return regmap_update_bits(st->regmap, 252 252 + ADI_AXI_ADC_REG_CHAN_USR_CTRL_2(chan), 253 253 + ADI_AXI_ADC_CHAN_USR_CTRL_2_DEC_RATE_N_MASK, 254 254 + FIELD_PREP(ADI_AXI_ADC_CHAN_USR_CTRL_2_DEC_RATE_N_MASK, 255 255 + rate)); 256 256 + } 257 257 + 254 258 static int axi_adc_read_chan_status(struct adi_axi_adc_state *st, unsigned int chan, 255 259 unsigned int *status) 256 260 { ··· 403 381 } 404 382 405 383 static int axi_adc_ad485x_oversampling_ratio_set(struct iio_backend *back, 406 406 - unsigned int ratio) 384 384 + unsigned int chan, 385 385 + unsigned int ratio) 407 386 { 408 387 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 409 388 ··· 423 400 return regmap_set_bits(st->regmap, ADI_AXI_ADC_REG_CNTRL_3, 424 401 AXI_AD485X_CNTRL_3_OS_EN_MSK); 425 402 } 403 403 + } 404 404 + 405 405 + static int axi_adc_ad408x_filter_type_set(struct iio_backend *back, 406 406 + enum iio_backend_filter_type type) 407 407 + { 408 408 + struct adi_axi_adc_state *st = iio_backend_get_priv(back); 409 409 + 410 410 + if (type) 411 411 + return regmap_set_bits(st->regmap, ADI_AXI_ADC_REG_CNTRL_3, 412 412 + AXI_AD408X_CNTRL_3_FILTER_EN_MSK); 413 413 + 414 414 + return regmap_clear_bits(st->regmap, ADI_AXI_ADC_REG_CNTRL_3, 415 415 + AXI_AD408X_CNTRL_3_FILTER_EN_MSK); 416 416 + } 417 417 + 418 418 + static int axi_adc_ad408x_interface_data_align(struct iio_backend *back, 419 419 + u32 timeout_us) 420 420 + { 421 421 + struct adi_axi_adc_state *st = iio_backend_get_priv(back); 422 422 + u32 val; 423 423 + int ret; 424 424 + 425 425 + ret = regmap_set_bits(st->regmap, ADI_AXI_ADC_REG_CTRL, 426 426 + ADI_AXI_ADC_CTRL_SYNC_MSK); 427 427 + if (ret) 428 428 + return ret; 429 429 + 430 430 + return regmap_read_poll_timeout(st->regmap, ADI_AXI_ADC_REG_SYNC_STATUS, 431 431 + val, 432 432 + FIELD_GET(ADI_AXI_ADC_SYNC_STATUS_ADC_SYNC_MSK, val), 433 433 + 1, timeout_us); 434 434 + } 435 435 + 436 436 + static int axi_adc_num_lanes_set(struct iio_backend *back, 437 437 + unsigned int num_lanes) 438 438 + { 439 439 + struct adi_axi_adc_state *st = iio_backend_get_priv(back); 440 440 + 441 441 + if (!num_lanes) 442 442 + return -EINVAL; 443 443 + 444 444 + return regmap_update_bits(st->regmap, ADI_AXI_ADC_REG_CTRL, 445 445 + ADI_AXI_ADC_CTRL_NUM_LANES_MSK, 446 446 + FIELD_PREP(ADI_AXI_ADC_CTRL_NUM_LANES_MSK, num_lanes)); 426 447 } 427 448 428 449 static struct iio_buffer *axi_adc_request_buffer(struct iio_backend *back, ··· 616 549 .test_pattern_set = axi_adc_test_pattern_set, 617 550 .chan_status = axi_adc_chan_status, 618 551 .interface_type_get = axi_adc_interface_type_get, 552 552 + .oversampling_ratio_set = axi_adc_oversampling_ratio_set, 619 553 .debugfs_reg_access = iio_backend_debugfs_ptr(axi_adc_reg_access), 620 554 .debugfs_print_chan_status = iio_backend_debugfs_ptr(axi_adc_debugfs_print_chan_status), 621 555 }; ··· 648 580 static const struct iio_backend_info axi_ad485x = { 649 581 .name = "axi-ad485x", 650 582 .ops = &adi_ad485x_ops, 583 583 + }; 584 584 + 585 585 + static const struct iio_backend_ops adi_ad408x_ops = { 586 586 + .enable = axi_adc_enable, 587 587 + .disable = axi_adc_disable, 588 588 + .chan_enable = axi_adc_chan_enable, 589 589 + .chan_disable = axi_adc_chan_disable, 590 590 + .request_buffer = axi_adc_request_buffer, 591 591 + .free_buffer = axi_adc_free_buffer, 592 592 + .data_sample_trigger = axi_adc_data_sample_trigger, 593 593 + .filter_type_set = axi_adc_ad408x_filter_type_set, 594 594 + .interface_data_align = axi_adc_ad408x_interface_data_align, 595 595 + .num_lanes_set = axi_adc_num_lanes_set, 596 596 + .debugfs_reg_access = iio_backend_debugfs_ptr(axi_adc_reg_access), 597 597 + .debugfs_print_chan_status = iio_backend_debugfs_ptr(axi_adc_debugfs_print_chan_status), 598 598 + }; 599 599 + 600 600 + static const struct iio_backend_info axi_ad408x = { 601 601 + .name = "axi-ad408x", 602 602 + .ops = &adi_ad408x_ops, 651 603 }; 652 604 653 605 static int adi_axi_adc_probe(struct platform_device *pdev) ··· 785 697 .has_child_nodes = true, 786 698 }; 787 699 700 700 + static const struct axi_adc_info adi_axi_ad408x = { 701 701 + .version = ADI_AXI_PCORE_VER(10, 0, 'a'), 702 702 + .backend_info = &axi_ad408x, 703 703 + }; 704 704 + 788 705 /* Match table for of_platform binding */ 789 706 static const struct of_device_id adi_axi_adc_of_match[] = { 790 707 { .compatible = "adi,axi-adc-10.0.a", .data = &adc_generic }, 708 708 + { .compatible = "adi,axi-ad408x", .data = &adi_axi_ad408x }, 791 709 { .compatible = "adi,axi-ad485x", .data = &adi_axi_ad485x }, 792 710 { .compatible = "adi,axi-ad7606x", .data = &adc_ad7606 }, 793 711 { }

+5 -5

drivers/iio/adc/at91_adc.c

reviewed

··· 1226 1226 { .name = "external", .value = 0xd, .is_external = true }, 1227 1227 }; 1228 1228 1229 1229 - static struct at91_adc_caps at91sam9260_caps = { 1229 1229 + static const struct at91_adc_caps at91sam9260_caps = { 1230 1230 .calc_startup_ticks = calc_startup_ticks_9260, 1231 1231 .num_channels = 4, 1232 1232 .low_res_bits = 8, ··· 1250 1250 { .name = "continuous", .value = 0x6 }, 1251 1251 }; 1252 1252 1253 1253 - static struct at91_adc_caps at91sam9rl_caps = { 1253 1253 + static const struct at91_adc_caps at91sam9rl_caps = { 1254 1254 .has_ts = true, 1255 1255 .calc_startup_ticks = calc_startup_ticks_9260, /* same as 9260 */ 1256 1256 .num_channels = 6, ··· 1268 1268 .trigger_number = ARRAY_SIZE(at91sam9x5_triggers), 1269 1269 }; 1270 1270 1271 1271 - static struct at91_adc_caps at91sam9g45_caps = { 1271 1271 + static const struct at91_adc_caps at91sam9g45_caps = { 1272 1272 .has_ts = true, 1273 1273 .calc_startup_ticks = calc_startup_ticks_9260, /* same as 9260 */ 1274 1274 .num_channels = 8, ··· 1286 1286 .trigger_number = ARRAY_SIZE(at91sam9x5_triggers), 1287 1287 }; 1288 1288 1289 1289 - static struct at91_adc_caps at91sam9x5_caps = { 1289 1289 + static const struct at91_adc_caps at91sam9x5_caps = { 1290 1290 .has_ts = true, 1291 1291 .has_tsmr = true, 1292 1292 .ts_filter_average = 3, ··· 1308 1308 .trigger_number = ARRAY_SIZE(at91sam9x5_triggers), 1309 1309 }; 1310 1310 1311 1311 - static struct at91_adc_caps sama5d3_caps = { 1311 1311 + static const struct at91_adc_caps sama5d3_caps = { 1312 1312 .has_ts = true, 1313 1313 .has_tsmr = true, 1314 1314 .ts_filter_average = 3,

+1 -1

drivers/iio/adc/axp20x_adc.c

reviewed

··· 173 173 { } 174 174 }; 175 175 176 176 - static struct iio_map axp717_maps[] = { 176 176 + static const struct iio_map axp717_maps[] = { 177 177 { 178 178 .consumer_dev_name = "axp20x-usb-power-supply", 179 179 .consumer_channel = "vbus_v",

+1 -3

drivers/iio/adc/dln2-adc.c

reviewed

··· 467 467 struct { 468 468 __le16 values[DLN2_ADC_MAX_CHANNELS]; 469 469 aligned_s64 timestamp_space; 470 470 - } data; 470 470 + } data = { }; 471 471 struct dln2_adc_get_all_vals dev_data; 472 472 struct dln2_adc *dln2 = iio_priv(indio_dev); 473 473 const struct dln2_adc_demux_table *t; ··· 478 478 mutex_unlock(&dln2->mutex); 479 479 if (ret < 0) 480 480 goto done; 481 481 - 482 482 - memset(&data, 0, sizeof(data)); 483 481 484 482 /* Demux operation */ 485 483 for (i = 0; i < dln2->demux_count; ++i) {

+1 -3

drivers/iio/adc/hi8435.c

reviewed

··· 19 19 #include <linux/spi/spi.h> 20 20 #include <linux/gpio/consumer.h> 21 21 22 22 - #define DRV_NAME "hi8435" 23 23 - 24 22 /* Register offsets for HI-8435 */ 25 23 #define HI8435_CTRL_REG 0x02 26 24 #define HI8435_PSEN_REG 0x04 ··· 534 536 535 537 static struct spi_driver hi8435_driver = { 536 538 .driver = { 537 537 - .name = DRV_NAME, 539 539 + .name = "hi8435", 538 540 .of_match_table = hi8435_dt_ids, 539 541 }, 540 542 .probe = hi8435_probe,

+1 -3

drivers/iio/adc/max9611.c

reviewed

··· 25 25 #include <linux/mod_devicetable.h> 26 26 #include <linux/property.h> 27 27 28 28 - #define DRIVER_NAME "max9611" 29 29 - 30 28 /* max9611 register addresses */ 31 29 #define MAX9611_REG_CSA_DATA 0x00 32 30 #define MAX9611_REG_RS_DATA 0x02 ··· 551 553 552 554 static struct i2c_driver max9611_driver = { 553 555 .driver = { 554 554 - .name = DRIVER_NAME, 556 556 + .name = "max9611", 555 557 .of_match_table = max9611_of_table, 556 558 }, 557 559 .probe = max9611_probe,

+1 -1

drivers/iio/adc/mp2629_adc.c

reviewed

··· 44 44 struct device *dev; 45 45 }; 46 46 47 47 - static struct iio_chan_spec mp2629_channels[] = { 47 47 + static const struct iio_chan_spec mp2629_channels[] = { 48 48 MP2629_ADC_CHAN(BATT_VOLT, IIO_VOLTAGE), 49 49 MP2629_ADC_CHAN(SYSTEM_VOLT, IIO_VOLTAGE), 50 50 MP2629_ADC_CHAN(INPUT_VOLT, IIO_VOLTAGE),

+371 -69

drivers/iio/adc/mt6359-auxadc.c

reviewed

··· 7 7 * Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> 8 8 */ 9 9 10 10 + #include <linux/bitfield.h> 10 11 #include <linux/bits.h> 11 12 #include <linux/cleanup.h> 12 13 #include <linux/delay.h> ··· 25 24 #include <dt-bindings/iio/adc/mediatek,mt6357-auxadc.h> 26 25 #include <dt-bindings/iio/adc/mediatek,mt6358-auxadc.h> 27 26 #include <dt-bindings/iio/adc/mediatek,mt6359-auxadc.h> 27 27 + #include <dt-bindings/iio/adc/mediatek,mt6363-auxadc.h> 28 28 29 29 #define AUXADC_AVG_TIME_US 10 30 30 #define AUXADC_POLL_DELAY_US 100 31 31 #define AUXADC_TIMEOUT_US 32000 32 32 - #define AUXADC_VOLT_FULL 1800 33 32 #define IMP_STOP_DELAY_US 150 34 33 #define IMP_POLL_DELAY_US 1000 35 34 ··· 47 46 #define MT6359_IMP0_CONV_EN BIT(0) 48 47 #define MT6359_IMP1_IRQ_RDY BIT(15) 49 48 49 49 + #define MT6363_EXT_CHAN_MASK GENMASK(2, 0) 50 50 + #define MT6363_EXT_PURES_MASK GENMASK(4, 3) 51 51 + #define MT6363_PULLUP_RES_100K 0 52 52 + #define MT6363_PULLUP_RES_30K 1 53 53 + #define MT6363_PULLUP_RES_OPEN 3 54 54 + 50 55 enum mtk_pmic_auxadc_regs { 51 56 PMIC_AUXADC_ADC0, 52 57 PMIC_AUXADC_DCM_CON, ··· 61 54 PMIC_AUXADC_IMP3, 62 55 PMIC_AUXADC_RQST0, 63 56 PMIC_AUXADC_RQST1, 57 57 + PMIC_AUXADC_RQST3, 58 58 + PMIC_AUXADC_SDMADC_CON0, 64 59 PMIC_HK_TOP_WKEY, 65 60 PMIC_HK_TOP_RST_CON0, 66 61 PMIC_FGADC_R_CON0, ··· 84 75 PMIC_AUXADC_CHAN_TSX_TEMP, 85 76 PMIC_AUXADC_CHAN_HPOFS_CAL, 86 77 PMIC_AUXADC_CHAN_DCXO_TEMP, 78 78 + PMIC_AUXADC_CHAN_VTREF, 87 79 PMIC_AUXADC_CHAN_VBIF, 80 80 + PMIC_AUXADC_CHAN_VSYSSNS, 81 81 + PMIC_AUXADC_CHAN_VIN1, 82 82 + PMIC_AUXADC_CHAN_VIN2, 83 83 + PMIC_AUXADC_CHAN_VIN3, 84 84 + PMIC_AUXADC_CHAN_VIN4, 85 85 + PMIC_AUXADC_CHAN_VIN5, 86 86 + PMIC_AUXADC_CHAN_VIN6, 87 87 + PMIC_AUXADC_CHAN_VIN7, 88 88 PMIC_AUXADC_CHAN_IBAT, 89 89 PMIC_AUXADC_CHAN_VBAT, 90 90 PMIC_AUXADC_CHAN_MAX ··· 119 101 * struct mtk_pmic_auxadc_chan - PMIC AUXADC channel data 120 102 * @req_idx: Request register number 121 103 * @req_mask: Bitmask to activate a channel 104 104 + * @rdy_idx: Readiness register number 105 105 + * @rdy_mask: Bitmask to determine channel readiness 106 106 + * @ext_sel_idx: PMIC GPIO channel register number 107 107 + * @ext_sel_ch: PMIC GPIO number 108 108 + * @ext_sel_pu: PMIC GPIO channel pullup resistor selector 122 109 * @num_samples: Number of AUXADC samples for averaging 123 110 * @r_ratio: Resistance ratio fractional 124 111 */ 125 112 struct mtk_pmic_auxadc_chan { 126 113 u8 req_idx; 127 114 u16 req_mask; 115 115 + u8 rdy_idx; 116 116 + u16 rdy_mask; 117 117 + s8 ext_sel_idx; 118 118 + u8 ext_sel_ch; 119 119 + u8 ext_sel_pu; 128 120 u16 num_samples; 129 121 struct u8_fract r_ratio; 130 122 }; ··· 147 119 * @desc: PMIC AUXADC channel data 148 120 * @regs: List of PMIC specific registers 149 121 * @sec_unlock_key: Security unlock key for HK_TOP writes 122 122 + * @vref_mV: AUXADC Reference Voltage (VREF) in millivolts 150 123 * @imp_adc_num: ADC channel for battery impedance readings 124 124 + * @is_spmi: Defines whether this PMIC communicates over SPMI 125 125 + * @no_reset: If true, this PMIC does not support ADC reset 151 126 * @read_imp: Callback to read impedance channels 152 127 */ 153 128 struct mtk_pmic_auxadc_info { ··· 160 129 const struct mtk_pmic_auxadc_chan *desc; 161 130 const u16 *regs; 162 131 u16 sec_unlock_key; 132 132 + u32 vref_mV; 163 133 u8 imp_adc_num; 164 164 - int (*read_imp)(struct mt6359_auxadc *adc_dev, int *vbat, int *ibat); 134 134 + bool is_spmi; 135 135 + bool no_reset; 136 136 + int (*read_imp)(struct mt6359_auxadc *adc_dev, 137 137 + const struct iio_chan_spec *chan, int *vbat, int *ibat); 165 138 }; 166 139 167 167 - #define MTK_PMIC_ADC_CHAN(_ch_idx, _req_idx, _req_bit, _samples, _rnum, _rdiv) \ 140 140 + #define MTK_PMIC_ADC_EXT_CHAN(_ch_idx, _req_idx, _req_bit, _rdy_idx, _rdy_bit, \ 141 141 + _ext_sel_idx, _ext_sel_ch, _ext_sel_pu, \ 142 142 + _samples, _rnum, _rdiv) \ 168 143 [PMIC_AUXADC_CHAN_##_ch_idx] = { \ 169 144 .req_idx = _req_idx, \ 170 145 .req_mask = BIT(_req_bit), \ 146 146 + .rdy_idx = _rdy_idx, \ 147 147 + .rdy_mask = BIT(_rdy_bit), \ 148 148 + .ext_sel_idx = _ext_sel_idx, \ 149 149 + .ext_sel_ch = _ext_sel_ch, \ 150 150 + .ext_sel_pu = _ext_sel_pu, \ 171 151 .num_samples = _samples, \ 172 152 .r_ratio = { _rnum, _rdiv } \ 173 153 } 154 154 + 155 155 + #define MTK_PMIC_ADC_CHAN(_ch_idx, _req_idx, _req_bit, _rdy_idx, _rdy_bit, \ 156 156 + _samples, _rnum, _rdiv) \ 157 157 + MTK_PMIC_ADC_EXT_CHAN(_ch_idx, _req_idx, _req_bit, _rdy_idx, _rdy_bit, \ 158 158 + -1, 0, 0, _samples, _rnum, _rdiv) 174 159 175 160 #define MTK_PMIC_IIO_CHAN(_model, _name, _ch_idx, _adc_idx, _nbits, _ch_type) \ 176 161 { \ ··· 224 177 }; 225 178 226 179 static const struct mtk_pmic_auxadc_chan mt6357_auxadc_ch_desc[] = { 227 227 - MTK_PMIC_ADC_CHAN(BATADC, PMIC_AUXADC_RQST0, 0, 128, 3, 1), 228 228 - MTK_PMIC_ADC_CHAN(ISENSE, PMIC_AUXADC_RQST0, 0, 128, 3, 1), 229 229 - MTK_PMIC_ADC_CHAN(VCDT, PMIC_AUXADC_RQST0, 0, 8, 1, 1), 230 230 - MTK_PMIC_ADC_CHAN(BAT_TEMP, PMIC_AUXADC_RQST0, 3, 8, 1, 1), 231 231 - MTK_PMIC_ADC_CHAN(CHIP_TEMP, PMIC_AUXADC_RQST0, 4, 8, 1, 1), 232 232 - MTK_PMIC_ADC_CHAN(ACCDET, PMIC_AUXADC_RQST0, 5, 8, 1, 1), 233 233 - MTK_PMIC_ADC_CHAN(TSX_TEMP, PMIC_AUXADC_RQST0, 7, 128, 1, 1), 234 234 - MTK_PMIC_ADC_CHAN(HPOFS_CAL, PMIC_AUXADC_RQST0, 9, 256, 1, 1), 235 235 - MTK_PMIC_ADC_CHAN(DCXO_TEMP, PMIC_AUXADC_RQST0, 10, 16, 1, 1), 236 236 - MTK_PMIC_ADC_CHAN(VBIF, PMIC_AUXADC_RQST0, 11, 8, 1, 1), 237 237 - MTK_PMIC_ADC_CHAN(VCORE_TEMP, PMIC_AUXADC_RQST1, 5, 8, 1, 1), 238 238 - MTK_PMIC_ADC_CHAN(VPROC_TEMP, PMIC_AUXADC_RQST1, 6, 8, 1, 1), 180 180 + MTK_PMIC_ADC_CHAN(BATADC, PMIC_AUXADC_RQST0, 0, PMIC_AUXADC_IMP0, 8, 128, 3, 1), 181 181 + MTK_PMIC_ADC_CHAN(ISENSE, PMIC_AUXADC_RQST0, 0, PMIC_AUXADC_IMP0, 8, 128, 3, 1), 182 182 + MTK_PMIC_ADC_CHAN(VCDT, PMIC_AUXADC_RQST0, 0, PMIC_AUXADC_IMP0, 8, 8, 1, 1), 183 183 + MTK_PMIC_ADC_CHAN(BAT_TEMP, PMIC_AUXADC_RQST0, 3, PMIC_AUXADC_IMP0, 8, 8, 1, 1), 184 184 + MTK_PMIC_ADC_CHAN(CHIP_TEMP, PMIC_AUXADC_RQST0, 4, PMIC_AUXADC_IMP0, 8, 8, 1, 1), 185 185 + MTK_PMIC_ADC_CHAN(ACCDET, PMIC_AUXADC_RQST0, 5, PMIC_AUXADC_IMP0, 8, 8, 1, 1), 186 186 + MTK_PMIC_ADC_CHAN(TSX_TEMP, PMIC_AUXADC_RQST0, 7, PMIC_AUXADC_IMP0, 8, 128, 1, 1), 187 187 + MTK_PMIC_ADC_CHAN(HPOFS_CAL, PMIC_AUXADC_RQST0, 9, PMIC_AUXADC_IMP0, 8, 256, 1, 1), 188 188 + MTK_PMIC_ADC_CHAN(DCXO_TEMP, PMIC_AUXADC_RQST0, 10, PMIC_AUXADC_IMP0, 8, 16, 1, 1), 189 189 + MTK_PMIC_ADC_CHAN(VBIF, PMIC_AUXADC_RQST0, 11, PMIC_AUXADC_IMP0, 8, 8, 1, 1), 190 190 + MTK_PMIC_ADC_CHAN(VCORE_TEMP, PMIC_AUXADC_RQST1, 5, PMIC_AUXADC_IMP0, 8, 8, 1, 1), 191 191 + MTK_PMIC_ADC_CHAN(VPROC_TEMP, PMIC_AUXADC_RQST1, 6, PMIC_AUXADC_IMP0, 8, 8, 1, 1), 239 192 240 193 /* Battery impedance channels */ 241 241 - MTK_PMIC_ADC_CHAN(VBAT, 0, 0, 128, 3, 1), 194 194 + MTK_PMIC_ADC_CHAN(VBAT, 0, 0, PMIC_AUXADC_IMP0, 8, 128, 3, 1), 242 195 }; 243 196 244 197 static const u16 mt6357_auxadc_regs[] = { ··· 271 224 }; 272 225 273 226 static const struct mtk_pmic_auxadc_chan mt6358_auxadc_ch_desc[] = { 274 274 - MTK_PMIC_ADC_CHAN(BATADC, PMIC_AUXADC_RQST0, 0, 128, 3, 1), 275 275 - MTK_PMIC_ADC_CHAN(VCDT, PMIC_AUXADC_RQST0, 0, 8, 1, 1), 276 276 - MTK_PMIC_ADC_CHAN(BAT_TEMP, PMIC_AUXADC_RQST0, 3, 8, 2, 1), 277 277 - MTK_PMIC_ADC_CHAN(CHIP_TEMP, PMIC_AUXADC_RQST0, 4, 8, 1, 1), 278 278 - MTK_PMIC_ADC_CHAN(ACCDET, PMIC_AUXADC_RQST0, 5, 8, 1, 1), 279 279 - MTK_PMIC_ADC_CHAN(VDCXO, PMIC_AUXADC_RQST0, 6, 8, 3, 2), 280 280 - MTK_PMIC_ADC_CHAN(TSX_TEMP, PMIC_AUXADC_RQST0, 7, 128, 1, 1), 281 281 - MTK_PMIC_ADC_CHAN(HPOFS_CAL, PMIC_AUXADC_RQST0, 9, 256, 1, 1), 282 282 - MTK_PMIC_ADC_CHAN(DCXO_TEMP, PMIC_AUXADC_RQST0, 10, 16, 1, 1), 283 283 - MTK_PMIC_ADC_CHAN(VBIF, PMIC_AUXADC_RQST0, 11, 8, 2, 1), 284 284 - MTK_PMIC_ADC_CHAN(VCORE_TEMP, PMIC_AUXADC_RQST1, 8, 8, 1, 1), 285 285 - MTK_PMIC_ADC_CHAN(VPROC_TEMP, PMIC_AUXADC_RQST1, 9, 8, 1, 1), 286 286 - MTK_PMIC_ADC_CHAN(VGPU_TEMP, PMIC_AUXADC_RQST1, 10, 8, 1, 1), 227 227 + MTK_PMIC_ADC_CHAN(BATADC, PMIC_AUXADC_RQST0, 0, PMIC_AUXADC_IMP0, 8, 128, 3, 1), 228 228 + MTK_PMIC_ADC_CHAN(VCDT, PMIC_AUXADC_RQST0, 0, PMIC_AUXADC_IMP0, 8, 8, 1, 1), 229 229 + MTK_PMIC_ADC_CHAN(BAT_TEMP, PMIC_AUXADC_RQST0, 3, PMIC_AUXADC_IMP0, 8, 8, 2, 1), 230 230 + MTK_PMIC_ADC_CHAN(CHIP_TEMP, PMIC_AUXADC_RQST0, 4, PMIC_AUXADC_IMP0, 8, 8, 1, 1), 231 231 + MTK_PMIC_ADC_CHAN(ACCDET, PMIC_AUXADC_RQST0, 5, PMIC_AUXADC_IMP0, 8, 8, 1, 1), 232 232 + MTK_PMIC_ADC_CHAN(VDCXO, PMIC_AUXADC_RQST0, 6, PMIC_AUXADC_IMP0, 8, 8, 3, 2), 233 233 + MTK_PMIC_ADC_CHAN(TSX_TEMP, PMIC_AUXADC_RQST0, 7, PMIC_AUXADC_IMP0, 8, 128, 1, 1), 234 234 + MTK_PMIC_ADC_CHAN(HPOFS_CAL, PMIC_AUXADC_RQST0, 9, PMIC_AUXADC_IMP0, 8, 256, 1, 1), 235 235 + MTK_PMIC_ADC_CHAN(DCXO_TEMP, PMIC_AUXADC_RQST0, 10, PMIC_AUXADC_IMP0, 8, 16, 1, 1), 236 236 + MTK_PMIC_ADC_CHAN(VBIF, PMIC_AUXADC_RQST0, 11, PMIC_AUXADC_IMP0, 8, 8, 2, 1), 237 237 + MTK_PMIC_ADC_CHAN(VCORE_TEMP, PMIC_AUXADC_RQST1, 8, PMIC_AUXADC_IMP0, 8, 8, 1, 1), 238 238 + MTK_PMIC_ADC_CHAN(VPROC_TEMP, PMIC_AUXADC_RQST1, 9, PMIC_AUXADC_IMP0, 8, 8, 1, 1), 239 239 + MTK_PMIC_ADC_CHAN(VGPU_TEMP, PMIC_AUXADC_RQST1, 10, PMIC_AUXADC_IMP0, 8, 8, 1, 1), 287 240 288 241 /* Battery impedance channels */ 289 289 - MTK_PMIC_ADC_CHAN(VBAT, 0, 0, 128, 7, 2), 242 242 + MTK_PMIC_ADC_CHAN(VBAT, 0, 0, PMIC_AUXADC_IMP0, 8, 128, 7, 2), 290 243 }; 291 244 292 245 static const u16 mt6358_auxadc_regs[] = { ··· 319 272 }; 320 273 321 274 static const struct mtk_pmic_auxadc_chan mt6359_auxadc_ch_desc[] = { 322 322 - MTK_PMIC_ADC_CHAN(BATADC, PMIC_AUXADC_RQST0, 0, 128, 7, 2), 323 323 - MTK_PMIC_ADC_CHAN(BAT_TEMP, PMIC_AUXADC_RQST0, 3, 8, 5, 2), 324 324 - MTK_PMIC_ADC_CHAN(CHIP_TEMP, PMIC_AUXADC_RQST0, 4, 8, 1, 1), 325 325 - MTK_PMIC_ADC_CHAN(ACCDET, PMIC_AUXADC_RQST0, 5, 8, 1, 1), 326 326 - MTK_PMIC_ADC_CHAN(VDCXO, PMIC_AUXADC_RQST0, 6, 8, 3, 2), 327 327 - MTK_PMIC_ADC_CHAN(TSX_TEMP, PMIC_AUXADC_RQST0, 7, 128, 1, 1), 328 328 - MTK_PMIC_ADC_CHAN(HPOFS_CAL, PMIC_AUXADC_RQST0, 9, 256, 1, 1), 329 329 - MTK_PMIC_ADC_CHAN(DCXO_TEMP, PMIC_AUXADC_RQST0, 10, 16, 1, 1), 330 330 - MTK_PMIC_ADC_CHAN(VBIF, PMIC_AUXADC_RQST0, 11, 8, 5, 2), 331 331 - MTK_PMIC_ADC_CHAN(VCORE_TEMP, PMIC_AUXADC_RQST1, 8, 8, 1, 1), 332 332 - MTK_PMIC_ADC_CHAN(VPROC_TEMP, PMIC_AUXADC_RQST1, 9, 8, 1, 1), 333 333 - MTK_PMIC_ADC_CHAN(VGPU_TEMP, PMIC_AUXADC_RQST1, 10, 8, 1, 1), 275 275 + MTK_PMIC_ADC_CHAN(BATADC, PMIC_AUXADC_RQST0, 0, PMIC_AUXADC_IMP1, 15, 128, 7, 2), 276 276 + MTK_PMIC_ADC_CHAN(BAT_TEMP, PMIC_AUXADC_RQST0, 3, PMIC_AUXADC_IMP1, 15, 8, 5, 2), 277 277 + MTK_PMIC_ADC_CHAN(CHIP_TEMP, PMIC_AUXADC_RQST0, 4, PMIC_AUXADC_IMP1, 15, 8, 1, 1), 278 278 + MTK_PMIC_ADC_CHAN(ACCDET, PMIC_AUXADC_RQST0, 5, PMIC_AUXADC_IMP1, 15 ,8, 1, 1), 279 279 + MTK_PMIC_ADC_CHAN(VDCXO, PMIC_AUXADC_RQST0, 6, PMIC_AUXADC_IMP1, 15, 8, 3, 2), 280 280 + MTK_PMIC_ADC_CHAN(TSX_TEMP, PMIC_AUXADC_RQST0, 7, PMIC_AUXADC_IMP1, 15, 128, 1, 1), 281 281 + MTK_PMIC_ADC_CHAN(HPOFS_CAL, PMIC_AUXADC_RQST0, 9, PMIC_AUXADC_IMP1, 15, 256, 1, 1), 282 282 + MTK_PMIC_ADC_CHAN(DCXO_TEMP, PMIC_AUXADC_RQST0, 10, PMIC_AUXADC_IMP1, 15, 16, 1, 1), 283 283 + MTK_PMIC_ADC_CHAN(VBIF, PMIC_AUXADC_RQST0, 11, PMIC_AUXADC_IMP1, 15, 8, 5, 2), 284 284 + MTK_PMIC_ADC_CHAN(VCORE_TEMP, PMIC_AUXADC_RQST1, 8, PMIC_AUXADC_IMP1, 15, 8, 1, 1), 285 285 + MTK_PMIC_ADC_CHAN(VPROC_TEMP, PMIC_AUXADC_RQST1, 9, PMIC_AUXADC_IMP1, 15, 8, 1, 1), 286 286 + MTK_PMIC_ADC_CHAN(VGPU_TEMP, PMIC_AUXADC_RQST1, 10, PMIC_AUXADC_IMP1, 15, 8, 1, 1), 334 287 335 288 /* Battery impedance channels */ 336 336 - MTK_PMIC_ADC_CHAN(VBAT, 0, 0, 128, 7, 2), 337 337 - MTK_PMIC_ADC_CHAN(IBAT, 0, 0, 128, 7, 2), 289 289 + MTK_PMIC_ADC_CHAN(VBAT, 0, 0, PMIC_AUXADC_IMP1, 15, 128, 7, 2), 290 290 + MTK_PMIC_ADC_CHAN(IBAT, 0, 0, PMIC_AUXADC_IMP1, 15, 128, 7, 2), 338 291 }; 339 292 340 293 static const u16 mt6359_auxadc_regs[] = { ··· 349 302 [PMIC_AUXADC_IMP3] = 0x120e, 350 303 }; 351 304 305 305 + static const struct iio_chan_spec mt6363_auxadc_channels[] = { 306 306 + MTK_PMIC_IIO_CHAN(MT6363, bat_adc, BATADC, 0, 15, IIO_RESISTANCE), 307 307 + MTK_PMIC_IIO_CHAN(MT6363, cdt_v, VCDT, 2, 12, IIO_TEMP), 308 308 + MTK_PMIC_IIO_CHAN(MT6363, batt_temp, BAT_TEMP, 3, 12, IIO_TEMP), 309 309 + MTK_PMIC_IIO_CHAN(MT6363, chip_temp, CHIP_TEMP, 4, 12, IIO_TEMP), 310 310 + MTK_PMIC_IIO_CHAN(MT6363, sys_sns_v, VSYSSNS, 6, 15, IIO_VOLTAGE), 311 311 + MTK_PMIC_IIO_CHAN(MT6363, tref_v, VTREF, 11, 12, IIO_VOLTAGE), 312 312 + MTK_PMIC_IIO_CHAN(MT6363, vcore_temp, VCORE_TEMP, 38, 12, IIO_TEMP), 313 313 + MTK_PMIC_IIO_CHAN(MT6363, vproc_temp, VPROC_TEMP, 39, 12, IIO_TEMP), 314 314 + MTK_PMIC_IIO_CHAN(MT6363, vgpu_temp, VGPU_TEMP, 40, 12, IIO_TEMP), 315 315 + 316 316 + /* For VIN, ADC12 holds the result depending on which GPIO was activated */ 317 317 + MTK_PMIC_IIO_CHAN(MT6363, in1_v, VIN1, 45, 15, IIO_VOLTAGE), 318 318 + MTK_PMIC_IIO_CHAN(MT6363, in2_v, VIN2, 45, 15, IIO_VOLTAGE), 319 319 + MTK_PMIC_IIO_CHAN(MT6363, in3_v, VIN3, 45, 15, IIO_VOLTAGE), 320 320 + MTK_PMIC_IIO_CHAN(MT6363, in4_v, VIN4, 45, 15, IIO_VOLTAGE), 321 321 + MTK_PMIC_IIO_CHAN(MT6363, in5_v, VIN5, 45, 15, IIO_VOLTAGE), 322 322 + MTK_PMIC_IIO_CHAN(MT6363, in6_v, VIN6, 45, 15, IIO_VOLTAGE), 323 323 + MTK_PMIC_IIO_CHAN(MT6363, in7_v, VIN7, 45, 15, IIO_VOLTAGE), 324 324 + }; 325 325 + 326 326 + static const struct mtk_pmic_auxadc_chan mt6363_auxadc_ch_desc[] = { 327 327 + MTK_PMIC_ADC_CHAN(BATADC, PMIC_AUXADC_RQST0, 0, PMIC_AUXADC_ADC0, 15, 64, 4, 1), 328 328 + MTK_PMIC_ADC_CHAN(VCDT, PMIC_AUXADC_RQST0, 2, PMIC_AUXADC_ADC0, 15, 32, 1, 1), 329 329 + MTK_PMIC_ADC_CHAN(BAT_TEMP, PMIC_AUXADC_RQST0, 3, PMIC_AUXADC_ADC0, 15, 32, 3, 2), 330 330 + MTK_PMIC_ADC_CHAN(CHIP_TEMP, PMIC_AUXADC_RQST0, 4, PMIC_AUXADC_ADC0, 15, 32, 1, 1), 331 331 + MTK_PMIC_ADC_CHAN(VSYSSNS, PMIC_AUXADC_RQST1, 6, PMIC_AUXADC_ADC0, 15, 64, 3, 1), 332 332 + MTK_PMIC_ADC_CHAN(VTREF, PMIC_AUXADC_RQST1, 3, PMIC_AUXADC_ADC0, 15, 32, 3, 2), 333 333 + MTK_PMIC_ADC_CHAN(VCORE_TEMP, PMIC_AUXADC_RQST3, 0, PMIC_AUXADC_ADC0, 15, 32, 1, 1), 334 334 + MTK_PMIC_ADC_CHAN(VPROC_TEMP, PMIC_AUXADC_RQST3, 1, PMIC_AUXADC_ADC0, 15, 32, 1, 1), 335 335 + MTK_PMIC_ADC_CHAN(VGPU_TEMP, PMIC_AUXADC_RQST3, 2, PMIC_AUXADC_ADC0, 15, 32, 1, 1), 336 336 + 337 337 + MTK_PMIC_ADC_EXT_CHAN(VIN1, 338 338 + PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15, 339 339 + PMIC_AUXADC_SDMADC_CON0, 1, MT6363_PULLUP_RES_100K, 32, 1, 1), 340 340 + MTK_PMIC_ADC_EXT_CHAN(VIN2, 341 341 + PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15, 342 342 + PMIC_AUXADC_SDMADC_CON0, 2, MT6363_PULLUP_RES_100K, 32, 1, 1), 343 343 + MTK_PMIC_ADC_EXT_CHAN(VIN3, 344 344 + PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15, 345 345 + PMIC_AUXADC_SDMADC_CON0, 3, MT6363_PULLUP_RES_100K, 32, 1, 1), 346 346 + MTK_PMIC_ADC_EXT_CHAN(VIN4, 347 347 + PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15, 348 348 + PMIC_AUXADC_SDMADC_CON0, 4, MT6363_PULLUP_RES_100K, 32, 1, 1), 349 349 + MTK_PMIC_ADC_EXT_CHAN(VIN5, 350 350 + PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15, 351 351 + PMIC_AUXADC_SDMADC_CON0, 5, MT6363_PULLUP_RES_100K, 32, 1, 1), 352 352 + MTK_PMIC_ADC_EXT_CHAN(VIN6, 353 353 + PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15, 354 354 + PMIC_AUXADC_SDMADC_CON0, 6, MT6363_PULLUP_RES_100K, 32, 1, 1), 355 355 + MTK_PMIC_ADC_EXT_CHAN(VIN7, 356 356 + PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15, 357 357 + PMIC_AUXADC_SDMADC_CON0, 7, MT6363_PULLUP_RES_100K, 32, 1, 1), 358 358 + }; 359 359 + 360 360 + static const u16 mt6363_auxadc_regs[] = { 361 361 + [PMIC_AUXADC_RQST0] = 0x1108, 362 362 + [PMIC_AUXADC_RQST1] = 0x1109, 363 363 + [PMIC_AUXADC_RQST3] = 0x110c, 364 364 + [PMIC_AUXADC_ADC0] = 0x1088, 365 365 + [PMIC_AUXADC_IMP0] = 0x1208, 366 366 + [PMIC_AUXADC_IMP1] = 0x1209, 367 367 + }; 368 368 + 369 369 + static const struct iio_chan_spec mt6373_auxadc_channels[] = { 370 370 + MTK_PMIC_IIO_CHAN(MT6363, chip_temp, CHIP_TEMP, 4, 12, IIO_TEMP), 371 371 + MTK_PMIC_IIO_CHAN(MT6363, vcore_temp, VCORE_TEMP, 38, 12, IIO_TEMP), 372 372 + MTK_PMIC_IIO_CHAN(MT6363, vproc_temp, VPROC_TEMP, 39, 12, IIO_TEMP), 373 373 + MTK_PMIC_IIO_CHAN(MT6363, vgpu_temp, VGPU_TEMP, 40, 12, IIO_TEMP), 374 374 + 375 375 + /* For VIN, ADC12 holds the result depending on which GPIO was activated */ 376 376 + MTK_PMIC_IIO_CHAN(MT6363, in1_v, VIN1, 45, 15, IIO_VOLTAGE), 377 377 + MTK_PMIC_IIO_CHAN(MT6363, in2_v, VIN2, 45, 15, IIO_VOLTAGE), 378 378 + MTK_PMIC_IIO_CHAN(MT6363, in3_v, VIN3, 45, 15, IIO_VOLTAGE), 379 379 + MTK_PMIC_IIO_CHAN(MT6363, in4_v, VIN4, 45, 15, IIO_VOLTAGE), 380 380 + MTK_PMIC_IIO_CHAN(MT6363, in5_v, VIN5, 45, 15, IIO_VOLTAGE), 381 381 + }; 382 382 + 383 383 + static const struct mtk_pmic_auxadc_chan mt6373_auxadc_ch_desc[] = { 384 384 + MTK_PMIC_ADC_CHAN(CHIP_TEMP, PMIC_AUXADC_RQST0, 4, PMIC_AUXADC_ADC0, 15, 32, 1, 1), 385 385 + MTK_PMIC_ADC_CHAN(VCORE_TEMP, PMIC_AUXADC_RQST3, 0, PMIC_AUXADC_ADC0, 15, 32, 1, 1), 386 386 + MTK_PMIC_ADC_CHAN(VPROC_TEMP, PMIC_AUXADC_RQST3, 1, PMIC_AUXADC_ADC0, 15, 32, 1, 1), 387 387 + MTK_PMIC_ADC_CHAN(VGPU_TEMP, PMIC_AUXADC_RQST3, 2, PMIC_AUXADC_ADC0, 15, 32, 1, 1), 388 388 + 389 389 + MTK_PMIC_ADC_EXT_CHAN(VIN1, 390 390 + PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15, 391 391 + PMIC_AUXADC_SDMADC_CON0, 1, MT6363_PULLUP_RES_30K, 32, 1, 1), 392 392 + MTK_PMIC_ADC_EXT_CHAN(VIN2, 393 393 + PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15, 394 394 + PMIC_AUXADC_SDMADC_CON0, 2, MT6363_PULLUP_RES_OPEN, 32, 1, 1), 395 395 + MTK_PMIC_ADC_EXT_CHAN(VIN3, 396 396 + PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15, 397 397 + PMIC_AUXADC_SDMADC_CON0, 3, MT6363_PULLUP_RES_OPEN, 32, 1, 1), 398 398 + MTK_PMIC_ADC_EXT_CHAN(VIN4, 399 399 + PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15, 400 400 + PMIC_AUXADC_SDMADC_CON0, 4, MT6363_PULLUP_RES_OPEN, 32, 1, 1), 401 401 + MTK_PMIC_ADC_EXT_CHAN(VIN5, 402 402 + PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15, 403 403 + PMIC_AUXADC_SDMADC_CON0, 5, MT6363_PULLUP_RES_OPEN, 32, 1, 1), 404 404 + }; 405 405 + 352 406 static void mt6358_stop_imp_conv(struct mt6359_auxadc *adc_dev) 353 407 { 354 408 const struct mtk_pmic_auxadc_info *cinfo = adc_dev->chip_info; ··· 461 313 regmap_clear_bits(regmap, cinfo->regs[PMIC_AUXADC_DCM_CON], MT6358_DCM_CK_SW_EN); 462 314 } 463 315 464 464 - static int mt6358_start_imp_conv(struct mt6359_auxadc *adc_dev) 316 316 + static int mt6358_start_imp_conv(struct mt6359_auxadc *adc_dev, const struct iio_chan_spec *chan) 465 317 { 466 318 const struct mtk_pmic_auxadc_info *cinfo = adc_dev->chip_info; 319 319 + const struct mtk_pmic_auxadc_chan *desc = &cinfo->desc[chan->scan_index]; 467 320 struct regmap *regmap = adc_dev->regmap; 468 321 u32 val; 469 322 int ret; ··· 472 323 regmap_set_bits(regmap, cinfo->regs[PMIC_AUXADC_DCM_CON], MT6358_DCM_CK_SW_EN); 473 324 regmap_set_bits(regmap, cinfo->regs[PMIC_AUXADC_IMP1], MT6358_IMP1_AUTOREPEAT_EN); 474 325 475 475 - ret = regmap_read_poll_timeout(adc_dev->regmap, cinfo->regs[PMIC_AUXADC_IMP0], 476 476 - val, val & MT6358_IMP0_IRQ_RDY, 326 326 + ret = regmap_read_poll_timeout(regmap, cinfo->regs[desc->rdy_idx], 327 327 + val, val & desc->rdy_mask, 477 328 IMP_POLL_DELAY_US, AUXADC_TIMEOUT_US); 478 329 if (ret) { 479 330 mt6358_stop_imp_conv(adc_dev); ··· 483 334 return 0; 484 335 } 485 336 486 486 - static int mt6358_read_imp(struct mt6359_auxadc *adc_dev, int *vbat, int *ibat) 337 337 + static int mt6358_read_imp(struct mt6359_auxadc *adc_dev, 338 338 + const struct iio_chan_spec *chan, int *vbat, int *ibat) 487 339 { 488 340 const struct mtk_pmic_auxadc_info *cinfo = adc_dev->chip_info; 489 341 struct regmap *regmap = adc_dev->regmap; ··· 492 342 u32 val_v; 493 343 int ret; 494 344 495 495 - ret = mt6358_start_imp_conv(adc_dev); 345 345 + ret = mt6358_start_imp_conv(adc_dev, chan); 496 346 if (ret) 497 347 return ret; 498 348 ··· 509 359 return 0; 510 360 } 511 361 512 512 - static int mt6359_read_imp(struct mt6359_auxadc *adc_dev, int *vbat, int *ibat) 362 362 + static int mt6359_read_imp(struct mt6359_auxadc *adc_dev, 363 363 + const struct iio_chan_spec *chan, int *vbat, int *ibat) 513 364 { 514 365 const struct mtk_pmic_auxadc_info *cinfo = adc_dev->chip_info; 366 366 + const struct mtk_pmic_auxadc_chan *desc = &cinfo->desc[chan->scan_index]; 515 367 struct regmap *regmap = adc_dev->regmap; 516 368 u32 val, val_v, val_i; 517 369 int ret; 518 370 519 371 /* Start conversion */ 520 372 regmap_write(regmap, cinfo->regs[PMIC_AUXADC_IMP0], MT6359_IMP0_CONV_EN); 521 521 - ret = regmap_read_poll_timeout(regmap, cinfo->regs[PMIC_AUXADC_IMP1], 522 522 - val, val & MT6359_IMP1_IRQ_RDY, 373 373 + ret = regmap_read_poll_timeout(regmap, cinfo->regs[desc->rdy_idx], 374 374 + val, val & desc->rdy_mask, 523 375 IMP_POLL_DELAY_US, AUXADC_TIMEOUT_US); 524 376 525 377 /* Stop conversion regardless of the result */ ··· 556 404 .regs = mt6357_auxadc_regs, 557 405 .imp_adc_num = MT6357_IMP_ADC_NUM, 558 406 .read_imp = mt6358_read_imp, 407 407 + .vref_mV = 1800, 559 408 }; 560 409 561 410 static const struct mtk_pmic_auxadc_info mt6358_chip_info = { ··· 567 414 .regs = mt6358_auxadc_regs, 568 415 .imp_adc_num = MT6358_IMP_ADC_NUM, 569 416 .read_imp = mt6358_read_imp, 417 417 + .vref_mV = 1800, 570 418 }; 571 419 572 420 static const struct mtk_pmic_auxadc_info mt6359_chip_info = { ··· 578 424 .regs = mt6359_auxadc_regs, 579 425 .sec_unlock_key = 0x6359, 580 426 .read_imp = mt6359_read_imp, 427 427 + .vref_mV = 1800, 428 428 + }; 429 429 + 430 430 + static const struct mtk_pmic_auxadc_info mt6363_chip_info = { 431 431 + .model_name = "MT6363", 432 432 + .channels = mt6363_auxadc_channels, 433 433 + .num_channels = ARRAY_SIZE(mt6363_auxadc_channels), 434 434 + .desc = mt6363_auxadc_ch_desc, 435 435 + .regs = mt6363_auxadc_regs, 436 436 + .is_spmi = true, 437 437 + .no_reset = true, 438 438 + .vref_mV = 1840, 439 439 + }; 440 440 + 441 441 + static const struct mtk_pmic_auxadc_info mt6373_chip_info = { 442 442 + .model_name = "MT6373", 443 443 + .channels = mt6373_auxadc_channels, 444 444 + .num_channels = ARRAY_SIZE(mt6373_auxadc_channels), 445 445 + .desc = mt6373_auxadc_ch_desc, 446 446 + .regs = mt6363_auxadc_regs, 447 447 + .is_spmi = true, 448 448 + .no_reset = true, 449 449 + .vref_mV = 1840, 581 450 }; 582 451 583 452 static void mt6359_auxadc_reset(struct mt6359_auxadc *adc_dev) 584 453 { 585 454 const struct mtk_pmic_auxadc_info *cinfo = adc_dev->chip_info; 586 455 struct regmap *regmap = adc_dev->regmap; 456 456 + 457 457 + /* Some PMICs do not support reset */ 458 458 + if (cinfo->no_reset) 459 459 + return; 587 460 588 461 /* Unlock HK_TOP writes */ 589 462 if (cinfo->sec_unlock_key) ··· 627 446 regmap_write(regmap, cinfo->regs[PMIC_HK_TOP_WKEY], 0); 628 447 } 629 448 630 630 - static int mt6359_auxadc_read_adc(struct mt6359_auxadc *adc_dev, 631 631 - const struct iio_chan_spec *chan, int *out) 449 449 + /** 450 450 + * mt6359_auxadc_sample_adc_val() - Start ADC channel sampling and read value 451 451 + * @adc_dev: Main driver structure 452 452 + * @chan: IIO Channel spec for requested ADC 453 453 + * @out: Preallocated variable to store the value read from HW 454 454 + * 455 455 + * This function starts the sampling for an ADC channel, waits until all 456 456 + * of the samples are averaged and then reads the value from the HW. 457 457 + * 458 458 + * Note that the caller must stop the ADC sampling on its own, as this 459 459 + * function *never* stops it. 460 460 + * 461 461 + * Return: 462 462 + * Negative number for error; 463 463 + * Upon success returns zero and writes the read value to *out. 464 464 + */ 465 465 + static int mt6359_auxadc_sample_adc_val(struct mt6359_auxadc *adc_dev, 466 466 + const struct iio_chan_spec *chan, u32 *out) 632 467 { 633 468 const struct mtk_pmic_auxadc_info *cinfo = adc_dev->chip_info; 634 469 const struct mtk_pmic_auxadc_chan *desc = &cinfo->desc[chan->scan_index]; 635 470 struct regmap *regmap = adc_dev->regmap; 636 636 - u32 val; 471 471 + u32 reg, rdy_mask, val, lval; 637 472 int ret; 638 473 639 474 /* Request to start sampling for ADC channel */ ··· 660 463 /* Wait until all samples are averaged */ 661 464 fsleep(desc->num_samples * AUXADC_AVG_TIME_US); 662 465 663 663 - ret = regmap_read_poll_timeout(regmap, 664 664 - cinfo->regs[PMIC_AUXADC_ADC0] + (chan->address << 1), 665 665 - val, val & PMIC_AUXADC_RDY_BIT, 466 466 + reg = cinfo->regs[PMIC_AUXADC_ADC0] + (chan->address << 1); 467 467 + rdy_mask = PMIC_AUXADC_RDY_BIT; 468 468 + 469 469 + /* 470 470 + * Even though for both PWRAP and SPMI cases the ADC HW signals that 471 471 + * the data is ready by setting AUXADC_RDY_BIT, for SPMI the register 472 472 + * read is only 8 bits long: for this case, the check has to be done 473 473 + * on the ADC(x)_H register (high bits) and the rdy_mask needs to be 474 474 + * shifted to the right by the same 8 bits. 475 475 + */ 476 476 + if (cinfo->is_spmi) { 477 477 + rdy_mask >>= 8; 478 478 + reg += 1; 479 479 + } 480 480 + 481 481 + ret = regmap_read_poll_timeout(regmap, reg, val, val & rdy_mask, 666 482 AUXADC_POLL_DELAY_US, AUXADC_TIMEOUT_US); 483 483 + if (ret) { 484 484 + dev_dbg(adc_dev->dev, "ADC read timeout for chan %lu\n", chan->address); 485 485 + return ret; 486 486 + } 487 487 + 488 488 + if (cinfo->is_spmi) { 489 489 + ret = regmap_read(regmap, reg - 1, &lval); 490 490 + if (ret) 491 491 + return ret; 492 492 + 493 493 + val = (val << 8) | lval; 494 494 + } 495 495 + 496 496 + *out = val; 497 497 + return 0; 498 498 + } 499 499 + 500 500 + static int mt6359_auxadc_read_adc(struct mt6359_auxadc *adc_dev, 501 501 + const struct iio_chan_spec *chan, int *out) 502 502 + { 503 503 + const struct mtk_pmic_auxadc_info *cinfo = adc_dev->chip_info; 504 504 + const struct mtk_pmic_auxadc_chan *desc = &cinfo->desc[chan->scan_index]; 505 505 + struct regmap *regmap = adc_dev->regmap; 506 506 + int ret, adc_stop_err; 507 507 + u8 ext_sel; 508 508 + u32 val; 509 509 + 510 510 + if (desc->ext_sel_idx >= 0) { 511 511 + ext_sel = FIELD_PREP(MT6363_EXT_PURES_MASK, desc->ext_sel_pu); 512 512 + ext_sel |= FIELD_PREP(MT6363_EXT_CHAN_MASK, desc->ext_sel_ch); 513 513 + 514 514 + ret = regmap_update_bits(regmap, cinfo->regs[desc->ext_sel_idx], 515 515 + MT6363_EXT_PURES_MASK | MT6363_EXT_CHAN_MASK, 516 516 + ext_sel); 517 517 + if (ret) 518 518 + return ret; 519 519 + } 520 520 + 521 521 + /* 522 522 + * Get sampled value, then stop sampling unconditionally; the gathered 523 523 + * value is good regardless of if the ADC could be stopped. 524 524 + * 525 525 + * Note that if the ADC cannot be stopped but sampling was ok, this 526 526 + * function will not return any error, but will set the timed_out 527 527 + * status: this is not critical, as the ADC may auto recover and auto 528 528 + * stop after some time (depending on the PMIC model); if not, the next 529 529 + * read attempt will return -ETIMEDOUT and, for models that support it, 530 530 + * reset will be triggered. 531 531 + */ 532 532 + ret = mt6359_auxadc_sample_adc_val(adc_dev, chan, &val); 533 533 + 534 534 + adc_stop_err = regmap_write(regmap, cinfo->regs[desc->req_idx], 0); 535 535 + if (adc_stop_err) { 536 536 + dev_warn(adc_dev->dev, "Could not stop the ADC: %d\n,", adc_stop_err); 537 537 + adc_dev->timed_out = true; 538 538 + } 539 539 + 540 540 + /* If any sampling error occurred, the retrieved value is invalid */ 667 541 if (ret) 668 542 return ret; 669 543 670 670 - /* Stop sampling */ 671 671 - regmap_write(regmap, cinfo->regs[desc->req_idx], 0); 544 544 + /* ...and deactivate the ADC GPIO if previously done */ 545 545 + if (desc->ext_sel_idx >= 0) { 546 546 + ext_sel = FIELD_PREP(MT6363_EXT_PURES_MASK, MT6363_PULLUP_RES_OPEN); 672 547 548 548 + ret = regmap_update_bits(regmap, cinfo->regs[desc->ext_sel_idx], 549 549 + MT6363_EXT_PURES_MASK, ext_sel); 550 550 + if (ret) 551 551 + return ret; 552 552 + } 553 553 + 554 554 + /* Everything went fine, give back the ADC reading */ 673 555 *out = val & GENMASK(chan->scan_type.realbits - 1, 0); 674 556 return 0; 675 557 } ··· 769 493 int ret; 770 494 771 495 if (mask == IIO_CHAN_INFO_SCALE) { 772 772 - *val = desc->r_ratio.numerator * AUXADC_VOLT_FULL; 496 496 + *val = desc->r_ratio.numerator * cinfo->vref_mV; 773 497 774 498 if (desc->r_ratio.denominator > 1) { 775 499 *val2 = desc->r_ratio.denominator; ··· 782 506 scoped_guard(mutex, &adc_dev->lock) { 783 507 switch (chan->scan_index) { 784 508 case PMIC_AUXADC_CHAN_IBAT: 785 785 - ret = adc_dev->chip_info->read_imp(adc_dev, NULL, val); 509 509 + if (!adc_dev->chip_info->read_imp) 510 510 + return -EOPNOTSUPP; 511 511 + 512 512 + ret = adc_dev->chip_info->read_imp(adc_dev, chan, NULL, val); 786 513 break; 787 514 case PMIC_AUXADC_CHAN_VBAT: 788 788 - ret = adc_dev->chip_info->read_imp(adc_dev, val, NULL); 515 515 + if (!adc_dev->chip_info->read_imp) 516 516 + return -EOPNOTSUPP; 517 517 + 518 518 + ret = adc_dev->chip_info->read_imp(adc_dev, chan, val, NULL); 789 519 break; 790 520 default: 791 521 ret = mt6359_auxadc_read_adc(adc_dev, chan, val); ··· 825 543 826 544 static int mt6359_auxadc_probe(struct platform_device *pdev) 827 545 { 546 546 + const struct mtk_pmic_auxadc_info *chip_info; 828 547 struct device *dev = &pdev->dev; 829 829 - struct device *mt6397_mfd_dev = dev->parent; 548 548 + struct device *mfd_dev = dev->parent; 830 549 struct mt6359_auxadc *adc_dev; 831 550 struct iio_dev *indio_dev; 551 551 + struct device *regmap_dev; 832 552 struct regmap *regmap; 833 553 int ret; 834 554 555 555 + chip_info = device_get_match_data(dev); 556 556 + if (!chip_info) 557 557 + return -EINVAL; 558 558 + /* 559 559 + * The regmap for this device has to be acquired differently for 560 560 + * SoC PMIC Wrapper and SPMI PMIC cases: 561 561 + * 562 562 + * If this is under SPMI, the regmap comes from the direct parent of 563 563 + * this driver: this_device->parent(mfd). 564 564 + * ... or ... 565 565 + * If this is under the SoC PMIC Wrapper, the regmap comes from the 566 566 + * parent of the MT6397 MFD: this_device->parent(mfd)->parent(pwrap) 567 567 + */ 568 568 + if (chip_info->is_spmi) 569 569 + regmap_dev = mfd_dev; 570 570 + else 571 571 + regmap_dev = mfd_dev->parent; 572 572 + 573 573 + 835 574 /* Regmap is from SoC PMIC Wrapper, parent of the mt6397 MFD */ 836 836 - regmap = dev_get_regmap(mt6397_mfd_dev->parent, NULL); 575 575 + regmap = dev_get_regmap(regmap_dev, NULL); 837 576 if (!regmap) 838 577 return dev_err_probe(dev, -ENODEV, "Failed to get regmap\n"); 839 578 ··· 865 562 adc_dev = iio_priv(indio_dev); 866 563 adc_dev->regmap = regmap; 867 564 adc_dev->dev = dev; 868 868 - 869 869 - adc_dev->chip_info = device_get_match_data(dev); 870 870 - if (!adc_dev->chip_info) 871 871 - return -EINVAL; 565 565 + adc_dev->chip_info = chip_info; 872 566 873 567 mutex_init(&adc_dev->lock); 874 568 ··· 888 588 { .compatible = "mediatek,mt6357-auxadc", .data = &mt6357_chip_info }, 889 589 { .compatible = "mediatek,mt6358-auxadc", .data = &mt6358_chip_info }, 890 590 { .compatible = "mediatek,mt6359-auxadc", .data = &mt6359_chip_info }, 591 591 + { .compatible = "mediatek,mt6363-auxadc", .data = &mt6363_chip_info }, 592 592 + { .compatible = "mediatek,mt6373-auxadc", .data = &mt6373_chip_info }, 891 593 { } 892 594 }; 893 595 MODULE_DEVICE_TABLE(of, mt6359_auxadc_of_match);

+1 -2

drivers/iio/adc/mt6360-adc.c

reviewed

··· 264 264 struct { 265 265 u16 values[MT6360_CHAN_MAX]; 266 266 aligned_s64 timestamp; 267 267 - } data; 267 267 + } data = { }; 268 268 int i = 0, bit, val, ret; 269 269 270 270 - memset(&data, 0, sizeof(data)); 271 270 iio_for_each_active_channel(indio_dev, bit) { 272 271 ret = mt6360_adc_read_channel(mad, bit, &val); 273 272 if (ret < 0) {

+1 -1

drivers/iio/adc/qcom-vadc-common.c

reviewed

··· 330 330 const struct adc5_data *data, 331 331 u16 adc_code, int *result_mdec); 332 332 333 333 - static struct qcom_adc5_scale_type scale_adc5_fn[] = { 333 333 + static const struct qcom_adc5_scale_type scale_adc5_fn[] = { 334 334 [SCALE_HW_CALIB_DEFAULT] = {qcom_vadc_scale_hw_calib_volt}, 335 335 [SCALE_HW_CALIB_THERM_100K_PULLUP] = {qcom_vadc_scale_hw_calib_therm}, 336 336 [SCALE_HW_CALIB_XOTHERM] = {qcom_vadc_scale_hw_calib_therm},

+1 -3

drivers/iio/adc/rockchip_saradc.c

reviewed

··· 404 404 struct { 405 405 u16 values[SARADC_MAX_CHANNELS]; 406 406 aligned_s64 timestamp; 407 407 - } data; 407 407 + } data = { }; 408 408 int ret; 409 409 int i, j = 0; 410 410 - 411 411 - memset(&data, 0, sizeof(data)); 412 410 413 411 mutex_lock(&info->lock); 414 412

+1 -3

drivers/iio/adc/rtq6056.c

reviewed

··· 645 645 struct { 646 646 u16 vals[RTQ6056_MAX_CHANNEL]; 647 647 aligned_s64 timestamp; 648 648 - } data; 648 648 + } data = { }; 649 649 unsigned int raw; 650 650 int i = 0, bit, ret; 651 651 - 652 652 - memset(&data, 0, sizeof(data)); 653 651 654 652 pm_runtime_get_sync(dev); 655 653

+1 -2

drivers/iio/adc/stm32-adc-core.c

reviewed

··· 407 407 static int stm32_adc_irq_probe(struct platform_device *pdev, 408 408 struct stm32_adc_priv *priv) 409 409 { 410 410 - struct device_node *np = pdev->dev.of_node; 411 410 unsigned int i; 412 411 413 412 /* ··· 420 421 return priv->irq[i]; 421 422 } 422 423 423 423 - priv->domain = irq_domain_create_simple(of_fwnode_handle(np), 424 424 + priv->domain = irq_domain_create_simple(dev_fwnode(&pdev->dev), 424 425 STM32_ADC_MAX_ADCS, 0, 425 426 &stm32_adc_domain_ops, 426 427 priv);

+4 -5

drivers/iio/adc/stm32-adc.c

reviewed

··· 216 216 struct stm32_adc_cfg { 217 217 const struct stm32_adc_regspec *regs; 218 218 const struct stm32_adc_info *adc_info; 219 219 - struct stm32_adc_trig_info *trigs; 219 219 + const struct stm32_adc_trig_info *trigs; 220 220 bool clk_required; 221 221 bool has_vregready; 222 222 bool has_boostmode; ··· 383 383 }; 384 384 385 385 /* STM32F4 external trigger sources for all instances */ 386 386 - static struct stm32_adc_trig_info stm32f4_adc_trigs[] = { 386 386 + static const struct stm32_adc_trig_info stm32f4_adc_trigs[] = { 387 387 { TIM1_CH1, STM32_EXT0 }, 388 388 { TIM1_CH2, STM32_EXT1 }, 389 389 { TIM1_CH3, STM32_EXT2 }, ··· 473 473 }; 474 474 475 475 /* STM32H7 external trigger sources for all instances */ 476 476 - static struct stm32_adc_trig_info stm32h7_adc_trigs[] = { 476 476 + static const struct stm32_adc_trig_info stm32h7_adc_trigs[] = { 477 477 { TIM1_CH1, STM32_EXT0 }, 478 478 { TIM1_CH2, STM32_EXT1 }, 479 479 { TIM1_CH3, STM32_EXT2 }, ··· 2470 2470 static int stm32_adc_dma_request(struct device *dev, struct iio_dev *indio_dev) 2471 2471 { 2472 2472 struct stm32_adc *adc = iio_priv(indio_dev); 2473 2473 - struct dma_slave_config config; 2473 2473 + struct dma_slave_config config = { }; 2474 2474 int ret; 2475 2475 2476 2476 adc->dma_chan = dma_request_chan(dev, "rx"); ··· 2494 2494 } 2495 2495 2496 2496 /* Configure DMA channel to read data register */ 2497 2497 - memset(&config, 0, sizeof(config)); 2498 2497 config.src_addr = (dma_addr_t)adc->common->phys_base; 2499 2498 config.src_addr += adc->offset + adc->cfg->regs->dr; 2500 2499 config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;

+1

drivers/iio/adc/stm32-dfsdm-adc.c

reviewed

··· 8 8 9 9 #include <linux/dmaengine.h> 10 10 #include <linux/dma-mapping.h> 11 11 + #include <linux/export.h> 11 12 #include <linux/iio/adc/stm32-dfsdm-adc.h> 12 13 #include <linux/iio/backend.h> 13 14 #include <linux/iio/buffer.h>

+1

drivers/iio/adc/stm32-dfsdm-core.c

reviewed

··· 8 8 9 9 #include <linux/bitfield.h> 10 10 #include <linux/clk.h> 11 11 + #include <linux/export.h> 11 12 #include <linux/iio/iio.h> 12 13 #include <linux/iio/sysfs.h> 13 14 #include <linux/interrupt.h>

+1 -3

drivers/iio/adc/ti-ads1015.c

reviewed

··· 450 450 struct { 451 451 s16 chan; 452 452 aligned_s64 timestamp; 453 453 - } scan; 453 453 + } scan = { }; 454 454 int chan, ret, res; 455 455 - 456 456 - memset(&scan, 0, sizeof(scan)); 457 455 458 456 mutex_lock(&data->lock); 459 457 chan = find_first_bit(indio_dev->active_scan_mask,

+1 -3

drivers/iio/adc/ti-ads1119.c

reviewed

··· 507 507 struct { 508 508 s16 sample; 509 509 aligned_s64 timestamp; 510 510 - } scan; 510 510 + } scan = { }; 511 511 unsigned int index; 512 512 int ret; 513 513 - 514 514 - memset(&scan, 0, sizeof(scan)); 515 513 516 514 if (!iio_trigger_using_own(indio_dev)) { 517 515 index = find_first_bit(indio_dev->active_scan_mask,

+5 -5

drivers/iio/adc/ti-ads131e08.c

reviewed

··· 625 625 * 16 bits of data into the buffer. 626 626 */ 627 627 unsigned int num_bytes = ADS131E08_NUM_DATA_BYTES(st->data_rate); 628 628 - u8 tweek_offset = num_bytes == 2 ? 1 : 0; 628 628 + u8 tweak_offset = num_bytes == 2 ? 1 : 0; 629 629 630 630 if (iio_trigger_using_own(indio_dev)) 631 631 ret = ads131e08_read_data(st, st->readback_len); ··· 640 640 dest = st->tmp_buf.data + i * ADS131E08_NUM_STORAGE_BYTES; 641 641 642 642 /* 643 643 - * Tweek offset is 0: 643 643 + * Tweak offset is 0: 644 644 * +---+---+---+---+ 645 645 * |D0 |D1 |D2 | X | (3 data bytes) 646 646 * +---+---+---+---+ 647 647 * a+0 a+1 a+2 a+3 648 648 * 649 649 - * Tweek offset is 1: 649 649 + * Tweak offset is 1: 650 650 * +---+---+---+---+ 651 651 * |P0 |D0 |D1 | X | (one padding byte and 2 data bytes) 652 652 * +---+---+---+---+ 653 653 * a+0 a+1 a+2 a+3 654 654 */ 655 655 - memcpy(dest + tweek_offset, src, num_bytes); 655 655 + memcpy(dest + tweak_offset, src, num_bytes); 656 656 657 657 /* 658 658 * Data conversion from 16 bits of data to 24 bits of data 659 659 * is done by sign extension (properly filling padding byte). 660 660 */ 661 661 - if (tweek_offset) 661 661 + if (tweak_offset) 662 662 *dest = *src & BIT(7) ? 0xff : 0x00; 663 663 664 664 i++;

+1 -3

drivers/iio/adc/ti-lmp92064.c

reviewed

··· 200 200 struct { 201 201 u16 values[2]; 202 202 aligned_s64 timestamp; 203 203 - } data; 203 203 + } data = { }; 204 204 int ret; 205 205 - 206 206 - memset(&data, 0, sizeof(data)); 207 205 208 206 ret = lmp92064_read_meas(priv, data.values); 209 207 if (ret)

+1 -2

drivers/iio/adc/ti-tsc2046.c

reviewed

··· 276 276 struct tsc2046_adc_ch_cfg *ch = &priv->ch_cfg[ch_idx]; 277 277 unsigned int val, val_normalized = 0; 278 278 int ret, i, count_skip = 0, max_count; 279 279 - struct spi_transfer xfer; 279 279 + struct spi_transfer xfer = { }; 280 280 struct spi_message msg; 281 281 u8 cmd; 282 282 ··· 314 314 /* automatically power down on last sample */ 315 315 tx_buf[i].cmd = tsc2046_adc_get_cmd(priv, ch_idx, false); 316 316 317 317 - memset(&xfer, 0, sizeof(xfer)); 318 317 xfer.tx_buf = tx_buf; 319 318 xfer.rx_buf = rx_buf; 320 319 xfer.len = sizeof(*tx_buf) * max_count;

+1 -4

drivers/iio/adc/vf610_adc.c

reviewed

··· 28 28 #include <linux/iio/trigger_consumer.h> 29 29 #include <linux/iio/triggered_buffer.h> 30 30 31 31 - /* This will be the driver name the kernel reports */ 32 32 - #define DRIVER_NAME "vf610-adc" 33 33 - 34 31 /* Vybrid/IMX ADC registers */ 35 32 #define VF610_REG_ADC_HC0 0x00 36 33 #define VF610_REG_ADC_HC1 0x04 ··· 949 952 static struct platform_driver vf610_adc_driver = { 950 953 .probe = vf610_adc_probe, 951 954 .driver = { 952 952 - .name = DRIVER_NAME, 955 955 + .name = "vf610-adc", 953 956 .of_match_table = vf610_adc_match, 954 957 .pm = pm_sleep_ptr(&vf610_adc_pm_ops), 955 958 },

+3 -3

drivers/iio/amplifiers/ad8366.c

reviewed

··· 45 45 struct gpio_desc *reset_gpio; 46 46 unsigned char ch[2]; 47 47 enum ad8366_type type; 48 48 - struct ad8366_info *info; 48 48 + const struct ad8366_info *info; 49 49 /* 50 50 * DMA (thus cache coherency maintenance) may require the 51 51 * transfer buffers to live in their own cache lines. ··· 53 53 unsigned char data[2] __aligned(IIO_DMA_MINALIGN); 54 54 }; 55 55 56 56 - static struct ad8366_info ad8366_infos[] = { 56 56 + static const struct ad8366_info ad8366_infos[] = { 57 57 [ID_AD8366] = { 58 58 .gain_min = 4500, 59 59 .gain_max = 20500, ··· 163 163 long mask) 164 164 { 165 165 struct ad8366_state *st = iio_priv(indio_dev); 166 166 - struct ad8366_info *inf = st->info; 166 166 + const struct ad8366_info *inf = st->info; 167 167 int code = 0, gain; 168 168 int ret; 169 169

+18 -37

drivers/iio/amplifiers/ada4250.c

reviewed

··· 13 13 #include <linux/regmap.h> 14 14 #include <linux/regulator/consumer.h> 15 15 #include <linux/spi/spi.h> 16 16 - 17 17 - #include <linux/unaligned.h> 16 16 + #include <linux/types.h> 17 17 + #include <linux/units.h> 18 18 19 19 /* ADA4250 Register Map */ 20 20 #define ADA4250_REG_GAIN_MUX 0x00 ··· 56 56 struct ada4250_state { 57 57 struct spi_device *spi; 58 58 struct regmap *regmap; 59 59 - struct regulator *reg; 60 59 /* Protect against concurrent accesses to the device and data content */ 61 60 struct mutex lock; 61 61 + int avdd_uv; 62 62 + int offset_uv; 62 63 u8 bias; 63 64 u8 gain; 64 64 - int offset_uv; 65 65 bool refbuf_en; 66 66 + __le16 reg_val_16 __aligned(IIO_DMA_MINALIGN); 66 67 }; 67 68 68 69 /* ADA4250 Current Bias Source Settings: Disabled, Bandgap Reference, AVDD */ ··· 92 91 if (st->bias == 0 || st->bias == 3) 93 92 return -EINVAL; 94 93 95 95 - voltage_v = regulator_get_voltage(st->reg); 96 96 - voltage_v = DIV_ROUND_CLOSEST(voltage_v, 1000000); 94 94 + voltage_v = DIV_ROUND_CLOSEST(st->avdd_uv, MICRO); 97 95 98 96 if (st->bias == ADA4250_BIAS_AVDD) 99 97 x[0] = voltage_v; ··· 292 292 } 293 293 }; 294 294 295 295 - static void ada4250_reg_disable(void *data) 296 296 - { 297 297 - regulator_disable(data); 298 298 - } 299 299 - 300 295 static int ada4250_init(struct ada4250_state *st) 301 296 { 297 297 + struct device *dev = &st->spi->dev; 302 298 int ret; 303 299 u16 chip_id; 304 304 - u8 data[2] __aligned(8) = {}; 305 305 - struct spi_device *spi = st->spi; 306 300 307 307 - st->refbuf_en = device_property_read_bool(&spi->dev, "adi,refbuf-enable"); 301 301 + st->refbuf_en = device_property_read_bool(dev, "adi,refbuf-enable"); 308 302 309 309 - st->reg = devm_regulator_get(&spi->dev, "avdd"); 310 310 - if (IS_ERR(st->reg)) 311 311 - return dev_err_probe(&spi->dev, PTR_ERR(st->reg), 303 303 + st->avdd_uv = devm_regulator_get_enable_read_voltage(dev, "avdd"); 304 304 + if (st->avdd_uv < 0) 305 305 + return dev_err_probe(dev, st->avdd_uv, 312 306 "failed to get the AVDD voltage\n"); 313 313 - 314 314 - ret = regulator_enable(st->reg); 315 315 - if (ret) { 316 316 - dev_err(&spi->dev, "Failed to enable specified AVDD supply\n"); 317 317 - return ret; 318 318 - } 319 319 - 320 320 - ret = devm_add_action_or_reset(&spi->dev, ada4250_reg_disable, st->reg); 321 321 - if (ret) 322 322 - return ret; 323 307 324 308 ret = regmap_write(st->regmap, ADA4250_REG_RESET, 325 309 FIELD_PREP(ADA4250_RESET_MSK, 1)); 326 310 if (ret) 327 311 return ret; 328 312 329 329 - ret = regmap_bulk_read(st->regmap, ADA4250_REG_CHIP_ID, data, 2); 313 313 + ret = regmap_bulk_read(st->regmap, ADA4250_REG_CHIP_ID, &st->reg_val_16, 314 314 + sizeof(st->reg_val_16)); 330 315 if (ret) 331 316 return ret; 332 317 333 333 - chip_id = get_unaligned_le16(data); 318 318 + chip_id = le16_to_cpu(st->reg_val_16); 334 319 335 335 - if (chip_id != ADA4250_CHIP_ID) { 336 336 - dev_err(&spi->dev, "Invalid chip ID.\n"); 337 337 - return -EINVAL; 338 338 - } 320 320 + if (chip_id != ADA4250_CHIP_ID) 321 321 + dev_info(dev, "Invalid chip ID: 0x%02X.\n", chip_id); 339 322 340 323 return regmap_write(st->regmap, ADA4250_REG_REFBUF_EN, 341 324 FIELD_PREP(ADA4250_REFBUF_MSK, st->refbuf_en)); ··· 351 368 mutex_init(&st->lock); 352 369 353 370 ret = ada4250_init(st); 354 354 - if (ret) { 355 355 - dev_err(&spi->dev, "ADA4250 init failed\n"); 356 356 - return ret; 357 357 - } 371 371 + if (ret) 372 372 + return dev_err_probe(&spi->dev, ret, "ADA4250 init failed\n"); 358 373 359 374 return devm_iio_device_register(&spi->dev, indio_dev); 360 375 }

+1 -1

drivers/iio/buffer/industrialio-triggered-buffer.c

reviewed

··· 1 1 // SPDX-License-Identifier: GPL-2.0-only 2 2 - /* 2 2 + /* 3 3 * Copyright (c) 2012 Analog Devices, Inc. 4 4 * Author: Lars-Peter Clausen <lars@metafoo.de> 5 5 */

+1 -1

drivers/iio/chemical/atlas-ezo-sensor.c

reviewed

··· 82 82 }, 83 83 }; 84 84 85 85 - static struct atlas_ezo_device atlas_ezo_devices[] = { 85 85 + static const struct atlas_ezo_device atlas_ezo_devices[] = { 86 86 [ATLAS_CO2_EZO] = { 87 87 .channels = atlas_co2_ezo_channels, 88 88 .num_channels = 1,

+1 -2

drivers/iio/chemical/atlas-sensor.c

reviewed

··· 24 24 #include <linux/iio/triggered_buffer.h> 25 25 #include <linux/pm_runtime.h> 26 26 27 27 - #define ATLAS_REGMAP_NAME "atlas_regmap" 28 27 #define ATLAS_DRV_NAME "atlas" 29 28 30 29 #define ATLAS_REG_DEV_TYPE 0x00 ··· 95 96 }; 96 97 97 98 static const struct regmap_config atlas_regmap_config = { 98 98 - .name = ATLAS_REGMAP_NAME, 99 99 + .name = "atlas_regmap", 99 100 .reg_bits = 8, 100 101 .val_bits = 8, 101 102 };

+1 -1

drivers/iio/chemical/bme680_core.c

reviewed

··· 158 158 .val_bits = 8, 159 159 .max_register = 0xef, 160 160 .volatile_table = &bme680_volatile_table, 161 161 - .cache_type = REGCACHE_RBTREE, 161 161 + .cache_type = REGCACHE_MAPLE, 162 162 }; 163 163 EXPORT_SYMBOL_NS(bme680_regmap_config, "IIO_BME680"); 164 164

+1 -2

drivers/iio/chemical/scd30_core.c

reviewed

··· 587 587 struct { 588 588 int data[SCD30_MEAS_COUNT]; 589 589 aligned_s64 ts; 590 590 - } scan; 590 590 + } scan = { }; 591 591 int ret; 592 592 593 593 mutex_lock(&state->lock); ··· 595 595 ret = scd30_read_poll(state); 596 596 else 597 597 ret = scd30_read_meas(state); 598 598 - memset(&scan, 0, sizeof(scan)); 599 598 memcpy(scan.data, state->meas, sizeof(state->meas)); 600 599 mutex_unlock(&state->lock); 601 600 if (ret)

+1 -2

drivers/iio/chemical/scd4x.c

reviewed

··· 665 665 struct { 666 666 uint16_t data[3]; 667 667 aligned_s64 ts; 668 668 - } scan; 668 668 + } scan = { }; 669 669 int ret; 670 670 671 671 - memset(&scan, 0, sizeof(scan)); 672 671 mutex_lock(&state->lock); 673 672 ret = scd4x_read_poll(state, scan.data); 674 673 mutex_unlock(&state->lock);

+2 -4

drivers/iio/chemical/sunrise_co2.c

reviewed

··· 51 51 { 52 52 struct i2c_client *client = context; 53 53 struct sunrise_dev *sunrise = i2c_get_clientdata(client); 54 54 - union i2c_smbus_data data; 54 54 + union i2c_smbus_data data = { }; 55 55 int ret; 56 56 57 57 if (reg_size != 1 || !val_size) 58 58 return -EINVAL; 59 59 60 60 - memset(&data, 0, sizeof(data)); 61 60 data.block[0] = val_size; 62 61 63 62 /* ··· 87 88 { 88 89 struct i2c_client *client = context; 89 90 struct sunrise_dev *sunrise = i2c_get_clientdata(client); 90 90 - union i2c_smbus_data data; 91 91 + union i2c_smbus_data data = { }; 91 92 92 93 /* Discard reg address from values count. */ 93 94 if (!count) 94 95 return -EINVAL; 95 96 count--; 96 97 97 97 - memset(&data, 0, sizeof(data)); 98 98 data.block[0] = count; 99 99 memcpy(&data.block[1], (u8 *)val_buf + 1, count); 100 100

+9

drivers/iio/common/cros_ec_sensors/Kconfig

reviewed

··· 30 30 convertible devices. 31 31 This module is loaded when the EC can calculate the angle between the base 32 32 and the lid. 33 33 + 34 34 + config IIO_CROS_EC_ACTIVITY 35 35 + tristate "ChromeOS EC Activity Sensors" 36 36 + depends on IIO_CROS_EC_SENSORS_CORE 37 37 + help 38 38 + Module to handle activity events presented by the ChromeOS EC sensor hub. 39 39 + Activities can be a proximity detector (on body/off body detection) 40 40 + or a significant motion detector. 41 41 + Creates an IIO device to manage all activities.

+1

drivers/iio/common/cros_ec_sensors/Makefile

reviewed

··· 7 7 obj-$(CONFIG_IIO_CROS_EC_SENSORS_CORE) += cros-ec-sensors-core.o 8 8 obj-$(CONFIG_IIO_CROS_EC_SENSORS) += cros_ec_sensors.o 9 9 obj-$(CONFIG_IIO_CROS_EC_SENSORS_LID_ANGLE) += cros_ec_lid_angle.o 10 10 + obj-$(CONFIG_IIO_CROS_EC_ACTIVITY) += cros_ec_activity.o

+307

drivers/iio/common/cros_ec_sensors/cros_ec_activity.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0 2 2 + /* 3 3 + * cros_ec_activity - Driver for activities/gesture recognition. 4 4 + * 5 5 + * Copyright 2025 Google, Inc 6 6 + * 7 7 + * This driver uses the cros-ec interface to communicate with the ChromeOS 8 8 + * EC about activity data. 9 9 + */ 10 10 + 11 11 + #include <linux/bits.h> 12 12 + #include <linux/cleanup.h> 13 13 + #include <linux/kernel.h> 14 14 + #include <linux/module.h> 15 15 + #include <linux/mutex.h> 16 16 + #include <linux/platform_device.h> 17 17 + #include <linux/types.h> 18 18 + 19 19 + #include <linux/platform_data/cros_ec_commands.h> 20 20 + #include <linux/platform_data/cros_ec_proto.h> 21 21 + 22 22 + #include <linux/iio/common/cros_ec_sensors_core.h> 23 23 + #include <linux/iio/events.h> 24 24 + #include <linux/iio/iio.h> 25 25 + #include <linux/iio/trigger_consumer.h> 26 26 + 27 27 + #define DRV_NAME "cros-ec-activity" 28 28 + 29 29 + /* state data for ec_sensors iio driver. */ 30 30 + struct cros_ec_sensors_state { 31 31 + /* Shared by all sensors */ 32 32 + struct cros_ec_sensors_core_state core; 33 33 + 34 34 + struct iio_chan_spec *channels; 35 35 + 36 36 + int body_detection_channel_index; 37 37 + int sig_motion_channel_index; 38 38 + }; 39 39 + 40 40 + static const struct iio_event_spec cros_ec_activity_single_shot[] = { 41 41 + { 42 42 + .type = IIO_EV_TYPE_CHANGE, 43 43 + /* significant motion trigger when we get out of still. */ 44 44 + .dir = IIO_EV_DIR_FALLING, 45 45 + .mask_separate = BIT(IIO_EV_INFO_ENABLE), 46 46 + }, 47 47 + }; 48 48 + 49 49 + static const struct iio_event_spec cros_ec_body_detect_events[] = { 50 50 + { 51 51 + .type = IIO_EV_TYPE_CHANGE, 52 52 + .dir = IIO_EV_DIR_EITHER, 53 53 + .mask_separate = BIT(IIO_EV_INFO_ENABLE), 54 54 + }, 55 55 + }; 56 56 + 57 57 + static int cros_ec_activity_sensors_read_raw(struct iio_dev *indio_dev, 58 58 + struct iio_chan_spec const *chan, 59 59 + int *val, int *val2, long mask) 60 60 + { 61 61 + struct cros_ec_sensors_state *st = iio_priv(indio_dev); 62 62 + int ret; 63 63 + 64 64 + if (chan->type != IIO_PROXIMITY || mask != IIO_CHAN_INFO_RAW) 65 65 + return -EINVAL; 66 66 + 67 67 + guard(mutex)(&st->core.cmd_lock); 68 68 + st->core.param.cmd = MOTIONSENSE_CMD_GET_ACTIVITY; 69 69 + st->core.param.get_activity.activity = 70 70 + MOTIONSENSE_ACTIVITY_BODY_DETECTION; 71 71 + ret = cros_ec_motion_send_host_cmd(&st->core, 0); 72 72 + if (ret) 73 73 + return ret; 74 74 + 75 75 + /* 76 76 + * EC actually report if a body is near (1) or far (0). 77 77 + * Units for proximity sensor after scale is in meter, 78 78 + * so invert the result to return 0m when near and 1m when far. 79 79 + */ 80 80 + *val = !st->core.resp->get_activity.state; 81 81 + return IIO_VAL_INT; 82 82 + } 83 83 + 84 84 + static int cros_ec_activity_read_event_config(struct iio_dev *indio_dev, 85 85 + const struct iio_chan_spec *chan, 86 86 + enum iio_event_type type, 87 87 + enum iio_event_direction dir) 88 88 + { 89 89 + struct cros_ec_sensors_state *st = iio_priv(indio_dev); 90 90 + int ret; 91 91 + 92 92 + if (chan->type != IIO_ACTIVITY && chan->type != IIO_PROXIMITY) 93 93 + return -EINVAL; 94 94 + 95 95 + guard(mutex)(&st->core.cmd_lock); 96 96 + st->core.param.cmd = MOTIONSENSE_CMD_LIST_ACTIVITIES; 97 97 + ret = cros_ec_motion_send_host_cmd(&st->core, 0); 98 98 + if (ret) 99 99 + return ret; 100 100 + 101 101 + switch (chan->type) { 102 102 + case IIO_PROXIMITY: 103 103 + return !!(st->core.resp->list_activities.enabled & 104 104 + (1 << MOTIONSENSE_ACTIVITY_BODY_DETECTION)); 105 105 + case IIO_ACTIVITY: 106 106 + if (chan->channel2 == IIO_MOD_STILL) { 107 107 + return !!(st->core.resp->list_activities.enabled & 108 108 + (1 << MOTIONSENSE_ACTIVITY_SIG_MOTION)); 109 109 + } 110 110 + 111 111 + dev_warn(&indio_dev->dev, "Unknown activity: %d\n", 112 112 + chan->channel2); 113 113 + return -EINVAL; 114 114 + default: 115 115 + dev_warn(&indio_dev->dev, "Unknown channel type: %d\n", 116 116 + chan->type); 117 117 + return -EINVAL; 118 118 + } 119 119 + } 120 120 + 121 121 + static int cros_ec_activity_write_event_config(struct iio_dev *indio_dev, 122 122 + const struct iio_chan_spec *chan, 123 123 + enum iio_event_type type, 124 124 + enum iio_event_direction dir, 125 125 + bool state) 126 126 + { 127 127 + struct cros_ec_sensors_state *st = iio_priv(indio_dev); 128 128 + 129 129 + guard(mutex)(&st->core.cmd_lock); 130 130 + st->core.param.cmd = MOTIONSENSE_CMD_SET_ACTIVITY; 131 131 + switch (chan->type) { 132 132 + case IIO_PROXIMITY: 133 133 + st->core.param.set_activity.activity = 134 134 + MOTIONSENSE_ACTIVITY_BODY_DETECTION; 135 135 + break; 136 136 + case IIO_ACTIVITY: 137 137 + if (chan->channel2 == IIO_MOD_STILL) { 138 138 + st->core.param.set_activity.activity = 139 139 + MOTIONSENSE_ACTIVITY_SIG_MOTION; 140 140 + break; 141 141 + } 142 142 + dev_warn(&indio_dev->dev, "Unknown activity: %d\n", 143 143 + chan->channel2); 144 144 + return -EINVAL; 145 145 + default: 146 146 + dev_warn(&indio_dev->dev, "Unknown channel type: %d\n", 147 147 + chan->type); 148 148 + return -EINVAL; 149 149 + } 150 150 + st->core.param.set_activity.enable = state; 151 151 + return cros_ec_motion_send_host_cmd(&st->core, 0); 152 152 + } 153 153 + 154 154 + static int cros_ec_activity_push_data(struct iio_dev *indio_dev, 155 155 + s16 *data, s64 timestamp) 156 156 + { 157 157 + struct ec_response_activity_data *activity_data = 158 158 + (struct ec_response_activity_data *)data; 159 159 + enum motionsensor_activity activity = activity_data->activity; 160 160 + u8 state = activity_data->state; 161 161 + const struct cros_ec_sensors_state *st = iio_priv(indio_dev); 162 162 + const struct iio_chan_spec *chan; 163 163 + enum iio_event_direction dir; 164 164 + int index; 165 165 + 166 166 + switch (activity) { 167 167 + case MOTIONSENSE_ACTIVITY_BODY_DETECTION: 168 168 + index = st->body_detection_channel_index; 169 169 + dir = state ? IIO_EV_DIR_FALLING : IIO_EV_DIR_RISING; 170 170 + break; 171 171 + case MOTIONSENSE_ACTIVITY_SIG_MOTION: 172 172 + index = st->sig_motion_channel_index; 173 173 + dir = IIO_EV_DIR_FALLING; 174 174 + break; 175 175 + default: 176 176 + dev_warn(&indio_dev->dev, "Unknown activity: %d\n", activity); 177 177 + return 0; 178 178 + } 179 179 + chan = &st->channels[index]; 180 180 + iio_push_event(indio_dev, 181 181 + IIO_UNMOD_EVENT_CODE(chan->type, index, chan->event_spec[0].type, dir), 182 182 + timestamp); 183 183 + return 0; 184 184 + } 185 185 + 186 186 + static irqreturn_t cros_ec_activity_capture(int irq, void *p) 187 187 + { 188 188 + struct iio_poll_func *pf = p; 189 189 + struct iio_dev *indio_dev = pf->indio_dev; 190 190 + 191 191 + /* 192 192 + * This callback would be called when a software trigger is 193 193 + * used. But when this virtual sensor is present, it is guaranteed 194 194 + * the sensor hub is advanced enough to not need a software trigger. 195 195 + */ 196 196 + dev_warn(&indio_dev->dev, "%s: Not Expected\n", __func__); 197 197 + return IRQ_NONE; 198 198 + } 199 199 + 200 200 + static const struct iio_info ec_sensors_info = { 201 201 + .read_raw = &cros_ec_activity_sensors_read_raw, 202 202 + .read_event_config = cros_ec_activity_read_event_config, 203 203 + .write_event_config = cros_ec_activity_write_event_config, 204 204 + }; 205 205 + 206 206 + static int cros_ec_sensors_probe(struct platform_device *pdev) 207 207 + { 208 208 + struct device *dev = &pdev->dev; 209 209 + struct cros_ec_device *ec_device = dev_get_drvdata(dev->parent); 210 210 + struct iio_dev *indio_dev; 211 211 + struct cros_ec_sensors_state *st; 212 212 + struct iio_chan_spec *channel; 213 213 + unsigned long activities; 214 214 + int i, index, ret, nb_activities; 215 215 + 216 216 + if (!ec_device) { 217 217 + dev_warn(dev, "No CROS EC device found.\n"); 218 218 + return -EINVAL; 219 219 + } 220 220 + 221 221 + indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 222 222 + if (!indio_dev) 223 223 + return -ENOMEM; 224 224 + 225 225 + ret = cros_ec_sensors_core_init(pdev, indio_dev, true, 226 226 + cros_ec_activity_capture); 227 227 + if (ret) 228 228 + return ret; 229 229 + 230 230 + indio_dev->info = &ec_sensors_info; 231 231 + st = iio_priv(indio_dev); 232 232 + st->core.type = st->core.resp->info.type; 233 233 + st->core.read_ec_sensors_data = cros_ec_sensors_read_cmd; 234 234 + 235 235 + st->core.param.cmd = MOTIONSENSE_CMD_LIST_ACTIVITIES; 236 236 + ret = cros_ec_motion_send_host_cmd(&st->core, 0); 237 237 + if (ret) 238 238 + return ret; 239 239 + 240 240 + activities = st->core.resp->list_activities.enabled | 241 241 + st->core.resp->list_activities.disabled; 242 242 + if (!activities) 243 243 + return -ENODEV; 244 244 + 245 245 + /* Allocate a channel per activity and one for timestamp */ 246 246 + nb_activities = hweight_long(activities) + 1; 247 247 + st->channels = devm_kcalloc(dev, nb_activities, 248 248 + sizeof(*st->channels), GFP_KERNEL); 249 249 + if (!st->channels) 250 250 + return -ENOMEM; 251 251 + 252 252 + channel = &st->channels[0]; 253 253 + index = 0; 254 254 + for_each_set_bit(i, &activities, BITS_PER_LONG) { 255 255 + /* List all available triggers */ 256 256 + if (i == MOTIONSENSE_ACTIVITY_BODY_DETECTION) { 257 257 + channel->type = IIO_PROXIMITY; 258 258 + channel->info_mask_separate = BIT(IIO_CHAN_INFO_RAW); 259 259 + channel->event_spec = cros_ec_body_detect_events; 260 260 + channel->num_event_specs = 261 261 + ARRAY_SIZE(cros_ec_body_detect_events); 262 262 + st->body_detection_channel_index = index; 263 263 + } else { 264 264 + channel->type = IIO_ACTIVITY; 265 265 + channel->modified = 1; 266 266 + channel->event_spec = cros_ec_activity_single_shot; 267 267 + channel->num_event_specs = 268 268 + ARRAY_SIZE(cros_ec_activity_single_shot); 269 269 + if (i == MOTIONSENSE_ACTIVITY_SIG_MOTION) { 270 270 + channel->channel2 = IIO_MOD_STILL; 271 271 + st->sig_motion_channel_index = index; 272 272 + } else { 273 273 + dev_warn(dev, "Unknown activity: %d\n", i); 274 274 + continue; 275 275 + } 276 276 + } 277 277 + channel->ext_info = cros_ec_sensors_limited_info; 278 278 + channel->scan_index = index++; 279 279 + channel++; 280 280 + } 281 281 + 282 282 + /* Timestamp */ 283 283 + channel->scan_index = index; 284 284 + channel->type = IIO_TIMESTAMP; 285 285 + channel->channel = -1; 286 286 + channel->scan_type.sign = 's'; 287 287 + channel->scan_type.realbits = 64; 288 288 + channel->scan_type.storagebits = 64; 289 289 + 290 290 + indio_dev->channels = st->channels; 291 291 + indio_dev->num_channels = index + 1; 292 292 + 293 293 + return cros_ec_sensors_core_register(dev, indio_dev, 294 294 + cros_ec_activity_push_data); 295 295 + } 296 296 + 297 297 + static struct platform_driver cros_ec_sensors_platform_driver = { 298 298 + .driver = { 299 299 + .name = DRV_NAME, 300 300 + }, 301 301 + .probe = cros_ec_sensors_probe, 302 302 + }; 303 303 + module_platform_driver(cros_ec_sensors_platform_driver); 304 304 + 305 305 + MODULE_DESCRIPTION("ChromeOS EC activity sensors driver"); 306 306 + MODULE_ALIAS("platform:" DRV_NAME); 307 307 + MODULE_LICENSE("GPL v2");

+10

drivers/iio/common/cros_ec_sensors/cros_ec_sensors_core.c

reviewed

··· 486 486 }; 487 487 EXPORT_SYMBOL_GPL(cros_ec_sensors_ext_info); 488 488 489 489 + const struct iio_chan_spec_ext_info cros_ec_sensors_limited_info[] = { 490 490 + { 491 491 + .name = "id", 492 492 + .shared = IIO_SHARED_BY_ALL, 493 493 + .read = cros_ec_sensors_id 494 494 + }, 495 495 + { } 496 496 + }; 497 497 + EXPORT_SYMBOL_GPL(cros_ec_sensors_limited_info); 498 498 + 489 499 /** 490 500 * cros_ec_sensors_idx_to_reg - convert index into offset in shared memory 491 501 * @st: pointer to state information for device

+1 -1

drivers/iio/common/hid-sensors/hid-sensor-attributes.c

reviewed

··· 11 11 #include <linux/hid-sensor-hub.h> 12 12 #include <linux/iio/iio.h> 13 13 14 14 - static struct { 14 14 + static const struct { 15 15 u32 usage_id; 16 16 int unit; /* 0 for default others from HID sensor spec */ 17 17 int scale_val0; /* scale, whole number */

+1 -2

drivers/iio/dac/ad3552r.c

reviewed

··· 293 293 struct iio_buffer *buf = indio_dev->buffer; 294 294 struct ad3552r_desc *dac = iio_priv(indio_dev); 295 295 /* Maximum size of a scan */ 296 296 - u8 buff[AD3552R_MAX_CH * AD3552R_MAX_REG_SIZE]; 296 296 + u8 buff[AD3552R_MAX_CH * AD3552R_MAX_REG_SIZE] = { }; 297 297 int err; 298 298 299 299 - memset(buff, 0, sizeof(buff)); 300 299 err = iio_pop_from_buffer(buf, buff); 301 300 if (err) 302 301 goto end;

+1 -1

drivers/iio/dac/ad5380.c

reviewed

··· 426 426 .val_bits = 14, 427 427 428 428 .max_register = AD5380_REG_DATA(40), 429 429 - .cache_type = REGCACHE_RBTREE, 429 429 + .cache_type = REGCACHE_MAPLE, 430 430 431 431 .volatile_reg = ad5380_reg_false, 432 432 .readable_reg = ad5380_reg_false,

+1 -1

drivers/iio/dac/ad5770r.c

reviewed

··· 155 155 int max; 156 156 }; 157 157 158 158 - static struct ad5770r_output_modes ad5770r_rng_tbl[] = { 158 158 + static const struct ad5770r_output_modes ad5770r_rng_tbl[] = { 159 159 { 0, AD5770R_CH0_0_300, 0, 300 }, 160 160 { 0, AD5770R_CH0_NEG_60_0, -60, 0 }, 161 161 { 0, AD5770R_CH0_NEG_60_300, -60, 300 },

+22 -20

drivers/iio/dac/adi-axi-dac.c

reviewed

··· 635 635 AXI_DAC_CNTRL_2_SDR_DDR_N); 636 636 } 637 637 638 638 + static int axi_dac_wait_bus_free(struct axi_dac_state *st) 639 639 + { 640 640 + u32 val; 641 641 + int ret; 642 642 + 643 643 + ret = regmap_read_poll_timeout(st->regmap, AXI_DAC_UI_STATUS_REG, val, 644 644 + FIELD_GET(AXI_DAC_UI_STATUS_IF_BUSY, val) == 0, 10, 645 645 + 100 * KILO); 646 646 + if (ret == -ETIMEDOUT) 647 647 + dev_err(st->dev, "AXI bus timeout\n"); 648 648 + 649 649 + return ret; 650 650 + } 651 651 + 638 652 static int axi_dac_data_stream_enable(struct iio_backend *back) 639 653 { 640 654 struct axi_dac_state *st = iio_backend_get_priv(back); 641 641 - int ret, val; 655 655 + int ret; 642 656 643 643 - ret = regmap_read_poll_timeout(st->regmap, 644 644 - AXI_DAC_UI_STATUS_REG, val, 645 645 - FIELD_GET(AXI_DAC_UI_STATUS_IF_BUSY, val) == 0, 646 646 - 10, 100 * KILO); 657 657 + ret = axi_dac_wait_bus_free(st); 647 658 if (ret) 648 659 return ret; 649 660 ··· 745 734 if (ret) 746 735 return ret; 747 736 748 748 - ret = regmap_read_poll_timeout(st->regmap, 749 749 - AXI_DAC_UI_STATUS_REG, ival, 750 750 - FIELD_GET(AXI_DAC_UI_STATUS_IF_BUSY, ival) == 0, 751 751 - 10, 100 * KILO); 752 752 - if (ret == -ETIMEDOUT) 753 753 - dev_err(st->dev, "AXI read timeout\n"); 737 737 + ret = axi_dac_wait_bus_free(st); 738 738 + if (ret) 739 739 + return ret; 754 740 755 741 /* Cleaning always AXI_DAC_CUSTOM_CTRL_TRANSFER_DATA */ 756 742 return regmap_clear_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG, ··· 768 760 { 769 761 struct axi_dac_state *st = iio_backend_get_priv(back); 770 762 int ret; 771 771 - u32 ival; 772 763 773 764 guard(mutex)(&st->lock); 774 765 ··· 780 773 if (ret) 781 774 return ret; 782 775 783 783 - ret = regmap_read_poll_timeout(st->regmap, 784 784 - AXI_DAC_UI_STATUS_REG, ival, 785 785 - FIELD_GET(AXI_DAC_UI_STATUS_IF_BUSY, ival) == 0, 786 786 - 10, 100 * KILO); 776 776 + ret = axi_dac_wait_bus_free(st); 787 777 if (ret) 788 778 return ret; 789 779 ··· 791 787 enum ad3552r_io_mode mode) 792 788 { 793 789 struct axi_dac_state *st = iio_backend_get_priv(back); 794 794 - int ival, ret; 790 790 + int ret; 795 791 796 792 if (mode > AD3552R_IO_MODE_QSPI) 797 793 return -EINVAL; ··· 804 800 if (ret) 805 801 return ret; 806 802 807 807 - return regmap_read_poll_timeout(st->regmap, AXI_DAC_UI_STATUS_REG, ival, 808 808 - FIELD_GET(AXI_DAC_UI_STATUS_IF_BUSY, ival) == 0, 10, 809 809 - 100 * KILO); 803 803 + return axi_dac_wait_bus_free(st); 810 804 } 811 805 812 806 static void axi_dac_child_remove(void *data)

+1 -1

drivers/iio/dac/ltc2688.c

reviewed

··· 622 622 { } 623 623 }; 624 624 625 625 - static struct iio_chan_spec_ext_info ltc2688_dither_ext_info[] = { 625 625 + static const struct iio_chan_spec_ext_info ltc2688_dither_ext_info[] = { 626 626 LTC2688_CHAN_EXT_INFO("dither_raw", LTC2688_INPUT_B, IIO_SEPARATE, 627 627 ltc2688_dac_input_read, ltc2688_dac_input_write), 628 628 LTC2688_CHAN_EXT_INFO("dither_raw_available", LTC2688_INPUT_B_AVAIL,

+1 -3

drivers/iio/dac/max517.c

reviewed

··· 15 15 #include <linux/iio/sysfs.h> 16 16 #include <linux/iio/dac/max517.h> 17 17 18 18 - #define MAX517_DRV_NAME "max517" 19 19 - 20 18 /* Commands */ 21 19 #define COMMAND_CHANNEL0 0x00 22 20 #define COMMAND_CHANNEL1 0x01 /* for MAX518 and MAX519 */ ··· 198 200 199 201 static struct i2c_driver max517_driver = { 200 202 .driver = { 201 201 - .name = MAX517_DRV_NAME, 203 203 + .name = "max517", 202 204 .pm = pm_sleep_ptr(&max517_pm_ops), 203 205 }, 204 206 .probe = max517_probe,

+1 -3

drivers/iio/dac/mcp4725.c

reviewed

··· 24 24 25 25 #include <linux/iio/dac/mcp4725.h> 26 26 27 27 - #define MCP4725_DRV_NAME "mcp4725" 28 28 - 29 27 #define MCP472X_REF_VDD 0x00 30 28 #define MCP472X_REF_VREF_UNBUFFERED 0x02 31 29 #define MCP472X_REF_VREF_BUFFERED 0x03 ··· 544 546 545 547 static struct i2c_driver mcp4725_driver = { 546 548 .driver = { 547 547 - .name = MCP4725_DRV_NAME, 549 549 + .name = "mcp4725", 548 550 .of_match_table = mcp4725_of_match, 549 551 .pm = pm_sleep_ptr(&mcp4725_pm_ops), 550 552 },

+1 -1

drivers/iio/dac/rohm-bd79703.c

reviewed

··· 35 35 .reg_bits = 8, 36 36 .val_bits = 8, 37 37 .max_register = BD79703_MAX_REGISTER, 38 38 - .cache_type = REGCACHE_RBTREE, 38 38 + .cache_type = REGCACHE_MAPLE, 39 39 }; 40 40 41 41 /* Dynamic driver private data */

+5 -18

drivers/iio/dac/vf610_dac.c

reviewed

··· 178 178 179 179 indio_dev = devm_iio_device_alloc(&pdev->dev, 180 180 sizeof(struct vf610_dac)); 181 181 - if (!indio_dev) { 182 182 - dev_err(&pdev->dev, "Failed allocating iio device\n"); 181 181 + if (!indio_dev) 183 182 return -ENOMEM; 184 184 - } 185 183 186 184 info = iio_priv(indio_dev); 187 185 info->dev = &pdev->dev; ··· 188 190 if (IS_ERR(info->regs)) 189 191 return PTR_ERR(info->regs); 190 192 191 191 - info->clk = devm_clk_get(&pdev->dev, "dac"); 192 192 - if (IS_ERR(info->clk)) { 193 193 - dev_err(&pdev->dev, "Failed getting clock, err = %ld\n", 194 194 - PTR_ERR(info->clk)); 195 195 - return PTR_ERR(info->clk); 196 196 - } 193 193 + info->clk = devm_clk_get_enabled(&pdev->dev, "dac"); 194 194 + if (IS_ERR(info->clk)) 195 195 + return dev_err_probe(&pdev->dev, PTR_ERR(info->clk), 196 196 + "Failed getting clock\n"); 197 197 198 198 platform_set_drvdata(pdev, indio_dev); 199 199 ··· 202 206 indio_dev->num_channels = ARRAY_SIZE(vf610_dac_iio_channels); 203 207 204 208 mutex_init(&info->lock); 205 205 - 206 206 - ret = clk_prepare_enable(info->clk); 207 207 - if (ret) { 208 208 - dev_err(&pdev->dev, 209 209 - "Could not prepare or enable the clock\n"); 210 210 - return ret; 211 211 - } 212 209 213 210 vf610_dac_init(info); 214 211 ··· 215 226 216 227 error_iio_device_register: 217 228 vf610_dac_exit(info); 218 218 - clk_disable_unprepare(info->clk); 219 229 220 230 return ret; 221 231 } ··· 226 238 227 239 iio_device_unregister(indio_dev); 228 240 vf610_dac_exit(info); 229 229 - clk_disable_unprepare(info->clk); 230 241 } 231 242 232 243 static int vf610_dac_suspend(struct device *dev)

+1 -3

drivers/iio/gyro/bmg160_core.c

reviewed

··· 21 21 #include <linux/regulator/consumer.h> 22 22 #include "bmg160.h" 23 23 24 24 - #define BMG160_IRQ_NAME "bmg160_event" 25 25 - 26 24 #define BMG160_REG_CHIP_ID 0x00 27 25 #define BMG160_CHIP_ID_VAL 0x0F 28 26 ··· 1097 1099 bmg160_data_rdy_trig_poll, 1098 1100 bmg160_event_handler, 1099 1101 IRQF_TRIGGER_RISING, 1100 1100 - BMG160_IRQ_NAME, 1102 1102 + "bmg160_event", 1101 1103 indio_dev); 1102 1104 if (ret) 1103 1105 return ret;

+1 -1

drivers/iio/health/afe4403.c

reviewed

··· 405 405 .val_bits = 24, 406 406 407 407 .max_register = AFE440X_PDNCYCLEENDC, 408 408 - .cache_type = REGCACHE_RBTREE, 408 408 + .cache_type = REGCACHE_MAPLE, 409 409 .volatile_table = &afe4403_volatile_table, 410 410 }; 411 411

+1 -1

drivers/iio/health/afe4404.c

reviewed

··· 413 413 .val_bits = 24, 414 414 415 415 .max_register = AFE4404_AVG_LED1_ALED1VAL, 416 416 - .cache_type = REGCACHE_RBTREE, 416 416 + .cache_type = REGCACHE_MAPLE, 417 417 .volatile_table = &afe4404_volatile_table, 418 418 }; 419 419

+1 -2

drivers/iio/health/max30100.c

reviewed

··· 22 22 #include <linux/iio/buffer.h> 23 23 #include <linux/iio/kfifo_buf.h> 24 24 25 25 - #define MAX30100_REGMAP_NAME "max30100_regmap" 26 25 #define MAX30100_DRV_NAME "max30100" 27 26 28 27 #define MAX30100_REG_INT_STATUS 0x00 ··· 93 94 } 94 95 95 96 static const struct regmap_config max30100_regmap_config = { 96 96 - .name = MAX30100_REGMAP_NAME, 97 97 + .name = "max30100_regmap", 97 98 98 99 .reg_bits = 8, 99 100 .val_bits = 8,

+1 -2

drivers/iio/health/max30102.c

reviewed

··· 25 25 #include <linux/iio/buffer.h> 26 26 #include <linux/iio/kfifo_buf.h> 27 27 28 28 - #define MAX30102_REGMAP_NAME "max30102_regmap" 29 28 #define MAX30102_DRV_NAME "max30102" 30 29 #define MAX30102_PART_NUMBER 0x15 31 30 ··· 111 112 }; 112 113 113 114 static const struct regmap_config max30102_regmap_config = { 114 114 - .name = MAX30102_REGMAP_NAME, 115 115 + .name = "max30102_regmap", 115 116 116 117 .reg_bits = 8, 117 118 .val_bits = 8,

+1 -3

drivers/iio/humidity/dht11.c

reviewed

··· 27 27 28 28 #include <linux/iio/iio.h> 29 29 30 30 - #define DRIVER_NAME "dht11" 31 31 - 32 30 #define DHT11_DATA_VALID_TIME 2000000000 /* 2s in ns */ 33 31 34 32 #define DHT11_EDGES_PREAMBLE 2 ··· 329 331 330 332 static struct platform_driver dht11_driver = { 331 333 .driver = { 332 332 - .name = DRIVER_NAME, 334 334 + .name = "dht11", 333 335 .of_match_table = dht11_dt_ids, 334 336 }, 335 337 .probe = dht11_probe,

+153 -161

drivers/iio/imu/adis16400.c

reviewed

··· 170 170 * that must be enabled together 171 171 **/ 172 172 struct adis16400_state { 173 173 - struct adis16400_chip_info *variant; 173 173 + const struct adis16400_chip_info *variant; 174 174 int filt_int; 175 175 176 176 struct adis adis; ··· 288 288 debugfs_create_file_unsafe("flash_count", 0400, 289 289 d, st, &adis16400_flash_count_fops); 290 290 } 291 291 - 292 292 - enum adis16400_chip_variant { 293 293 - ADIS16300, 294 294 - ADIS16334, 295 295 - ADIS16350, 296 296 - ADIS16360, 297 297 - ADIS16362, 298 298 - ADIS16364, 299 299 - ADIS16367, 300 300 - ADIS16400, 301 301 - ADIS16445, 302 302 - ADIS16448, 303 303 - }; 304 291 305 292 static int adis16334_get_freq(struct adis16400_state *st) 306 293 { ··· 971 984 .self_test_ms = 45, 972 985 }; 973 986 974 974 - static struct adis16400_chip_info adis16400_chips[] = { 975 975 - [ADIS16300] = { 976 976 - .channels = adis16300_channels, 977 977 - .num_channels = ARRAY_SIZE(adis16300_channels), 978 978 - .flags = ADIS16400_HAS_PROD_ID | ADIS16400_HAS_SLOW_MODE | 979 979 - ADIS16400_HAS_SERIAL_NUMBER, 980 980 - .gyro_scale_micro = IIO_DEGREE_TO_RAD(50000), /* 0.05 deg/s */ 981 981 - .accel_scale_micro = 5884, 982 982 - .temp_scale_nano = 140000000, /* 0.14 C */ 983 983 - .temp_offset = 25000000 / 140000, /* 25 C = 0x00 */ 984 984 - .set_freq = adis16400_set_freq, 985 985 - .get_freq = adis16400_get_freq, 986 986 - .adis_data = ADIS16400_DATA(&adis16300_timeouts, 18), 987 987 - }, 988 988 - [ADIS16334] = { 989 989 - .channels = adis16334_channels, 990 990 - .num_channels = ARRAY_SIZE(adis16334_channels), 991 991 - .flags = ADIS16400_HAS_PROD_ID | ADIS16400_NO_BURST | 992 992 - ADIS16400_HAS_SERIAL_NUMBER, 993 993 - .gyro_scale_micro = IIO_DEGREE_TO_RAD(50000), /* 0.05 deg/s */ 994 994 - .accel_scale_micro = IIO_G_TO_M_S_2(1000), /* 1 mg */ 995 995 - .temp_scale_nano = 67850000, /* 0.06785 C */ 996 996 - .temp_offset = 25000000 / 67850, /* 25 C = 0x00 */ 997 997 - .set_freq = adis16334_set_freq, 998 998 - .get_freq = adis16334_get_freq, 999 999 - .adis_data = ADIS16400_DATA(&adis16334_timeouts, 0), 1000 1000 - }, 1001 1001 - [ADIS16350] = { 1002 1002 - .channels = adis16350_channels, 1003 1003 - .num_channels = ARRAY_SIZE(adis16350_channels), 1004 1004 - .gyro_scale_micro = IIO_DEGREE_TO_RAD(73260), /* 0.07326 deg/s */ 1005 1005 - .accel_scale_micro = IIO_G_TO_M_S_2(2522), /* 0.002522 g */ 1006 1006 - .temp_scale_nano = 145300000, /* 0.1453 C */ 1007 1007 - .temp_offset = 25000000 / 145300, /* 25 C = 0x00 */ 1008 1008 - .flags = ADIS16400_NO_BURST | ADIS16400_HAS_SLOW_MODE, 1009 1009 - .set_freq = adis16400_set_freq, 1010 1010 - .get_freq = adis16400_get_freq, 1011 1011 - .adis_data = ADIS16400_DATA(&adis16300_timeouts, 0), 1012 1012 - }, 1013 1013 - [ADIS16360] = { 1014 1014 - .channels = adis16350_channels, 1015 1015 - .num_channels = ARRAY_SIZE(adis16350_channels), 1016 1016 - .flags = ADIS16400_HAS_PROD_ID | ADIS16400_HAS_SLOW_MODE | 1017 1017 - ADIS16400_HAS_SERIAL_NUMBER, 1018 1018 - .gyro_scale_micro = IIO_DEGREE_TO_RAD(50000), /* 0.05 deg/s */ 1019 1019 - .accel_scale_micro = IIO_G_TO_M_S_2(3333), /* 3.333 mg */ 1020 1020 - .temp_scale_nano = 136000000, /* 0.136 C */ 1021 1021 - .temp_offset = 25000000 / 136000, /* 25 C = 0x00 */ 1022 1022 - .set_freq = adis16400_set_freq, 1023 1023 - .get_freq = adis16400_get_freq, 1024 1024 - .adis_data = ADIS16400_DATA(&adis16300_timeouts, 28), 1025 1025 - }, 1026 1026 - [ADIS16362] = { 1027 1027 - .channels = adis16350_channels, 1028 1028 - .num_channels = ARRAY_SIZE(adis16350_channels), 1029 1029 - .flags = ADIS16400_HAS_PROD_ID | ADIS16400_HAS_SLOW_MODE | 1030 1030 - ADIS16400_HAS_SERIAL_NUMBER, 1031 1031 - .gyro_scale_micro = IIO_DEGREE_TO_RAD(50000), /* 0.05 deg/s */ 1032 1032 - .accel_scale_micro = IIO_G_TO_M_S_2(333), /* 0.333 mg */ 1033 1033 - .temp_scale_nano = 136000000, /* 0.136 C */ 1034 1034 - .temp_offset = 25000000 / 136000, /* 25 C = 0x00 */ 1035 1035 - .set_freq = adis16400_set_freq, 1036 1036 - .get_freq = adis16400_get_freq, 1037 1037 - .adis_data = ADIS16400_DATA(&adis16362_timeouts, 28), 1038 1038 - }, 1039 1039 - [ADIS16364] = { 1040 1040 - .channels = adis16350_channels, 1041 1041 - .num_channels = ARRAY_SIZE(adis16350_channels), 1042 1042 - .flags = ADIS16400_HAS_PROD_ID | ADIS16400_HAS_SLOW_MODE | 1043 1043 - ADIS16400_HAS_SERIAL_NUMBER, 1044 1044 - .gyro_scale_micro = IIO_DEGREE_TO_RAD(50000), /* 0.05 deg/s */ 1045 1045 - .accel_scale_micro = IIO_G_TO_M_S_2(1000), /* 1 mg */ 1046 1046 - .temp_scale_nano = 136000000, /* 0.136 C */ 1047 1047 - .temp_offset = 25000000 / 136000, /* 25 C = 0x00 */ 1048 1048 - .set_freq = adis16400_set_freq, 1049 1049 - .get_freq = adis16400_get_freq, 1050 1050 - .adis_data = ADIS16400_DATA(&adis16362_timeouts, 28), 1051 1051 - }, 1052 1052 - [ADIS16367] = { 1053 1053 - .channels = adis16350_channels, 1054 1054 - .num_channels = ARRAY_SIZE(adis16350_channels), 1055 1055 - .flags = ADIS16400_HAS_PROD_ID | ADIS16400_HAS_SLOW_MODE | 1056 1056 - ADIS16400_HAS_SERIAL_NUMBER, 1057 1057 - .gyro_scale_micro = IIO_DEGREE_TO_RAD(2000), /* 0.2 deg/s */ 1058 1058 - .accel_scale_micro = IIO_G_TO_M_S_2(3333), /* 3.333 mg */ 1059 1059 - .temp_scale_nano = 136000000, /* 0.136 C */ 1060 1060 - .temp_offset = 25000000 / 136000, /* 25 C = 0x00 */ 1061 1061 - .set_freq = adis16400_set_freq, 1062 1062 - .get_freq = adis16400_get_freq, 1063 1063 - .adis_data = ADIS16400_DATA(&adis16300_timeouts, 28), 1064 1064 - }, 1065 1065 - [ADIS16400] = { 1066 1066 - .channels = adis16400_channels, 1067 1067 - .num_channels = ARRAY_SIZE(adis16400_channels), 1068 1068 - .flags = ADIS16400_HAS_PROD_ID | ADIS16400_HAS_SLOW_MODE, 1069 1069 - .gyro_scale_micro = IIO_DEGREE_TO_RAD(50000), /* 0.05 deg/s */ 1070 1070 - .accel_scale_micro = IIO_G_TO_M_S_2(3333), /* 3.333 mg */ 1071 1071 - .temp_scale_nano = 140000000, /* 0.14 C */ 1072 1072 - .temp_offset = 25000000 / 140000, /* 25 C = 0x00 */ 1073 1073 - .set_freq = adis16400_set_freq, 1074 1074 - .get_freq = adis16400_get_freq, 1075 1075 - .adis_data = ADIS16400_DATA(&adis16400_timeouts, 24), 1076 1076 - }, 1077 1077 - [ADIS16445] = { 1078 1078 - .channels = adis16445_channels, 1079 1079 - .num_channels = ARRAY_SIZE(adis16445_channels), 1080 1080 - .flags = ADIS16400_HAS_PROD_ID | 1081 1081 - ADIS16400_HAS_SERIAL_NUMBER | 1082 1082 - ADIS16400_BURST_DIAG_STAT, 1083 1083 - .gyro_scale_micro = IIO_DEGREE_TO_RAD(10000), /* 0.01 deg/s */ 1084 1084 - .accel_scale_micro = IIO_G_TO_M_S_2(250), /* 1/4000 g */ 1085 1085 - .temp_scale_nano = 73860000, /* 0.07386 C */ 1086 1086 - .temp_offset = 31000000 / 73860, /* 31 C = 0x00 */ 1087 1087 - .set_freq = adis16334_set_freq, 1088 1088 - .get_freq = adis16334_get_freq, 1089 1089 - .adis_data = ADIS16400_DATA(&adis16445_timeouts, 16), 1090 1090 - }, 1091 1091 - [ADIS16448] = { 1092 1092 - .channels = adis16448_channels, 1093 1093 - .num_channels = ARRAY_SIZE(adis16448_channels), 1094 1094 - .flags = ADIS16400_HAS_PROD_ID | 1095 1095 - ADIS16400_HAS_SERIAL_NUMBER | 1096 1096 - ADIS16400_BURST_DIAG_STAT, 1097 1097 - .gyro_scale_micro = IIO_DEGREE_TO_RAD(40000), /* 0.04 deg/s */ 1098 1098 - .accel_scale_micro = IIO_G_TO_M_S_2(833), /* 1/1200 g */ 1099 1099 - .temp_scale_nano = 73860000, /* 0.07386 C */ 1100 1100 - .temp_offset = 31000000 / 73860, /* 31 C = 0x00 */ 1101 1101 - .set_freq = adis16334_set_freq, 1102 1102 - .get_freq = adis16334_get_freq, 1103 1103 - .adis_data = ADIS16400_DATA(&adis16448_timeouts, 24), 1104 1104 - } 987 987 + static const struct adis16400_chip_info adis16300_chip_info = { 988 988 + .channels = adis16300_channels, 989 989 + .num_channels = ARRAY_SIZE(adis16300_channels), 990 990 + .flags = ADIS16400_HAS_PROD_ID | ADIS16400_HAS_SLOW_MODE | 991 991 + ADIS16400_HAS_SERIAL_NUMBER, 992 992 + .gyro_scale_micro = IIO_DEGREE_TO_RAD(50000), /* 0.05 deg/s */ 993 993 + .accel_scale_micro = 5884, 994 994 + .temp_scale_nano = 140000000, /* 0.14 C */ 995 995 + .temp_offset = 25000000 / 140000, /* 25 C = 0x00 */ 996 996 + .set_freq = adis16400_set_freq, 997 997 + .get_freq = adis16400_get_freq, 998 998 + .adis_data = ADIS16400_DATA(&adis16300_timeouts, 18), 999 999 + }; 1000 1000 + 1001 1001 + static const struct adis16400_chip_info adis16334_chip_info = { 1002 1002 + .channels = adis16334_channels, 1003 1003 + .num_channels = ARRAY_SIZE(adis16334_channels), 1004 1004 + .flags = ADIS16400_HAS_PROD_ID | ADIS16400_NO_BURST | 1005 1005 + ADIS16400_HAS_SERIAL_NUMBER, 1006 1006 + .gyro_scale_micro = IIO_DEGREE_TO_RAD(50000), /* 0.05 deg/s */ 1007 1007 + .accel_scale_micro = IIO_G_TO_M_S_2(1000), /* 1 mg */ 1008 1008 + .temp_scale_nano = 67850000, /* 0.06785 C */ 1009 1009 + .temp_offset = 25000000 / 67850, /* 25 C = 0x00 */ 1010 1010 + .set_freq = adis16334_set_freq, 1011 1011 + .get_freq = adis16334_get_freq, 1012 1012 + .adis_data = ADIS16400_DATA(&adis16334_timeouts, 0), 1013 1013 + }; 1014 1014 + 1015 1015 + static const struct adis16400_chip_info adis16350_chip_info = { 1016 1016 + .channels = adis16350_channels, 1017 1017 + .num_channels = ARRAY_SIZE(adis16350_channels), 1018 1018 + .gyro_scale_micro = IIO_DEGREE_TO_RAD(73260), /* 0.07326 deg/s */ 1019 1019 + .accel_scale_micro = IIO_G_TO_M_S_2(2522), /* 0.002522 g */ 1020 1020 + .temp_scale_nano = 145300000, /* 0.1453 C */ 1021 1021 + .temp_offset = 25000000 / 145300, /* 25 C = 0x00 */ 1022 1022 + .flags = ADIS16400_NO_BURST | ADIS16400_HAS_SLOW_MODE, 1023 1023 + .set_freq = adis16400_set_freq, 1024 1024 + .get_freq = adis16400_get_freq, 1025 1025 + .adis_data = ADIS16400_DATA(&adis16300_timeouts, 0), 1026 1026 + }; 1027 1027 + 1028 1028 + static const struct adis16400_chip_info adis16360_chip_info = { 1029 1029 + .channels = adis16350_channels, 1030 1030 + .num_channels = ARRAY_SIZE(adis16350_channels), 1031 1031 + .flags = ADIS16400_HAS_PROD_ID | ADIS16400_HAS_SLOW_MODE | 1032 1032 + ADIS16400_HAS_SERIAL_NUMBER, 1033 1033 + .gyro_scale_micro = IIO_DEGREE_TO_RAD(50000), /* 0.05 deg/s */ 1034 1034 + .accel_scale_micro = IIO_G_TO_M_S_2(3333), /* 3.333 mg */ 1035 1035 + .temp_scale_nano = 136000000, /* 0.136 C */ 1036 1036 + .temp_offset = 25000000 / 136000, /* 25 C = 0x00 */ 1037 1037 + .set_freq = adis16400_set_freq, 1038 1038 + .get_freq = adis16400_get_freq, 1039 1039 + .adis_data = ADIS16400_DATA(&adis16300_timeouts, 28), 1040 1040 + }; 1041 1041 + 1042 1042 + static const struct adis16400_chip_info adis16362_chip_info = { 1043 1043 + .channels = adis16350_channels, 1044 1044 + .num_channels = ARRAY_SIZE(adis16350_channels), 1045 1045 + .flags = ADIS16400_HAS_PROD_ID | ADIS16400_HAS_SLOW_MODE | 1046 1046 + ADIS16400_HAS_SERIAL_NUMBER, 1047 1047 + .gyro_scale_micro = IIO_DEGREE_TO_RAD(50000), /* 0.05 deg/s */ 1048 1048 + .accel_scale_micro = IIO_G_TO_M_S_2(333), /* 0.333 mg */ 1049 1049 + .temp_scale_nano = 136000000, /* 0.136 C */ 1050 1050 + .temp_offset = 25000000 / 136000, /* 25 C = 0x00 */ 1051 1051 + .set_freq = adis16400_set_freq, 1052 1052 + .get_freq = adis16400_get_freq, 1053 1053 + .adis_data = ADIS16400_DATA(&adis16362_timeouts, 28), 1054 1054 + }; 1055 1055 + 1056 1056 + static const struct adis16400_chip_info adis16364_chip_info = { 1057 1057 + .channels = adis16350_channels, 1058 1058 + .num_channels = ARRAY_SIZE(adis16350_channels), 1059 1059 + .flags = ADIS16400_HAS_PROD_ID | ADIS16400_HAS_SLOW_MODE | 1060 1060 + ADIS16400_HAS_SERIAL_NUMBER, 1061 1061 + .gyro_scale_micro = IIO_DEGREE_TO_RAD(50000), /* 0.05 deg/s */ 1062 1062 + .accel_scale_micro = IIO_G_TO_M_S_2(1000), /* 1 mg */ 1063 1063 + .temp_scale_nano = 136000000, /* 0.136 C */ 1064 1064 + .temp_offset = 25000000 / 136000, /* 25 C = 0x00 */ 1065 1065 + .set_freq = adis16400_set_freq, 1066 1066 + .get_freq = adis16400_get_freq, 1067 1067 + .adis_data = ADIS16400_DATA(&adis16362_timeouts, 28), 1068 1068 + }; 1069 1069 + 1070 1070 + static const struct adis16400_chip_info adis16367_chip_info = { 1071 1071 + .channels = adis16350_channels, 1072 1072 + .num_channels = ARRAY_SIZE(adis16350_channels), 1073 1073 + .flags = ADIS16400_HAS_PROD_ID | ADIS16400_HAS_SLOW_MODE | 1074 1074 + ADIS16400_HAS_SERIAL_NUMBER, 1075 1075 + .gyro_scale_micro = IIO_DEGREE_TO_RAD(2000), /* 0.2 deg/s */ 1076 1076 + .accel_scale_micro = IIO_G_TO_M_S_2(3333), /* 3.333 mg */ 1077 1077 + .temp_scale_nano = 136000000, /* 0.136 C */ 1078 1078 + .temp_offset = 25000000 / 136000, /* 25 C = 0x00 */ 1079 1079 + .set_freq = adis16400_set_freq, 1080 1080 + .get_freq = adis16400_get_freq, 1081 1081 + .adis_data = ADIS16400_DATA(&adis16300_timeouts, 28), 1082 1082 + }; 1083 1083 + 1084 1084 + static const struct adis16400_chip_info adis16400_chip_info = { 1085 1085 + .channels = adis16400_channels, 1086 1086 + .num_channels = ARRAY_SIZE(adis16400_channels), 1087 1087 + .flags = ADIS16400_HAS_PROD_ID | ADIS16400_HAS_SLOW_MODE, 1088 1088 + .gyro_scale_micro = IIO_DEGREE_TO_RAD(50000), /* 0.05 deg/s */ 1089 1089 + .accel_scale_micro = IIO_G_TO_M_S_2(3333), /* 3.333 mg */ 1090 1090 + .temp_scale_nano = 140000000, /* 0.14 C */ 1091 1091 + .temp_offset = 25000000 / 140000, /* 25 C = 0x00 */ 1092 1092 + .set_freq = adis16400_set_freq, 1093 1093 + .get_freq = adis16400_get_freq, 1094 1094 + .adis_data = ADIS16400_DATA(&adis16400_timeouts, 24), 1095 1095 + }; 1096 1096 + 1097 1097 + static const struct adis16400_chip_info adis16445_chip_info = { 1098 1098 + .channels = adis16445_channels, 1099 1099 + .num_channels = ARRAY_SIZE(adis16445_channels), 1100 1100 + .flags = ADIS16400_HAS_PROD_ID | ADIS16400_HAS_SERIAL_NUMBER | 1101 1101 + ADIS16400_BURST_DIAG_STAT, 1102 1102 + .gyro_scale_micro = IIO_DEGREE_TO_RAD(10000), /* 0.01 deg/s */ 1103 1103 + .accel_scale_micro = IIO_G_TO_M_S_2(250), /* 1/4000 g */ 1104 1104 + .temp_scale_nano = 73860000, /* 0.07386 C */ 1105 1105 + .temp_offset = 31000000 / 73860, /* 31 C = 0x00 */ 1106 1106 + .set_freq = adis16334_set_freq, 1107 1107 + .get_freq = adis16334_get_freq, 1108 1108 + .adis_data = ADIS16400_DATA(&adis16445_timeouts, 16), 1109 1109 + }; 1110 1110 + 1111 1111 + static const struct adis16400_chip_info adis16448_chip_info = { 1112 1112 + .channels = adis16448_channels, 1113 1113 + .num_channels = ARRAY_SIZE(adis16448_channels), 1114 1114 + .flags = ADIS16400_HAS_PROD_ID | ADIS16400_HAS_SERIAL_NUMBER | 1115 1115 + ADIS16400_BURST_DIAG_STAT, 1116 1116 + .gyro_scale_micro = IIO_DEGREE_TO_RAD(40000), /* 0.04 deg/s */ 1117 1117 + .accel_scale_micro = IIO_G_TO_M_S_2(833), /* 1/1200 g */ 1118 1118 + .temp_scale_nano = 73860000, /* 0.07386 C */ 1119 1119 + .temp_offset = 31000000 / 73860, /* 31 C = 0x00 */ 1120 1120 + .set_freq = adis16334_set_freq, 1121 1121 + .get_freq = adis16334_get_freq, 1122 1122 + .adis_data = ADIS16400_DATA(&adis16448_timeouts, 24), 1105 1123 }; 1106 1124 1107 1125 static const struct iio_info adis16400_info = { ··· 1149 1157 st = iio_priv(indio_dev); 1150 1158 1151 1159 /* setup the industrialio driver allocated elements */ 1152 1152 - st->variant = &adis16400_chips[spi_get_device_id(spi)->driver_data]; 1160 1160 + st->variant = spi_get_device_match_data(spi); 1153 1161 indio_dev->name = spi_get_device_id(spi)->name; 1154 1162 indio_dev->channels = st->variant->channels; 1155 1163 indio_dev->num_channels = st->variant->num_channels; ··· 1189 1197 } 1190 1198 1191 1199 static const struct spi_device_id adis16400_id[] = { 1192 1192 - {"adis16300", ADIS16300}, 1193 1193 - {"adis16305", ADIS16300}, 1194 1194 - {"adis16334", ADIS16334}, 1195 1195 - {"adis16350", ADIS16350}, 1196 1196 - {"adis16354", ADIS16350}, 1197 1197 - {"adis16355", ADIS16350}, 1198 1198 - {"adis16360", ADIS16360}, 1199 1199 - {"adis16362", ADIS16362}, 1200 1200 - {"adis16364", ADIS16364}, 1201 1201 - {"adis16365", ADIS16360}, 1202 1202 - {"adis16367", ADIS16367}, 1203 1203 - {"adis16400", ADIS16400}, 1204 1204 - {"adis16405", ADIS16400}, 1205 1205 - {"adis16445", ADIS16445}, 1206 1206 - {"adis16448", ADIS16448}, 1200 1200 + { "adis16300", (kernel_ulong_t)&adis16300_chip_info }, 1201 1201 + { "adis16305", (kernel_ulong_t)&adis16300_chip_info }, 1202 1202 + { "adis16334", (kernel_ulong_t)&adis16334_chip_info }, 1203 1203 + { "adis16350", (kernel_ulong_t)&adis16350_chip_info }, 1204 1204 + { "adis16354", (kernel_ulong_t)&adis16350_chip_info }, 1205 1205 + { "adis16355", (kernel_ulong_t)&adis16350_chip_info }, 1206 1206 + { "adis16360", (kernel_ulong_t)&adis16360_chip_info }, 1207 1207 + { "adis16362", (kernel_ulong_t)&adis16362_chip_info }, 1208 1208 + { "adis16364", (kernel_ulong_t)&adis16364_chip_info }, 1209 1209 + { "adis16365", (kernel_ulong_t)&adis16360_chip_info }, 1210 1210 + { "adis16367", (kernel_ulong_t)&adis16367_chip_info }, 1211 1211 + { "adis16400", (kernel_ulong_t)&adis16400_chip_info }, 1212 1212 + { "adis16405", (kernel_ulong_t)&adis16400_chip_info }, 1213 1213 + { "adis16445", (kernel_ulong_t)&adis16445_chip_info }, 1214 1214 + { "adis16448", (kernel_ulong_t)&adis16448_chip_info }, 1207 1215 { } 1208 1216 }; 1209 1217 MODULE_DEVICE_TABLE(spi, adis16400_id);

+2

drivers/iio/imu/bmi160/bmi160.h

reviewed

··· 28 28 29 29 int bmi160_probe_trigger(struct iio_dev *indio_dev, int irq, u32 irq_type); 30 30 31 31 + extern const struct dev_pm_ops bmi160_core_pm_ops; 32 32 + 31 33 #endif /* BMI160_H_ */

+20 -1

drivers/iio/imu/bmi160/bmi160_core.c

reviewed

··· 161 161 u8 pmu_cmd_suspend; 162 162 }; 163 163 164 164 - static struct bmi160_regs bmi160_regs[] = { 164 164 + static const struct bmi160_regs bmi160_regs[] = { 165 165 [BMI160_ACCEL] = { 166 166 .data = BMI160_REG_DATA_ACCEL_XOUT_L, 167 167 .config = BMI160_REG_ACCEL_CONFIG, ··· 889 889 return devm_iio_device_register(dev, indio_dev); 890 890 } 891 891 EXPORT_SYMBOL_NS_GPL(bmi160_core_probe, "IIO_BMI160"); 892 892 + 893 893 + static int bmi160_core_runtime_suspend(struct device *dev) 894 894 + { 895 895 + struct iio_dev *indio_dev = dev_get_drvdata(dev); 896 896 + 897 897 + return iio_device_suspend_triggering(indio_dev); 898 898 + } 899 899 + 900 900 + static int bmi160_core_runtime_resume(struct device *dev) 901 901 + { 902 902 + struct iio_dev *indio_dev = dev_get_drvdata(dev); 903 903 + 904 904 + return iio_device_resume_triggering(indio_dev); 905 905 + } 906 906 + 907 907 + const struct dev_pm_ops bmi160_core_pm_ops = { 908 908 + RUNTIME_PM_OPS(bmi160_core_runtime_suspend, bmi160_core_runtime_resume, NULL) 909 909 + }; 910 910 + EXPORT_SYMBOL_NS_GPL(bmi160_core_pm_ops, "IIO_BMI160"); 892 911 893 912 MODULE_AUTHOR("Daniel Baluta <daniel.baluta@intel.com>"); 894 913 MODULE_DESCRIPTION("Bosch BMI160 driver");

+2

drivers/iio/imu/bmi160/bmi160_i2c.c

reviewed

··· 11 11 #include <linux/i2c.h> 12 12 #include <linux/mod_devicetable.h> 13 13 #include <linux/module.h> 14 14 + #include <linux/pm.h> 14 15 #include <linux/regmap.h> 15 16 16 17 #include "bmi160.h" ··· 70 69 static struct i2c_driver bmi160_i2c_driver = { 71 70 .driver = { 72 71 .name = "bmi160_i2c", 72 72 + .pm = pm_ptr(&bmi160_core_pm_ops), 73 73 .acpi_match_table = bmi160_acpi_match, 74 74 .of_match_table = bmi160_of_match, 75 75 },

+2

drivers/iio/imu/bmi160/bmi160_spi.c

reviewed

··· 7 7 */ 8 8 #include <linux/mod_devicetable.h> 9 9 #include <linux/module.h> 10 10 + #include <linux/pm.h> 10 11 #include <linux/regmap.h> 11 12 #include <linux/spi/spi.h> 12 13 ··· 62 61 .acpi_match_table = bmi160_acpi_match, 63 62 .of_match_table = bmi160_of_match, 64 63 .name = "bmi160_spi", 64 64 + .pm = pm_ptr(&bmi160_core_pm_ops), 65 65 }, 66 66 }; 67 67 module_spi_driver(bmi160_spi_driver);

+2

drivers/iio/imu/bmi270/bmi270.h

reviewed

··· 20 20 int bmi270_core_probe(struct device *dev, struct regmap *regmap, 21 21 const struct bmi270_chip_info *chip_info); 22 22 23 23 + extern const struct dev_pm_ops bmi270_core_pm_ops; 24 24 + 23 25 #endif /* BMI270_H_ */

+324 -3

drivers/iio/imu/bmi270/bmi270_core.c

reviewed

··· 8 8 #include <linux/regmap.h> 9 9 #include <linux/units.h> 10 10 11 11 + #include <linux/iio/events.h> 11 12 #include <linux/iio/iio.h> 12 13 #include <linux/iio/sysfs.h> 13 14 #include <linux/iio/trigger.h> ··· 29 28 #define BMI270_ACCEL_X_REG 0x0c 30 29 #define BMI270_ANG_VEL_X_REG 0x12 31 30 31 31 + #define BMI270_INT_STATUS_0_REG 0x1c 32 32 + #define BMI270_INT_STATUS_0_STEP_CNT_MSK BIT(1) 33 33 + 32 34 #define BMI270_INT_STATUS_1_REG 0x1d 33 35 #define BMI270_INT_STATUS_1_ACC_GYR_DRDY_MSK GENMASK(7, 6) 36 36 + 37 37 + #define BMI270_SC_OUT_0_REG 0x1e 34 38 35 39 #define BMI270_INTERNAL_STATUS_REG 0x21 36 40 #define BMI270_INTERNAL_STATUS_MSG_MSK GENMASK(3, 0) ··· 44 38 #define BMI270_INTERNAL_STATUS_ODR_50HZ_ERR_MSK BIT(6) 45 39 46 40 #define BMI270_TEMPERATURE_0_REG 0x22 41 41 + 42 42 + #define BMI270_FEAT_PAGE_REG 0x2f 47 43 48 44 #define BMI270_ACC_CONF_REG 0x40 49 45 #define BMI270_ACC_CONF_ODR_MSK GENMASK(3, 0) ··· 78 70 #define BMI270_INT_LATCH_REG 0x55 79 71 #define BMI270_INT_LATCH_REG_MSK BIT(0) 80 72 73 73 + #define BMI270_INT1_MAP_FEAT_REG 0x56 74 74 + #define BMI270_INT2_MAP_FEAT_REG 0x57 75 75 + #define BMI270_INT_MAP_FEAT_STEP_CNT_WTRMRK_MSK BIT(1) 76 76 + 81 77 #define BMI270_INT_MAP_DATA_REG 0x58 82 78 #define BMI270_INT_MAP_DATA_DRDY_INT1_MSK BIT(2) 83 79 #define BMI270_INT_MAP_DATA_DRDY_INT2_MSK BIT(6) ··· 102 90 #define BMI270_PWR_CTRL_ACCEL_EN_MSK BIT(2) 103 91 #define BMI270_PWR_CTRL_TEMP_EN_MSK BIT(3) 104 92 93 93 + #define BMI270_STEP_SC26_WTRMRK_MSK GENMASK(9, 0) 94 94 + #define BMI270_STEP_SC26_RST_CNT_MSK BIT(10) 95 95 + #define BMI270_STEP_SC26_EN_CNT_MSK BIT(12) 96 96 + 105 97 /* See datasheet section 4.6.14, Temperature Sensor */ 106 98 #define BMI270_TEMP_OFFSET 11776 107 99 #define BMI270_TEMP_SCALE 1953125 100 100 + 101 101 + /* See page 90 of datasheet. The step counter "holds implicitly a 20x factor" */ 102 102 + #define BMI270_STEP_COUNTER_FACTOR 20 103 103 + #define BMI270_STEP_COUNTER_MAX 20460 108 104 109 105 #define BMI260_INIT_DATA_FILE "bmi260-init-data.fw" 110 106 #define BMI270_INIT_DATA_FILE "bmi270-init-data.fw" ··· 131 111 struct iio_trigger *trig; 132 112 /* Protect device's private data from concurrent access */ 133 113 struct mutex mutex; 114 114 + bool steps_enabled; 134 115 135 116 /* 136 117 * Where IIO_DMA_MINALIGN may be larger than 8 bytes, align to ··· 141 120 __le16 channels[6]; 142 121 aligned_s64 timestamp; 143 122 } buffer __aligned(IIO_DMA_MINALIGN); 123 123 + /* 124 124 + * Variable to access feature registers. It can be accessed concurrently 125 125 + * with the 'buffer' variable 126 126 + */ 127 127 + __le16 regval __aligned(IIO_DMA_MINALIGN); 144 128 }; 145 129 146 130 enum bmi270_scan { ··· 308 282 }, 309 283 }; 310 284 285 285 + enum bmi270_feature_reg_id { 286 286 + BMI270_SC_26_REG, 287 287 + }; 288 288 + 289 289 + struct bmi270_feature_reg { 290 290 + u8 page; 291 291 + u8 addr; 292 292 + }; 293 293 + 294 294 + static const struct bmi270_feature_reg bmi270_feature_regs[] = { 295 295 + [BMI270_SC_26_REG] = { 296 296 + .page = 6, 297 297 + .addr = 0x32, 298 298 + }, 299 299 + }; 300 300 + 301 301 + static int bmi270_write_feature_reg(struct bmi270_data *data, 302 302 + enum bmi270_feature_reg_id id, 303 303 + u16 val) 304 304 + { 305 305 + const struct bmi270_feature_reg *reg = &bmi270_feature_regs[id]; 306 306 + int ret; 307 307 + 308 308 + ret = regmap_write(data->regmap, BMI270_FEAT_PAGE_REG, reg->page); 309 309 + if (ret) 310 310 + return ret; 311 311 + 312 312 + data->regval = cpu_to_le16(val); 313 313 + return regmap_bulk_write(data->regmap, reg->addr, &data->regval, 314 314 + sizeof(data->regval)); 315 315 + } 316 316 + 317 317 + static int bmi270_read_feature_reg(struct bmi270_data *data, 318 318 + enum bmi270_feature_reg_id id, 319 319 + u16 *val) 320 320 + { 321 321 + const struct bmi270_feature_reg *reg = &bmi270_feature_regs[id]; 322 322 + int ret; 323 323 + 324 324 + ret = regmap_write(data->regmap, BMI270_FEAT_PAGE_REG, reg->page); 325 325 + if (ret) 326 326 + return ret; 327 327 + 328 328 + ret = regmap_bulk_read(data->regmap, reg->addr, &data->regval, 329 329 + sizeof(data->regval)); 330 330 + if (ret) 331 331 + return ret; 332 332 + 333 333 + *val = le16_to_cpu(data->regval); 334 334 + return 0; 335 335 + } 336 336 + 337 337 + static int bmi270_update_feature_reg(struct bmi270_data *data, 338 338 + enum bmi270_feature_reg_id id, 339 339 + u16 mask, u16 val) 340 340 + { 341 341 + u16 regval; 342 342 + int ret; 343 343 + 344 344 + ret = bmi270_read_feature_reg(data, id, &regval); 345 345 + if (ret) 346 346 + return ret; 347 347 + 348 348 + regval = (regval & ~mask) | (val & mask); 349 349 + 350 350 + return bmi270_write_feature_reg(data, id, regval); 351 351 + } 352 352 + 353 353 + static int bmi270_enable_steps(struct bmi270_data *data, int val) 354 354 + { 355 355 + int ret; 356 356 + 357 357 + guard(mutex)(&data->mutex); 358 358 + if (data->steps_enabled) 359 359 + return 0; 360 360 + 361 361 + ret = bmi270_update_feature_reg(data, BMI270_SC_26_REG, 362 362 + BMI270_STEP_SC26_EN_CNT_MSK, 363 363 + FIELD_PREP(BMI270_STEP_SC26_EN_CNT_MSK, 364 364 + val ? 1 : 0)); 365 365 + if (ret) 366 366 + return ret; 367 367 + 368 368 + data->steps_enabled = true; 369 369 + return 0; 370 370 + } 371 371 + 372 372 + static int bmi270_read_steps(struct bmi270_data *data, int *val) 373 373 + { 374 374 + __le16 steps_count; 375 375 + int ret; 376 376 + 377 377 + ret = regmap_bulk_read(data->regmap, BMI270_SC_OUT_0_REG, &steps_count, 378 378 + sizeof(steps_count)); 379 379 + if (ret) 380 380 + return ret; 381 381 + 382 382 + *val = sign_extend32(le16_to_cpu(steps_count), 15); 383 383 + return IIO_VAL_INT; 384 384 + } 385 385 + 386 386 + static int bmi270_int_map_reg(enum bmi270_irq_pin pin) 387 387 + { 388 388 + switch (pin) { 389 389 + case BMI270_IRQ_INT1: 390 390 + return BMI270_INT1_MAP_FEAT_REG; 391 391 + case BMI270_IRQ_INT2: 392 392 + return BMI270_INT2_MAP_FEAT_REG; 393 393 + default: 394 394 + return -EINVAL; 395 395 + } 396 396 + } 397 397 + 398 398 + static int bmi270_step_wtrmrk_en(struct bmi270_data *data, bool state) 399 399 + { 400 400 + int reg; 401 401 + 402 402 + guard(mutex)(&data->mutex); 403 403 + if (!data->steps_enabled) 404 404 + return -EINVAL; 405 405 + 406 406 + reg = bmi270_int_map_reg(data->irq_pin); 407 407 + if (reg < 0) 408 408 + return reg; 409 409 + 410 410 + return regmap_update_bits(data->regmap, reg, 411 411 + BMI270_INT_MAP_FEAT_STEP_CNT_WTRMRK_MSK, 412 412 + FIELD_PREP(BMI270_INT_MAP_FEAT_STEP_CNT_WTRMRK_MSK, 413 413 + state)); 414 414 + } 415 415 + 311 416 static int bmi270_set_scale(struct bmi270_data *data, int chan_type, int uscale) 312 417 { 313 418 int i; ··· 595 438 { 596 439 struct iio_dev *indio_dev = private; 597 440 struct bmi270_data *data = iio_priv(indio_dev); 598 598 - unsigned int status; 441 441 + unsigned int status0, status1; 442 442 + s64 timestamp = iio_get_time_ns(indio_dev); 599 443 int ret; 600 444 601 445 scoped_guard(mutex, &data->mutex) { 446 446 + ret = regmap_read(data->regmap, BMI270_INT_STATUS_0_REG, 447 447 + &status0); 448 448 + if (ret) 449 449 + return IRQ_NONE; 450 450 + 602 451 ret = regmap_read(data->regmap, BMI270_INT_STATUS_1_REG, 603 603 - &status); 452 452 + &status1); 604 453 if (ret) 605 454 return IRQ_NONE; 606 455 } 607 456 608 608 - if (FIELD_GET(BMI270_INT_STATUS_1_ACC_GYR_DRDY_MSK, status)) 457 457 + if (FIELD_GET(BMI270_INT_STATUS_1_ACC_GYR_DRDY_MSK, status1)) 609 458 iio_trigger_poll_nested(data->trig); 459 459 + 460 460 + if (FIELD_GET(BMI270_INT_STATUS_0_STEP_CNT_MSK, status0)) 461 461 + iio_push_event(indio_dev, IIO_UNMOD_EVENT_CODE(IIO_STEPS, 0, 462 462 + IIO_EV_TYPE_CHANGE, 463 463 + IIO_EV_DIR_NONE), 464 464 + timestamp); 610 465 611 466 return IRQ_HANDLED; 612 467 } ··· 720 551 struct bmi270_data *data = iio_priv(indio_dev); 721 552 722 553 switch (mask) { 554 554 + case IIO_CHAN_INFO_PROCESSED: 555 555 + return bmi270_read_steps(data, val); 723 556 case IIO_CHAN_INFO_RAW: 724 557 if (!iio_device_claim_direct(indio_dev)) 725 558 return -EBUSY; ··· 742 571 case IIO_CHAN_INFO_SAMP_FREQ: 743 572 ret = bmi270_get_odr(data, chan->type, val, val2); 744 573 return ret ? ret : IIO_VAL_INT_PLUS_MICRO; 574 574 + case IIO_CHAN_INFO_ENABLE: 575 575 + *val = data->steps_enabled ? 1 : 0; 576 576 + return IIO_VAL_INT; 745 577 default: 746 578 return -EINVAL; 747 579 } ··· 770 596 ret = bmi270_set_odr(data, chan->type, val, val2); 771 597 iio_device_release_direct(indio_dev); 772 598 return ret; 599 599 + case IIO_CHAN_INFO_ENABLE: 600 600 + return bmi270_enable_steps(data, val); 601 601 + case IIO_CHAN_INFO_PROCESSED: { 602 602 + if (val || !data->steps_enabled) 603 603 + return -EINVAL; 604 604 + 605 605 + guard(mutex)(&data->mutex); 606 606 + /* Clear step counter value */ 607 607 + return bmi270_update_feature_reg(data, BMI270_SC_26_REG, 608 608 + BMI270_STEP_SC26_RST_CNT_MSK, 609 609 + FIELD_PREP(BMI270_STEP_SC26_RST_CNT_MSK, 610 610 + 1)); 611 611 + } 773 612 default: 774 613 return -EINVAL; 775 614 } ··· 827 640 } 828 641 } 829 642 643 643 + static int bmi270_write_event_config(struct iio_dev *indio_dev, 644 644 + const struct iio_chan_spec *chan, 645 645 + enum iio_event_type type, 646 646 + enum iio_event_direction dir, bool state) 647 647 + { 648 648 + struct bmi270_data *data = iio_priv(indio_dev); 649 649 + 650 650 + switch (type) { 651 651 + case IIO_EV_TYPE_CHANGE: 652 652 + return bmi270_step_wtrmrk_en(data, state); 653 653 + default: 654 654 + return -EINVAL; 655 655 + } 656 656 + } 657 657 + 658 658 + static int bmi270_read_event_config(struct iio_dev *indio_dev, 659 659 + const struct iio_chan_spec *chan, 660 660 + enum iio_event_type type, 661 661 + enum iio_event_direction dir) 662 662 + { 663 663 + struct bmi270_data *data = iio_priv(indio_dev); 664 664 + int ret, reg, regval; 665 665 + 666 666 + guard(mutex)(&data->mutex); 667 667 + 668 668 + switch (chan->type) { 669 669 + case IIO_STEPS: 670 670 + reg = bmi270_int_map_reg(data->irq_pin); 671 671 + if (reg) 672 672 + return reg; 673 673 + 674 674 + ret = regmap_read(data->regmap, reg, &regval); 675 675 + if (ret) 676 676 + return ret; 677 677 + return FIELD_GET(BMI270_INT_MAP_FEAT_STEP_CNT_WTRMRK_MSK, 678 678 + regval) ? 1 : 0; 679 679 + default: 680 680 + return -EINVAL; 681 681 + } 682 682 + } 683 683 + 684 684 + static int bmi270_write_event_value(struct iio_dev *indio_dev, 685 685 + const struct iio_chan_spec *chan, 686 686 + enum iio_event_type type, 687 687 + enum iio_event_direction dir, 688 688 + enum iio_event_info info, 689 689 + int val, int val2) 690 690 + { 691 691 + struct bmi270_data *data = iio_priv(indio_dev); 692 692 + unsigned int raw; 693 693 + 694 694 + guard(mutex)(&data->mutex); 695 695 + 696 696 + switch (type) { 697 697 + case IIO_EV_TYPE_CHANGE: 698 698 + if (!in_range(val, 0, BMI270_STEP_COUNTER_MAX + 1)) 699 699 + return -EINVAL; 700 700 + 701 701 + raw = val / BMI270_STEP_COUNTER_FACTOR; 702 702 + return bmi270_update_feature_reg(data, BMI270_SC_26_REG, 703 703 + BMI270_STEP_SC26_WTRMRK_MSK, 704 704 + FIELD_PREP(BMI270_STEP_SC26_WTRMRK_MSK, 705 705 + raw)); 706 706 + default: 707 707 + return -EINVAL; 708 708 + } 709 709 + } 710 710 + 711 711 + static int bmi270_read_event_value(struct iio_dev *indio_dev, 712 712 + const struct iio_chan_spec *chan, 713 713 + enum iio_event_type type, 714 714 + enum iio_event_direction dir, 715 715 + enum iio_event_info info, 716 716 + int *val, int *val2) 717 717 + { 718 718 + struct bmi270_data *data = iio_priv(indio_dev); 719 719 + unsigned int raw; 720 720 + u16 regval; 721 721 + int ret; 722 722 + 723 723 + guard(mutex)(&data->mutex); 724 724 + 725 725 + switch (type) { 726 726 + case IIO_EV_TYPE_CHANGE: 727 727 + ret = bmi270_read_feature_reg(data, BMI270_SC_26_REG, &regval); 728 728 + if (ret) 729 729 + return ret; 730 730 + 731 731 + raw = FIELD_GET(BMI270_STEP_SC26_WTRMRK_MSK, regval); 732 732 + *val = raw * BMI270_STEP_COUNTER_FACTOR; 733 733 + return IIO_VAL_INT; 734 734 + default: 735 735 + return -EINVAL; 736 736 + } 737 737 + } 738 738 + 739 739 + static const struct iio_event_spec bmi270_step_wtrmrk_event = { 740 740 + .type = IIO_EV_TYPE_CHANGE, 741 741 + .dir = IIO_EV_DIR_NONE, 742 742 + .mask_shared_by_type = BIT(IIO_EV_INFO_ENABLE) | BIT(IIO_EV_INFO_VALUE), 743 743 + }; 744 744 + 830 745 static const struct iio_info bmi270_info = { 831 746 .read_raw = bmi270_read_raw, 832 747 .write_raw = bmi270_write_raw, 833 748 .read_avail = bmi270_read_avail, 749 749 + .write_event_config = bmi270_write_event_config, 750 750 + .read_event_config = bmi270_read_event_config, 751 751 + .write_event_value = bmi270_write_event_value, 752 752 + .read_event_value = bmi270_read_event_value, 834 753 }; 835 754 836 755 #define BMI270_ACCEL_CHANNEL(_axis) { \ ··· 990 697 BIT(IIO_CHAN_INFO_SCALE) | 991 698 BIT(IIO_CHAN_INFO_OFFSET), 992 699 .scan_index = -1, /* No buffer support */ 700 700 + }, 701 701 + { 702 702 + .type = IIO_STEPS, 703 703 + .info_mask_separate = BIT(IIO_CHAN_INFO_ENABLE) | 704 704 + BIT(IIO_CHAN_INFO_PROCESSED), 705 705 + .scan_index = -1, /* No buffer support */ 706 706 + .event_spec = &bmi270_step_wtrmrk_event, 707 707 + .num_event_specs = 1, 993 708 }, 994 709 IIO_CHAN_SOFT_TIMESTAMP(BMI270_SCAN_TIMESTAMP), 995 710 }; ··· 1283 982 indio_dev->available_scan_masks = bmi270_avail_scan_masks; 1284 983 indio_dev->modes = INDIO_DIRECT_MODE; 1285 984 indio_dev->info = &bmi270_info; 985 985 + dev_set_drvdata(data->dev, indio_dev); 1286 986 1287 987 ret = bmi270_trigger_probe(data, indio_dev); 1288 988 if (ret) ··· 1298 996 return devm_iio_device_register(dev, indio_dev); 1299 997 } 1300 998 EXPORT_SYMBOL_NS_GPL(bmi270_core_probe, "IIO_BMI270"); 999 999 + 1000 1000 + static int bmi270_core_runtime_suspend(struct device *dev) 1001 1001 + { 1002 1002 + struct iio_dev *indio_dev = dev_get_drvdata(dev); 1003 1003 + 1004 1004 + return iio_device_suspend_triggering(indio_dev); 1005 1005 + } 1006 1006 + 1007 1007 + static int bmi270_core_runtime_resume(struct device *dev) 1008 1008 + { 1009 1009 + struct iio_dev *indio_dev = dev_get_drvdata(dev); 1010 1010 + 1011 1011 + return iio_device_resume_triggering(indio_dev); 1012 1012 + } 1013 1013 + 1014 1014 + const struct dev_pm_ops bmi270_core_pm_ops = { 1015 1015 + RUNTIME_PM_OPS(bmi270_core_runtime_suspend, bmi270_core_runtime_resume, NULL) 1016 1016 + }; 1017 1017 + EXPORT_SYMBOL_NS_GPL(bmi270_core_pm_ops, "IIO_BMI270"); 1301 1018 1302 1019 MODULE_AUTHOR("Alex Lanzano"); 1303 1020 MODULE_DESCRIPTION("BMI270 driver");

+2

drivers/iio/imu/bmi270/bmi270_i2c.c

reviewed

··· 4 4 #include <linux/iio/iio.h> 5 5 #include <linux/module.h> 6 6 #include <linux/mod_devicetable.h> 7 7 + #include <linux/pm.h> 7 8 #include <linux/regmap.h> 8 9 9 10 #include "bmi270.h" ··· 53 52 static struct i2c_driver bmi270_i2c_driver = { 54 53 .driver = { 55 54 .name = "bmi270_i2c", 55 55 + .pm = pm_ptr(&bmi270_core_pm_ops), 56 56 .acpi_match_table = bmi270_acpi_match, 57 57 .of_match_table = bmi270_of_match, 58 58 },

+2

drivers/iio/imu/bmi270/bmi270_spi.c

reviewed

··· 3 3 #include <linux/iio/iio.h> 4 4 #include <linux/mod_devicetable.h> 5 5 #include <linux/module.h> 6 6 + #include <linux/pm.h> 6 7 #include <linux/regmap.h> 7 8 #include <linux/spi/spi.h> 8 9 ··· 80 79 static struct spi_driver bmi270_spi_driver = { 81 80 .driver = { 82 81 .name = "bmi270", 82 82 + .pm = pm_ptr(&bmi270_core_pm_ops), 83 83 .of_match_table = bmi270_of_match, 84 84 }, 85 85 .probe = bmi270_spi_probe,

+33 -25

drivers/iio/imu/bno055/bno055.c

reviewed

··· 114 114 #define BNO055_UID_LEN 16 115 115 116 116 struct bno055_sysfs_attr { 117 117 - int *vals; 117 117 + const int *vals; 118 118 int len; 119 119 - int *fusion_vals; 120 120 - int *hw_xlate; 119 119 + const int *fusion_vals; 120 120 + const int *hw_xlate; 121 121 + int hw_xlate_len; 121 122 int type; 122 123 }; 123 124 124 124 - static int bno055_acc_lpf_vals[] = { 125 125 + static const int bno055_acc_lpf_vals[] = { 125 126 7, 810000, 15, 630000, 31, 250000, 62, 500000, 126 127 125, 0, 250, 0, 500, 0, 1000, 0, 127 128 }; 128 129 129 129 - static struct bno055_sysfs_attr bno055_acc_lpf = { 130 130 + static const struct bno055_sysfs_attr bno055_acc_lpf = { 130 131 .vals = bno055_acc_lpf_vals, 131 132 .len = ARRAY_SIZE(bno055_acc_lpf_vals), 132 132 - .fusion_vals = (int[]){62, 500000}, 133 133 + .fusion_vals = (const int[]){62, 500000}, 133 134 .type = IIO_VAL_INT_PLUS_MICRO, 134 135 }; 135 136 136 136 - static int bno055_acc_range_vals[] = { 137 137 + static const int bno055_acc_range_vals[] = { 137 138 /* G: 2, 4, 8, 16 */ 138 139 1962, 3924, 7848, 15696 139 140 }; 140 141 141 141 - static struct bno055_sysfs_attr bno055_acc_range = { 142 142 + static const struct bno055_sysfs_attr bno055_acc_range = { 142 143 .vals = bno055_acc_range_vals, 143 144 .len = ARRAY_SIZE(bno055_acc_range_vals), 144 144 - .fusion_vals = (int[]){3924}, /* 4G */ 145 145 + .fusion_vals = (const int[]){3924}, /* 4G */ 145 146 .type = IIO_VAL_INT, 146 147 }; 147 148 ··· 166 165 * = hwval * (dps_range/(2^15 * k)) 167 166 * where k is rad-to-deg factor 168 167 */ 169 169 - static int bno055_gyr_scale_vals[] = { 168 168 + static const int bno055_gyr_scale_vals[] = { 170 169 125, 1877467, 250, 1877467, 500, 1877467, 171 170 1000, 1877467, 2000, 1877467, 172 171 }; 173 172 174 174 - static struct bno055_sysfs_attr bno055_gyr_scale = { 173 173 + static const int bno055_gyr_scale_hw_xlate[] = {0, 1, 2, 3, 4}; 174 174 + static const struct bno055_sysfs_attr bno055_gyr_scale = { 175 175 .vals = bno055_gyr_scale_vals, 176 176 .len = ARRAY_SIZE(bno055_gyr_scale_vals), 177 177 - .fusion_vals = (int[]){1, 900}, 178 178 - .hw_xlate = (int[]){4, 3, 2, 1, 0}, 177 177 + .fusion_vals = (const int[]){1, 900}, 178 178 + .hw_xlate = bno055_gyr_scale_hw_xlate, 179 179 + .hw_xlate_len = ARRAY_SIZE(bno055_gyr_scale_hw_xlate), 179 180 .type = IIO_VAL_FRACTIONAL, 180 181 }; 181 182 182 182 - static int bno055_gyr_lpf_vals[] = {12, 23, 32, 47, 64, 116, 230, 523}; 183 183 - static struct bno055_sysfs_attr bno055_gyr_lpf = { 183 183 + static const int bno055_gyr_lpf_vals[] = {12, 23, 32, 47, 64, 116, 230, 523}; 184 184 + static const int bno055_gyr_lpf_hw_xlate[] = {5, 4, 7, 3, 6, 2, 1, 0}; 185 185 + static const struct bno055_sysfs_attr bno055_gyr_lpf = { 184 186 .vals = bno055_gyr_lpf_vals, 185 187 .len = ARRAY_SIZE(bno055_gyr_lpf_vals), 186 186 - .fusion_vals = (int[]){32}, 187 187 - .hw_xlate = (int[]){5, 4, 7, 3, 6, 2, 1, 0}, 188 188 + .fusion_vals = (const int[]){32}, 189 189 + .hw_xlate = bno055_gyr_lpf_hw_xlate, 190 190 + .hw_xlate_len = ARRAY_SIZE(bno055_gyr_lpf_hw_xlate), 188 191 .type = IIO_VAL_INT, 189 192 }; 190 193 191 191 - static int bno055_mag_odr_vals[] = {2, 6, 8, 10, 15, 20, 25, 30}; 192 192 - static struct bno055_sysfs_attr bno055_mag_odr = { 194 194 + static const int bno055_mag_odr_vals[] = {2, 6, 8, 10, 15, 20, 25, 30}; 195 195 + static const struct bno055_sysfs_attr bno055_mag_odr = { 193 196 .vals = bno055_mag_odr_vals, 194 197 .len = ARRAY_SIZE(bno055_mag_odr_vals), 195 195 - .fusion_vals = (int[]){20}, 198 198 + .fusion_vals = (const int[]){20}, 196 199 .type = IIO_VAL_INT, 197 200 }; 198 201 ··· 295 290 .max_register = 0x80 * 2, 296 291 .writeable_reg = bno055_regmap_writeable, 297 292 .readable_reg = bno055_regmap_readable, 298 298 - .cache_type = REGCACHE_RBTREE, 293 293 + .cache_type = REGCACHE_MAPLE, 299 294 }; 300 295 EXPORT_SYMBOL_NS_GPL(bno055_regmap_config, "IIO_BNO055"); 301 296 ··· 553 548 }; 554 549 555 550 static int bno055_get_regmask(struct bno055_priv *priv, int *val, int *val2, 556 556 - int reg, int mask, struct bno055_sysfs_attr *attr) 551 551 + int reg, int mask, 552 552 + const struct bno055_sysfs_attr *attr) 557 553 { 558 554 const int shift = __ffs(mask); 559 555 int hwval, idx; ··· 567 561 568 562 idx = (hwval & mask) >> shift; 569 563 if (attr->hw_xlate) 570 570 - for (i = 0; i < attr->len; i++) 564 564 + for (i = 0; i < attr->hw_xlate_len; i++) 571 565 if (attr->hw_xlate[i] == idx) { 572 566 idx = i; 573 567 break; ··· 583 577 } 584 578 585 579 static int bno055_set_regmask(struct bno055_priv *priv, int val, int val2, 586 586 - int reg, int mask, struct bno055_sysfs_attr *attr) 580 580 + int reg, int mask, 581 581 + const struct bno055_sysfs_attr *attr) 587 582 { 588 583 const int shift = __ffs(mask); 589 584 int best_delta; ··· 765 758 } 766 759 } 767 760 768 768 - static int bno055_sysfs_attr_avail(struct bno055_priv *priv, struct bno055_sysfs_attr *attr, 761 761 + static int bno055_sysfs_attr_avail(struct bno055_priv *priv, 762 762 + const struct bno055_sysfs_attr *attr, 769 763 const int **vals, int *length) 770 764 { 771 765 if (priv->operation_mode != BNO055_OPR_MODE_AMG) {

+55 -7

drivers/iio/imu/inv_icm42600/inv_icm42600.h

reviewed

··· 135 135 bool temp; 136 136 }; 137 137 138 138 + struct inv_icm42600_apex { 139 139 + unsigned int on; 140 140 + struct { 141 141 + u64 value; 142 142 + bool enable; 143 143 + } wom; 144 144 + }; 145 145 + 138 146 /** 139 147 * struct inv_icm42600_state - driver state variables 140 148 * @lock: lock for serializing multiple registers access. ··· 151 143 * @map: regmap pointer. 152 144 * @vdd_supply: VDD voltage regulator for the chip. 153 145 * @vddio_supply: I/O voltage regulator for the chip. 146 146 + * @irq: chip irq, required to enable/disable and set wakeup 154 147 * @orientation: sensor chip orientation relative to main hardware. 155 148 * @conf: chip sensors configurations. 156 149 * @suspended: suspended sensors configuration. 157 150 * @indio_gyro: gyroscope IIO device. 158 151 * @indio_accel: accelerometer IIO device. 159 159 - * @buffer: data transfer buffer aligned for DMA. 160 160 - * @fifo: FIFO management structure. 161 152 * @timestamp: interrupt timestamps. 153 153 + * @apex: APEX (Advanced Pedometer and Event detection) management 154 154 + * @fifo: FIFO management structure. 155 155 + * @buffer: data transfer buffer aligned for DMA. 162 156 */ 163 157 struct inv_icm42600_state { 164 158 struct mutex lock; ··· 169 159 struct regmap *map; 170 160 struct regulator *vdd_supply; 171 161 struct regulator *vddio_supply; 162 162 + int irq; 172 163 struct iio_mount_matrix orientation; 173 164 struct inv_icm42600_conf conf; 174 165 struct inv_icm42600_suspended suspended; 175 166 struct iio_dev *indio_gyro; 176 167 struct iio_dev *indio_accel; 177 177 - uint8_t buffer[2] __aligned(IIO_DMA_MINALIGN); 178 178 - struct inv_icm42600_fifo fifo; 179 168 struct { 180 180 - int64_t gyro; 181 181 - int64_t accel; 169 169 + s64 gyro; 170 170 + s64 accel; 182 171 } timestamp; 172 172 + struct inv_icm42600_apex apex; 173 173 + struct inv_icm42600_fifo fifo; 174 174 + u8 buffer[3] __aligned(IIO_DMA_MINALIGN); 183 175 }; 184 176 185 177 ··· 265 253 #define INV_ICM42600_REG_FIFO_COUNT 0x002E 266 254 #define INV_ICM42600_REG_FIFO_DATA 0x0030 267 255 256 256 + #define INV_ICM42600_REG_INT_STATUS2 0x0037 257 257 + #define INV_ICM42600_INT_STATUS2_SMD_INT BIT(3) 258 258 + #define INV_ICM42600_INT_STATUS2_WOM_INT GENMASK(2, 0) 259 259 + 260 260 + #define INV_ICM42600_REG_INT_STATUS3 0x0038 261 261 + #define INV_ICM42600_INT_STATUS3_STEP_DET_INT BIT(5) 262 262 + #define INV_ICM42600_INT_STATUS3_STEP_CNT_OVF_INT BIT(4) 263 263 + #define INV_ICM42600_INT_STATUS3_TILT_DET_INT BIT(3) 264 264 + #define INV_ICM42600_INT_STATUS3_WAKE_INT BIT(2) 265 265 + #define INV_ICM42600_INT_STATUS3_SLEEP_INT BIT(1) 266 266 + #define INV_ICM42600_INT_STATUS3_TAP_DET_INT BIT(0) 267 267 + 268 268 #define INV_ICM42600_REG_SIGNAL_PATH_RESET 0x004B 269 269 #define INV_ICM42600_SIGNAL_PATH_RESET_DMP_INIT_EN BIT(6) 270 270 #define INV_ICM42600_SIGNAL_PATH_RESET_DMP_MEM_RESET BIT(5) ··· 333 309 #define INV_ICM42600_TMST_CONFIG_TMST_FSYNC_EN BIT(1) 334 310 #define INV_ICM42600_TMST_CONFIG_TMST_EN BIT(0) 335 311 312 312 + #define INV_ICM42600_REG_SMD_CONFIG 0x0057 313 313 + #define INV_ICM42600_SMD_CONFIG_WOM_INT_MODE BIT(3) 314 314 + #define INV_ICM42600_SMD_CONFIG_WOM_MODE BIT(2) 315 315 + #define INV_ICM42600_SMD_CONFIG_SMD_MODE_OFF 0x00 316 316 + #define INV_ICM42600_SMD_CONFIG_SMD_MODE_WOM 0x01 317 317 + #define INV_ICM42600_SMD_CONFIG_SMD_MODE_SHORT 0x02 318 318 + #define INV_ICM42600_SMD_CONFIG_SMD_MODE_LONG 0x03 319 319 + 336 320 #define INV_ICM42600_REG_FIFO_CONFIG1 0x005F 337 321 #define INV_ICM42600_FIFO_CONFIG1_RESUME_PARTIAL_RD BIT(6) 338 322 #define INV_ICM42600_FIFO_CONFIG1_WM_GT_TH BIT(5) ··· 369 337 #define INV_ICM42600_INT_SOURCE0_FIFO_THS_INT1_EN BIT(2) 370 338 #define INV_ICM42600_INT_SOURCE0_FIFO_FULL_INT1_EN BIT(1) 371 339 #define INV_ICM42600_INT_SOURCE0_UI_AGC_RDY_INT1_EN BIT(0) 340 340 + 341 341 + #define INV_ICM42600_REG_INT_SOURCE1 0x0066 342 342 + #define INV_ICM42600_INT_SOURCE1_I3C_ERROR_INT1_EN BIT(6) 343 343 + #define INV_ICM42600_INT_SOURCE1_SMD_INT1_EN BIT(3) 344 344 + #define INV_ICM42600_INT_SOURCE1_WOM_INT1_EN GENMASK(2, 0) 372 345 373 346 #define INV_ICM42600_REG_WHOAMI 0x0075 374 347 #define INV_ICM42600_WHOAMI_ICM42600 0x40 ··· 410 373 #define INV_ICM42600_INTF_CONFIG6_I3C_SDR_EN BIT(0) 411 374 412 375 /* User bank 4 (MSB 0x40) */ 376 376 + #define INV_ICM42600_REG_ACCEL_WOM_X_THR 0x404A 377 377 + #define INV_ICM42600_REG_ACCEL_WOM_Y_THR 0x404B 378 378 + #define INV_ICM42600_REG_ACCEL_WOM_Z_THR 0x404C 379 379 + 413 380 #define INV_ICM42600_REG_INT_SOURCE8 0x404F 414 381 #define INV_ICM42600_INT_SOURCE8_FSYNC_IBI_EN BIT(5) 415 382 #define INV_ICM42600_INT_SOURCE8_PLL_RDY_IBI_EN BIT(4) ··· 451 410 inv_icm42600_get_mount_matrix(const struct iio_dev *indio_dev, 452 411 const struct iio_chan_spec *chan); 453 412 454 454 - uint32_t inv_icm42600_odr_to_period(enum inv_icm42600_odr odr); 413 413 + u32 inv_icm42600_odr_to_period(enum inv_icm42600_odr odr); 455 414 456 415 int inv_icm42600_set_accel_conf(struct inv_icm42600_state *st, 457 416 struct inv_icm42600_sensor_conf *conf, ··· 463 422 464 423 int inv_icm42600_set_temp_conf(struct inv_icm42600_state *st, bool enable, 465 424 unsigned int *sleep_ms); 425 425 + 426 426 + int inv_icm42600_enable_wom(struct inv_icm42600_state *st); 427 427 + int inv_icm42600_disable_wom(struct inv_icm42600_state *st); 466 428 467 429 int inv_icm42600_debugfs_reg(struct iio_dev *indio_dev, unsigned int reg, 468 430 unsigned int writeval, unsigned int *readval); ··· 480 436 struct iio_dev *inv_icm42600_accel_init(struct inv_icm42600_state *st); 481 437 482 438 int inv_icm42600_accel_parse_fifo(struct iio_dev *indio_dev); 439 439 + 440 440 + void inv_icm42600_accel_handle_events(struct iio_dev *indio_dev, 441 441 + unsigned int status2, unsigned int status3, 442 442 + s64 timestamp); 483 443 484 444 #endif

+341 -19

drivers/iio/imu/inv_icm42600/inv_icm42600_accel.c

reviewed

··· 10 10 #include <linux/regmap.h> 11 11 #include <linux/delay.h> 12 12 #include <linux/math64.h> 13 13 + #include <linux/minmax.h> 14 14 + #include <linux/units.h> 13 15 14 16 #include <linux/iio/buffer.h> 15 17 #include <linux/iio/common/inv_sensors_timestamp.h> 18 18 + #include <linux/iio/events.h> 16 19 #include <linux/iio/iio.h> 17 20 #include <linux/iio/kfifo_buf.h> 18 21 ··· 48 45 .endianness = IIO_BE, \ 49 46 }, \ 50 47 .ext_info = _ext_info, \ 48 48 + } 49 49 + 50 50 + #define INV_ICM42600_ACCEL_EVENT_CHAN(_modifier, _events, _events_nb) \ 51 51 + { \ 52 52 + .type = IIO_ACCEL, \ 53 53 + .modified = 1, \ 54 54 + .channel2 = _modifier, \ 55 55 + .event_spec = _events, \ 56 56 + .num_event_specs = _events_nb, \ 57 57 + .scan_index = -1, \ 51 58 } 52 59 53 60 enum inv_icm42600_accel_scan { ··· 95 82 if (idx >= ARRAY_SIZE(inv_icm42600_accel_power_mode_values)) 96 83 return -EINVAL; 97 84 98 98 - if (iio_buffer_enabled(indio_dev)) 99 99 - return -EBUSY; 100 100 - 101 85 power_mode = inv_icm42600_accel_power_mode_values[idx]; 102 86 filter = inv_icm42600_accel_filter_values[idx]; 103 87 104 88 guard(mutex)(&st->lock); 89 89 + 90 90 + /* cannot change if accel sensor is on */ 91 91 + if (st->conf.accel.mode != INV_ICM42600_SENSOR_MODE_OFF) 92 92 + return -EBUSY; 105 93 106 94 /* prevent change if power mode is not supported by the ODR */ 107 95 switch (power_mode) { ··· 174 160 { } 175 161 }; 176 162 163 163 + /* WoM event: rising ROC */ 164 164 + static const struct iio_event_spec inv_icm42600_wom_events[] = { 165 165 + { 166 166 + .type = IIO_EV_TYPE_ROC, 167 167 + .dir = IIO_EV_DIR_RISING, 168 168 + .mask_separate = BIT(IIO_EV_INFO_ENABLE) | 169 169 + BIT(IIO_EV_INFO_VALUE), 170 170 + }, 171 171 + }; 172 172 + 177 173 static const struct iio_chan_spec inv_icm42600_accel_channels[] = { 178 174 INV_ICM42600_ACCEL_CHAN(IIO_MOD_X, INV_ICM42600_ACCEL_SCAN_X, 179 175 inv_icm42600_accel_ext_infos), ··· 193 169 inv_icm42600_accel_ext_infos), 194 170 INV_ICM42600_TEMP_CHAN(INV_ICM42600_ACCEL_SCAN_TEMP), 195 171 IIO_CHAN_SOFT_TIMESTAMP(INV_ICM42600_ACCEL_SCAN_TIMESTAMP), 172 172 + INV_ICM42600_ACCEL_EVENT_CHAN(IIO_MOD_X_OR_Y_OR_Z, inv_icm42600_wom_events, 173 173 + ARRAY_SIZE(inv_icm42600_wom_events)), 196 174 }; 197 175 198 176 /* ··· 203 177 */ 204 178 struct inv_icm42600_accel_buffer { 205 179 struct inv_icm42600_fifo_sensor_data accel; 206 206 - int16_t temp; 180 180 + s16 temp; 207 181 aligned_s64 timestamp; 208 182 }; 209 183 ··· 267 241 268 242 static int inv_icm42600_accel_read_sensor(struct iio_dev *indio_dev, 269 243 struct iio_chan_spec const *chan, 270 270 - int16_t *val) 244 244 + s16 *val) 271 245 { 272 246 struct inv_icm42600_state *st = iio_device_get_drvdata(indio_dev); 273 247 struct inv_icm42600_sensor_state *accel_st = iio_priv(indio_dev); ··· 310 284 if (ret) 311 285 goto exit; 312 286 313 313 - *val = (int16_t)be16_to_cpup(data); 287 287 + *val = (s16)be16_to_cpup(data); 314 288 if (*val == INV_ICM42600_DATA_INVALID) 315 289 ret = -EINVAL; 316 290 exit: ··· 318 292 pm_runtime_mark_last_busy(dev); 319 293 pm_runtime_put_autosuspend(dev); 320 294 return ret; 295 295 + } 296 296 + 297 297 + static unsigned int inv_icm42600_accel_convert_roc_to_wom(u64 roc, 298 298 + int accel_hz, int accel_uhz) 299 299 + { 300 300 + /* 1000/256mg per LSB converted in µm/s² */ 301 301 + const unsigned int convert = (9807U * (MICRO / MILLI)) / 256U; 302 302 + u64 value; 303 303 + u64 freq_uhz; 304 304 + 305 305 + /* return 0 only if roc is 0 */ 306 306 + if (roc == 0) 307 307 + return 0; 308 308 + 309 309 + freq_uhz = (u64)accel_hz * MICRO + (u64)accel_uhz; 310 310 + value = div64_u64(roc * MICRO, freq_uhz * (u64)convert); 311 311 + 312 312 + /* limit value to 8 bits and prevent 0 */ 313 313 + return clamp(value, 1, 255); 314 314 + } 315 315 + 316 316 + static u64 inv_icm42600_accel_convert_wom_to_roc(unsigned int threshold, 317 317 + int accel_hz, int accel_uhz) 318 318 + { 319 319 + /* 1000/256mg per LSB converted in µm/s² */ 320 320 + const unsigned int convert = (9807U * (MICRO / MILLI)) / 256U; 321 321 + u64 value; 322 322 + u64 freq_uhz; 323 323 + 324 324 + value = threshold * convert; 325 325 + freq_uhz = (u64)accel_hz * MICRO + (u64)accel_uhz; 326 326 + 327 327 + /* compute the differential by multiplying by the frequency */ 328 328 + return div_u64(value * freq_uhz, MICRO); 329 329 + } 330 330 + 331 331 + static int inv_icm42600_accel_set_wom_threshold(struct inv_icm42600_state *st, 332 332 + u64 value, 333 333 + int accel_hz, int accel_uhz) 334 334 + { 335 335 + unsigned int threshold; 336 336 + int ret; 337 337 + 338 338 + /* convert roc to wom threshold and convert back to handle clipping */ 339 339 + threshold = inv_icm42600_accel_convert_roc_to_wom(value, accel_hz, accel_uhz); 340 340 + value = inv_icm42600_accel_convert_wom_to_roc(threshold, accel_hz, accel_uhz); 341 341 + 342 342 + dev_dbg(regmap_get_device(st->map), "wom_threshold: 0x%x\n", threshold); 343 343 + 344 344 + /* set accel WoM threshold for the 3 axes */ 345 345 + st->buffer[0] = threshold; 346 346 + st->buffer[1] = threshold; 347 347 + st->buffer[2] = threshold; 348 348 + ret = regmap_bulk_write(st->map, INV_ICM42600_REG_ACCEL_WOM_X_THR, st->buffer, 3); 349 349 + if (ret) 350 350 + return ret; 351 351 + 352 352 + st->apex.wom.value = value; 353 353 + 354 354 + return 0; 355 355 + } 356 356 + 357 357 + static int _inv_icm42600_accel_enable_wom(struct iio_dev *indio_dev) 358 358 + { 359 359 + struct inv_icm42600_state *st = iio_device_get_drvdata(indio_dev); 360 360 + struct inv_icm42600_sensor_state *accel_st = iio_priv(indio_dev); 361 361 + struct inv_icm42600_sensor_conf conf = INV_ICM42600_SENSOR_CONF_INIT; 362 362 + unsigned int sleep_ms = 0; 363 363 + int ret; 364 364 + 365 365 + scoped_guard(mutex, &st->lock) { 366 366 + /* turn on accel sensor */ 367 367 + conf.mode = accel_st->power_mode; 368 368 + conf.filter = accel_st->filter; 369 369 + ret = inv_icm42600_set_accel_conf(st, &conf, &sleep_ms); 370 370 + if (ret) 371 371 + return ret; 372 372 + } 373 373 + 374 374 + if (sleep_ms) 375 375 + msleep(sleep_ms); 376 376 + 377 377 + scoped_guard(mutex, &st->lock) { 378 378 + ret = inv_icm42600_enable_wom(st); 379 379 + if (ret) 380 380 + return ret; 381 381 + st->apex.on++; 382 382 + st->apex.wom.enable = true; 383 383 + } 384 384 + 385 385 + return 0; 386 386 + } 387 387 + 388 388 + static int inv_icm42600_accel_enable_wom(struct iio_dev *indio_dev) 389 389 + { 390 390 + struct inv_icm42600_state *st = iio_device_get_drvdata(indio_dev); 391 391 + struct device *pdev = regmap_get_device(st->map); 392 392 + int ret; 393 393 + 394 394 + ret = pm_runtime_resume_and_get(pdev); 395 395 + if (ret) 396 396 + return ret; 397 397 + 398 398 + ret = _inv_icm42600_accel_enable_wom(indio_dev); 399 399 + if (ret) { 400 400 + pm_runtime_mark_last_busy(pdev); 401 401 + pm_runtime_put_autosuspend(pdev); 402 402 + return ret; 403 403 + } 404 404 + 405 405 + return 0; 406 406 + } 407 407 + 408 408 + static int _inv_icm42600_accel_disable_wom(struct iio_dev *indio_dev) 409 409 + { 410 410 + struct inv_icm42600_state *st = iio_device_get_drvdata(indio_dev); 411 411 + struct inv_icm42600_sensor_conf conf = INV_ICM42600_SENSOR_CONF_INIT; 412 412 + unsigned int sleep_ms = 0; 413 413 + int ret; 414 414 + 415 415 + scoped_guard(mutex, &st->lock) { 416 416 + /* 417 417 + * Consider that turning off WoM is always working to avoid 418 418 + * blocking the chip in on mode and prevent going back to sleep. 419 419 + * If there is an error, the chip will anyway go back to sleep 420 420 + * and the feature will not work anymore. 421 421 + */ 422 422 + st->apex.wom.enable = false; 423 423 + st->apex.on--; 424 424 + ret = inv_icm42600_disable_wom(st); 425 425 + if (ret) 426 426 + return ret; 427 427 + /* turn off accel sensor if not used */ 428 428 + if (!st->apex.on && !iio_buffer_enabled(indio_dev)) { 429 429 + conf.mode = INV_ICM42600_SENSOR_MODE_OFF; 430 430 + ret = inv_icm42600_set_accel_conf(st, &conf, &sleep_ms); 431 431 + if (ret) 432 432 + return ret; 433 433 + } 434 434 + } 435 435 + 436 436 + if (sleep_ms) 437 437 + msleep(sleep_ms); 438 438 + 439 439 + return 0; 440 440 + } 441 441 + 442 442 + static int inv_icm42600_accel_disable_wom(struct iio_dev *indio_dev) 443 443 + { 444 444 + struct inv_icm42600_state *st = iio_device_get_drvdata(indio_dev); 445 445 + struct device *pdev = regmap_get_device(st->map); 446 446 + int ret; 447 447 + 448 448 + ret = _inv_icm42600_accel_disable_wom(indio_dev); 449 449 + 450 450 + pm_runtime_mark_last_busy(pdev); 451 451 + pm_runtime_put_autosuspend(pdev); 452 452 + 453 453 + return ret; 454 454 + } 455 455 + 456 456 + void inv_icm42600_accel_handle_events(struct iio_dev *indio_dev, 457 457 + unsigned int status2, unsigned int status3, 458 458 + s64 timestamp) 459 459 + { 460 460 + struct inv_icm42600_state *st = iio_device_get_drvdata(indio_dev); 461 461 + u64 ev_code; 462 462 + 463 463 + /* handle WoM event */ 464 464 + if (st->apex.wom.enable && (status2 & INV_ICM42600_INT_STATUS2_WOM_INT)) { 465 465 + ev_code = IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X_OR_Y_OR_Z, 466 466 + IIO_EV_TYPE_ROC, IIO_EV_DIR_RISING); 467 467 + iio_push_event(indio_dev, ev_code, timestamp); 468 468 + } 321 469 } 322 470 323 471 /* IIO format int + nano */ ··· 666 466 ret = inv_icm42600_set_accel_conf(st, &conf, NULL); 667 467 if (ret) 668 468 goto out_unlock; 469 469 + /* update wom threshold since roc is dependent on sampling frequency */ 470 470 + ret = inv_icm42600_accel_set_wom_threshold(st, st->apex.wom.value, val, val2); 471 471 + if (ret) 472 472 + goto out_unlock; 669 473 inv_icm42600_buffer_update_fifo_period(st); 670 474 inv_icm42600_buffer_update_watermark(st); 671 475 ··· 696 492 int *val, int *val2) 697 493 { 698 494 struct device *dev = regmap_get_device(st->map); 699 699 - int64_t val64; 700 700 - int32_t bias; 495 495 + s64 val64; 496 496 + s32 bias; 701 497 unsigned int reg; 702 702 - int16_t offset; 703 703 - uint8_t data[2]; 498 498 + s16 offset; 499 499 + u8 data[2]; 704 500 int ret; 705 501 706 502 if (chan->type != IIO_ACCEL) ··· 754 550 * result in micro (1000000) 755 551 * (offset * 5 * 9.806650 * 1000000) / 10000 756 552 */ 757 757 - val64 = (int64_t)offset * 5LL * 9806650LL; 553 553 + val64 = (s64)offset * 5LL * 9806650LL; 758 554 /* for rounding, add + or - divisor (10000) divided by 2 */ 759 555 if (val64 >= 0) 760 556 val64 += 10000LL / 2LL; ··· 772 568 int val, int val2) 773 569 { 774 570 struct device *dev = regmap_get_device(st->map); 775 775 - int64_t val64; 776 776 - int32_t min, max; 571 571 + s64 val64; 572 572 + s32 min, max; 777 573 unsigned int reg, regval; 778 778 - int16_t offset; 574 574 + s16 offset; 779 575 int ret; 780 576 781 577 if (chan->type != IIO_ACCEL) ··· 800 596 inv_icm42600_accel_calibbias[1]; 801 597 max = inv_icm42600_accel_calibbias[4] * 1000000L + 802 598 inv_icm42600_accel_calibbias[5]; 803 803 - val64 = (int64_t)val * 1000000LL + (int64_t)val2; 599 599 + val64 = (s64)val * 1000000LL + (s64)val2; 804 600 if (val64 < min || val64 > max) 805 601 return -EINVAL; 806 602 ··· 875 671 int *val, int *val2, long mask) 876 672 { 877 673 struct inv_icm42600_state *st = iio_device_get_drvdata(indio_dev); 878 878 - int16_t data; 674 674 + s16 data; 879 675 int ret; 880 676 881 677 switch (chan->type) { ··· 1023 819 return ret; 1024 820 } 1025 821 822 822 + static int inv_icm42600_accel_read_event_config(struct iio_dev *indio_dev, 823 823 + const struct iio_chan_spec *chan, 824 824 + enum iio_event_type type, 825 825 + enum iio_event_direction dir) 826 826 + { 827 827 + struct inv_icm42600_state *st = iio_device_get_drvdata(indio_dev); 828 828 + 829 829 + /* handle only WoM (roc rising) event */ 830 830 + if (type != IIO_EV_TYPE_ROC || dir != IIO_EV_DIR_RISING) 831 831 + return -EINVAL; 832 832 + 833 833 + guard(mutex)(&st->lock); 834 834 + 835 835 + return st->apex.wom.enable ? 1 : 0; 836 836 + } 837 837 + 838 838 + static int inv_icm42600_accel_write_event_config(struct iio_dev *indio_dev, 839 839 + const struct iio_chan_spec *chan, 840 840 + enum iio_event_type type, 841 841 + enum iio_event_direction dir, 842 842 + bool state) 843 843 + { 844 844 + struct inv_icm42600_state *st = iio_device_get_drvdata(indio_dev); 845 845 + 846 846 + /* handle only WoM (roc rising) event */ 847 847 + if (type != IIO_EV_TYPE_ROC || dir != IIO_EV_DIR_RISING) 848 848 + return -EINVAL; 849 849 + 850 850 + scoped_guard(mutex, &st->lock) { 851 851 + if (st->apex.wom.enable == state) 852 852 + return 0; 853 853 + } 854 854 + 855 855 + if (state) 856 856 + return inv_icm42600_accel_enable_wom(indio_dev); 857 857 + 858 858 + return inv_icm42600_accel_disable_wom(indio_dev); 859 859 + } 860 860 + 861 861 + static int inv_icm42600_accel_read_event_value(struct iio_dev *indio_dev, 862 862 + const struct iio_chan_spec *chan, 863 863 + enum iio_event_type type, 864 864 + enum iio_event_direction dir, 865 865 + enum iio_event_info info, 866 866 + int *val, int *val2) 867 867 + { 868 868 + struct inv_icm42600_state *st = iio_device_get_drvdata(indio_dev); 869 869 + u32 rem; 870 870 + 871 871 + /* handle only WoM (roc rising) event value */ 872 872 + if (type != IIO_EV_TYPE_ROC || dir != IIO_EV_DIR_RISING) 873 873 + return -EINVAL; 874 874 + 875 875 + guard(mutex)(&st->lock); 876 876 + 877 877 + /* return value in micro */ 878 878 + *val = div_u64_rem(st->apex.wom.value, MICRO, &rem); 879 879 + *val2 = rem; 880 880 + return IIO_VAL_INT_PLUS_MICRO; 881 881 + } 882 882 + 883 883 + static int _inv_icm42600_accel_wom_value(struct inv_icm42600_state *st, 884 884 + int val, int val2) 885 885 + { 886 886 + u64 value; 887 887 + unsigned int accel_hz, accel_uhz; 888 888 + int ret; 889 889 + 890 890 + guard(mutex)(&st->lock); 891 891 + 892 892 + ret = inv_icm42600_accel_read_odr(st, &accel_hz, &accel_uhz); 893 893 + if (ret < 0) 894 894 + return ret; 895 895 + 896 896 + value = (u64)val * MICRO + (u64)val2; 897 897 + 898 898 + return inv_icm42600_accel_set_wom_threshold(st, value, 899 899 + accel_hz, accel_uhz); 900 900 + } 901 901 + 902 902 + static int inv_icm42600_accel_write_event_value(struct iio_dev *indio_dev, 903 903 + const struct iio_chan_spec *chan, 904 904 + enum iio_event_type type, 905 905 + enum iio_event_direction dir, 906 906 + enum iio_event_info info, 907 907 + int val, int val2) 908 908 + { 909 909 + struct inv_icm42600_state *st = iio_device_get_drvdata(indio_dev); 910 910 + struct device *dev = regmap_get_device(st->map); 911 911 + int ret; 912 912 + 913 913 + /* handle only WoM (roc rising) event value */ 914 914 + if (type != IIO_EV_TYPE_ROC || dir != IIO_EV_DIR_RISING) 915 915 + return -EINVAL; 916 916 + 917 917 + if (val < 0 || val2 < 0) 918 918 + return -EINVAL; 919 919 + 920 920 + ret = pm_runtime_resume_and_get(dev); 921 921 + if (ret) 922 922 + return ret; 923 923 + 924 924 + ret = _inv_icm42600_accel_wom_value(st, val, val2); 925 925 + 926 926 + pm_runtime_mark_last_busy(dev); 927 927 + pm_runtime_put_autosuspend(dev); 928 928 + 929 929 + return ret; 930 930 + } 931 931 + 1026 932 static const struct iio_info inv_icm42600_accel_info = { 1027 933 .read_raw = inv_icm42600_accel_read_raw, 1028 934 .read_avail = inv_icm42600_accel_read_avail, ··· 1142 828 .update_scan_mode = inv_icm42600_accel_update_scan_mode, 1143 829 .hwfifo_set_watermark = inv_icm42600_accel_hwfifo_set_watermark, 1144 830 .hwfifo_flush_to_buffer = inv_icm42600_accel_hwfifo_flush, 831 831 + .read_event_config = inv_icm42600_accel_read_event_config, 832 832 + .write_event_config = inv_icm42600_accel_write_event_config, 833 833 + .read_event_value = inv_icm42600_accel_read_event_value, 834 834 + .write_event_value = inv_icm42600_accel_write_event_value, 1145 835 }; 1146 836 1147 837 struct iio_dev *inv_icm42600_accel_init(struct inv_icm42600_state *st) ··· 1206 888 if (ret) 1207 889 return ERR_PTR(ret); 1208 890 891 891 + /* accel events are wakeup capable */ 892 892 + ret = devm_device_init_wakeup(&indio_dev->dev); 893 893 + if (ret) 894 894 + return ERR_PTR(ret); 895 895 + 1209 896 return indio_dev; 1210 897 } 1211 898 ··· 1225 902 const int8_t *temp; 1226 903 unsigned int odr; 1227 904 int64_t ts_val; 1228 1228 - struct inv_icm42600_accel_buffer buffer; 905 905 + /* buffer is copied to userspace, zeroing it to avoid any data leak */ 906 906 + struct inv_icm42600_accel_buffer buffer = { }; 1229 907 1230 908 /* parse all fifo packets */ 1231 909 for (i = 0, no = 0; i < st->fifo.count; i += size, ++no) { ··· 1245 921 inv_sensors_timestamp_apply_odr(ts, st->fifo.period, 1246 922 st->fifo.nb.total, no); 1247 923 1248 1248 - /* buffer is copied to userspace, zeroing it to avoid any data leak */ 1249 1249 - memset(&buffer, 0, sizeof(buffer)); 1250 924 memcpy(&buffer.accel, accel, sizeof(buffer.accel)); 1251 925 /* convert 8 bits FIFO temperature in high resolution format */ 1252 926 buffer.temp = temp ? (*temp * 64) : 0;

+12 -12

drivers/iio/imu/inv_icm42600/inv_icm42600_buffer.c

reviewed

··· 26 26 #define INV_ICM42600_FIFO_HEADER_ODR_GYRO BIT(0) 27 27 28 28 struct inv_icm42600_fifo_1sensor_packet { 29 29 - uint8_t header; 29 29 + u8 header; 30 30 struct inv_icm42600_fifo_sensor_data data; 31 31 - int8_t temp; 31 31 + s8 temp; 32 32 } __packed; 33 33 #define INV_ICM42600_FIFO_1SENSOR_PACKET_SIZE 8 34 34 35 35 struct inv_icm42600_fifo_2sensors_packet { 36 36 - uint8_t header; 36 36 + u8 header; 37 37 struct inv_icm42600_fifo_sensor_data accel; 38 38 struct inv_icm42600_fifo_sensor_data gyro; 39 39 - int8_t temp; 39 39 + s8 temp; 40 40 __be16 timestamp; 41 41 } __packed; 42 42 #define INV_ICM42600_FIFO_2SENSORS_PACKET_SIZE 16 43 43 44 44 ssize_t inv_icm42600_fifo_decode_packet(const void *packet, const void **accel, 45 45 - const void **gyro, const int8_t **temp, 45 45 + const void **gyro, const s8 **temp, 46 46 const void **timestamp, unsigned int *odr) 47 47 { 48 48 const struct inv_icm42600_fifo_1sensor_packet *pack1 = packet; 49 49 const struct inv_icm42600_fifo_2sensors_packet *pack2 = packet; 50 50 - uint8_t header = *((const uint8_t *)packet); 50 50 + u8 header = *((const u8 *)packet); 51 51 52 52 /* FIFO empty */ 53 53 if (header & INV_ICM42600_FIFO_HEADER_MSG) { ··· 100 100 101 101 void inv_icm42600_buffer_update_fifo_period(struct inv_icm42600_state *st) 102 102 { 103 103 - uint32_t period_gyro, period_accel, period; 103 103 + u32 period_gyro, period_accel, period; 104 104 105 105 if (st->fifo.en & INV_ICM42600_SENSOR_GYRO) 106 106 period_gyro = inv_icm42600_odr_to_period(st->conf.gyro.odr); ··· 204 204 { 205 205 size_t packet_size, wm_size; 206 206 unsigned int wm_gyro, wm_accel, watermark; 207 207 - uint32_t period_gyro, period_accel, period; 208 208 - uint32_t latency_gyro, latency_accel, latency; 207 207 + u32 period_gyro, period_accel, period; 208 208 + u32 latency_gyro, latency_accel, latency; 209 209 bool restore; 210 210 __le16 raw_wm; 211 211 int ret; ··· 422 422 conf.mode = INV_ICM42600_SENSOR_MODE_OFF; 423 423 if (sensor == INV_ICM42600_SENSOR_GYRO) 424 424 ret = inv_icm42600_set_gyro_conf(st, &conf, &sleep_sensor); 425 425 - else 425 425 + else if (!st->apex.on) 426 426 ret = inv_icm42600_set_accel_conf(st, &conf, &sleep_sensor); 427 427 if (ret) 428 428 goto out_unlock; ··· 459 459 __be16 *raw_fifo_count; 460 460 ssize_t i, size; 461 461 const void *accel, *gyro, *timestamp; 462 462 - const int8_t *temp; 462 462 + const s8 *temp; 463 463 unsigned int odr; 464 464 int ret; 465 465 ··· 550 550 struct inv_icm42600_sensor_state *gyro_st = iio_priv(st->indio_gyro); 551 551 struct inv_icm42600_sensor_state *accel_st = iio_priv(st->indio_accel); 552 552 struct inv_sensors_timestamp *ts; 553 553 - int64_t gyro_ts, accel_ts; 553 553 + s64 gyro_ts, accel_ts; 554 554 int ret; 555 555 556 556 gyro_ts = iio_get_time_ns(st->indio_gyro);

+5 -5

drivers/iio/imu/inv_icm42600/inv_icm42600_buffer.h

reviewed

··· 28 28 struct inv_icm42600_fifo { 29 29 unsigned int on; 30 30 unsigned int en; 31 31 - uint32_t period; 31 31 + u32 period; 32 32 struct { 33 33 unsigned int gyro; 34 34 unsigned int accel; ··· 41 41 size_t accel; 42 42 size_t total; 43 43 } nb; 44 44 - uint8_t data[2080] __aligned(IIO_DMA_MINALIGN); 44 44 + u8 data[2080] __aligned(IIO_DMA_MINALIGN); 45 45 }; 46 46 47 47 /* FIFO data packet */ ··· 52 52 } __packed; 53 53 #define INV_ICM42600_FIFO_DATA_INVALID -32768 54 54 55 55 - static inline int16_t inv_icm42600_fifo_get_sensor_data(__be16 d) 55 55 + static inline s16 inv_icm42600_fifo_get_sensor_data(__be16 d) 56 56 { 57 57 return be16_to_cpu(d); 58 58 } ··· 60 60 static inline bool 61 61 inv_icm42600_fifo_is_data_valid(const struct inv_icm42600_fifo_sensor_data *s) 62 62 { 63 63 - int16_t x, y, z; 63 63 + s16 x, y, z; 64 64 65 65 x = inv_icm42600_fifo_get_sensor_data(s->x); 66 66 y = inv_icm42600_fifo_get_sensor_data(s->y); ··· 75 75 } 76 76 77 77 ssize_t inv_icm42600_fifo_decode_packet(const void *packet, const void **accel, 78 78 - const void **gyro, const int8_t **temp, 78 78 + const void **gyro, const s8 **temp, 79 79 const void **timestamp, unsigned int *odr); 80 80 81 81 extern const struct iio_buffer_setup_ops inv_icm42600_buffer_ops;

+96 -11

drivers/iio/imu/inv_icm42600/inv_icm42600_core.c

reviewed

··· 83 83 .num_ranges = ARRAY_SIZE(inv_icm42600_regmap_ranges), 84 84 .volatile_table = inv_icm42600_regmap_volatile_accesses, 85 85 .rd_noinc_table = inv_icm42600_regmap_rd_noinc_accesses, 86 86 - .cache_type = REGCACHE_RBTREE, 86 86 + .cache_type = REGCACHE_MAPLE, 87 87 }; 88 88 EXPORT_SYMBOL_NS_GPL(inv_icm42600_regmap_config, "IIO_ICM42600"); 89 89 ··· 97 97 .num_ranges = ARRAY_SIZE(inv_icm42600_regmap_ranges), 98 98 .volatile_table = inv_icm42600_regmap_volatile_accesses, 99 99 .rd_noinc_table = inv_icm42600_regmap_rd_noinc_accesses, 100 100 - .cache_type = REGCACHE_RBTREE, 100 100 + .cache_type = REGCACHE_MAPLE, 101 101 .use_single_write = true, 102 102 }; 103 103 EXPORT_SYMBOL_NS_GPL(inv_icm42600_spi_regmap_config, "IIO_ICM42600"); 104 104 105 105 struct inv_icm42600_hw { 106 106 - uint8_t whoami; 106 106 + u8 whoami; 107 107 const char *name; 108 108 const struct inv_icm42600_conf *conf; 109 109 }; ··· 188 188 return &st->orientation; 189 189 } 190 190 191 191 - uint32_t inv_icm42600_odr_to_period(enum inv_icm42600_odr odr) 191 191 + u32 inv_icm42600_odr_to_period(enum inv_icm42600_odr odr) 192 192 { 193 193 - static uint32_t odr_periods[INV_ICM42600_ODR_NB] = { 193 193 + static u32 odr_periods[INV_ICM42600_ODR_NB] = { 194 194 /* reserved values */ 195 195 0, 0, 0, 196 196 /* 8kHz */ ··· 404 404 sleep_ms); 405 405 } 406 406 407 407 + int inv_icm42600_enable_wom(struct inv_icm42600_state *st) 408 408 + { 409 409 + int ret; 410 410 + 411 411 + /* enable WoM hardware */ 412 412 + ret = regmap_write(st->map, INV_ICM42600_REG_SMD_CONFIG, 413 413 + INV_ICM42600_SMD_CONFIG_SMD_MODE_WOM | 414 414 + INV_ICM42600_SMD_CONFIG_WOM_MODE); 415 415 + if (ret) 416 416 + return ret; 417 417 + 418 418 + /* enable WoM interrupt */ 419 419 + return regmap_set_bits(st->map, INV_ICM42600_REG_INT_SOURCE1, 420 420 + INV_ICM42600_INT_SOURCE1_WOM_INT1_EN); 421 421 + } 422 422 + 423 423 + int inv_icm42600_disable_wom(struct inv_icm42600_state *st) 424 424 + { 425 425 + int ret; 426 426 + 427 427 + /* disable WoM interrupt */ 428 428 + ret = regmap_clear_bits(st->map, INV_ICM42600_REG_INT_SOURCE1, 429 429 + INV_ICM42600_INT_SOURCE1_WOM_INT1_EN); 430 430 + if (ret) 431 431 + return ret; 432 432 + 433 433 + /* disable WoM hardware */ 434 434 + return regmap_write(st->map, INV_ICM42600_REG_SMD_CONFIG, 435 435 + INV_ICM42600_SMD_CONFIG_SMD_MODE_OFF); 436 436 + } 437 437 + 407 438 int inv_icm42600_debugfs_reg(struct iio_dev *indio_dev, unsigned int reg, 408 439 unsigned int writeval, unsigned int *readval) 409 440 { ··· 578 547 int ret; 579 548 580 549 mutex_lock(&st->lock); 550 550 + 551 551 + if (st->apex.on) { 552 552 + unsigned int status2, status3; 553 553 + 554 554 + /* read INT_STATUS2 and INT_STATUS3 in 1 operation */ 555 555 + ret = regmap_bulk_read(st->map, INV_ICM42600_REG_INT_STATUS2, st->buffer, 2); 556 556 + if (ret) 557 557 + goto out_unlock; 558 558 + status2 = st->buffer[0]; 559 559 + status3 = st->buffer[1]; 560 560 + inv_icm42600_accel_handle_events(st->indio_accel, status2, status3, 561 561 + st->timestamp.accel); 562 562 + } 581 563 582 564 ret = regmap_read(st->map, INV_ICM42600_REG_INT_STATUS, &status); 583 565 if (ret) ··· 765 721 mutex_init(&st->lock); 766 722 st->chip = chip; 767 723 st->map = regmap; 724 724 + st->irq = irq; 768 725 769 726 ret = iio_read_mount_matrix(dev, &st->orientation); 770 727 if (ret) { ··· 844 799 static int inv_icm42600_suspend(struct device *dev) 845 800 { 846 801 struct inv_icm42600_state *st = dev_get_drvdata(dev); 802 802 + struct device *accel_dev; 803 803 + bool wakeup; 804 804 + int accel_conf; 847 805 int ret; 848 806 849 807 mutex_lock(&st->lock); ··· 867 819 goto out_unlock; 868 820 } 869 821 822 822 + /* keep chip on and wake-up capable if APEX and wakeup on */ 823 823 + accel_dev = &st->indio_accel->dev; 824 824 + wakeup = st->apex.on && device_may_wakeup(accel_dev); 825 825 + if (wakeup) { 826 826 + /* keep accel on and setup irq for wakeup */ 827 827 + accel_conf = st->conf.accel.mode; 828 828 + enable_irq_wake(st->irq); 829 829 + disable_irq(st->irq); 830 830 + } else { 831 831 + /* disable APEX features and accel if wakeup disabled */ 832 832 + if (st->apex.wom.enable) { 833 833 + ret = inv_icm42600_disable_wom(st); 834 834 + if (ret) 835 835 + goto out_unlock; 836 836 + } 837 837 + accel_conf = INV_ICM42600_SENSOR_MODE_OFF; 838 838 + } 839 839 + 870 840 ret = inv_icm42600_set_pwr_mgmt0(st, INV_ICM42600_SENSOR_MODE_OFF, 871 871 - INV_ICM42600_SENSOR_MODE_OFF, false, 872 872 - NULL); 841 841 + accel_conf, false, NULL); 873 842 if (ret) 874 843 goto out_unlock; 875 844 876 876 - regulator_disable(st->vddio_supply); 845 845 + /* disable vddio regulator if chip is sleeping */ 846 846 + if (!wakeup) 847 847 + regulator_disable(st->vddio_supply); 877 848 878 849 out_unlock: 879 850 mutex_unlock(&st->lock); ··· 908 841 struct inv_icm42600_state *st = dev_get_drvdata(dev); 909 842 struct inv_icm42600_sensor_state *gyro_st = iio_priv(st->indio_gyro); 910 843 struct inv_icm42600_sensor_state *accel_st = iio_priv(st->indio_accel); 844 844 + struct device *accel_dev; 845 845 + bool wakeup; 911 846 int ret; 912 847 913 848 mutex_lock(&st->lock); 914 849 915 915 - ret = inv_icm42600_enable_regulator_vddio(st); 916 916 - if (ret) 917 917 - goto out_unlock; 850 850 + /* check wakeup capability */ 851 851 + accel_dev = &st->indio_accel->dev; 852 852 + wakeup = st->apex.on && device_may_wakeup(accel_dev); 853 853 + /* restore irq state or vddio if cut off */ 854 854 + if (wakeup) { 855 855 + enable_irq(st->irq); 856 856 + disable_irq_wake(st->irq); 857 857 + } else { 858 858 + ret = inv_icm42600_enable_regulator_vddio(st); 859 859 + if (ret) 860 860 + goto out_unlock; 861 861 + } 918 862 919 863 pm_runtime_disable(dev); 920 864 pm_runtime_set_active(dev); ··· 937 859 st->suspended.temp, NULL); 938 860 if (ret) 939 861 goto out_unlock; 862 862 + 863 863 + /* restore APEX features if disabled */ 864 864 + if (!wakeup && st->apex.wom.enable) { 865 865 + ret = inv_icm42600_enable_wom(st); 866 866 + if (ret) 867 867 + goto out_unlock; 868 868 + } 940 869 941 870 /* restore FIFO data streaming */ 942 871 if (st->fifo.on) {

+20 -21

drivers/iio/imu/inv_icm42600/inv_icm42600_gyro.c

reviewed

··· 77 77 */ 78 78 struct inv_icm42600_gyro_buffer { 79 79 struct inv_icm42600_fifo_sensor_data gyro; 80 80 - int16_t temp; 80 80 + s16 temp; 81 81 aligned_s64 timestamp; 82 82 }; 83 83 ··· 139 139 140 140 static int inv_icm42600_gyro_read_sensor(struct inv_icm42600_state *st, 141 141 struct iio_chan_spec const *chan, 142 142 - int16_t *val) 142 142 + s16 *val) 143 143 { 144 144 struct device *dev = regmap_get_device(st->map); 145 145 struct inv_icm42600_sensor_conf conf = INV_ICM42600_SENSOR_CONF_INIT; ··· 179 179 if (ret) 180 180 goto exit; 181 181 182 182 - *val = (int16_t)be16_to_cpup(data); 182 182 + *val = (s16)be16_to_cpup(data); 183 183 if (*val == INV_ICM42600_DATA_INVALID) 184 184 ret = -EINVAL; 185 185 exit: ··· 399 399 int *val, int *val2) 400 400 { 401 401 struct device *dev = regmap_get_device(st->map); 402 402 - int64_t val64; 403 403 - int32_t bias; 402 402 + s64 val64; 403 403 + s32 bias; 404 404 unsigned int reg; 405 405 - int16_t offset; 406 406 - uint8_t data[2]; 405 405 + s16 offset; 406 406 + u8 data[2]; 407 407 int ret; 408 408 409 409 if (chan->type != IIO_ANGL_VEL) ··· 457 457 * result in nano (1000000000) 458 458 * (offset * 64 * Pi * 1000000000) / (2048 * 180) 459 459 */ 460 460 - val64 = (int64_t)offset * 64LL * 3141592653LL; 460 460 + val64 = (s64)offset * 64LL * 3141592653LL; 461 461 /* for rounding, add + or - divisor (2048 * 180) divided by 2 */ 462 462 if (val64 >= 0) 463 463 val64 += 2048 * 180 / 2; ··· 475 475 int val, int val2) 476 476 { 477 477 struct device *dev = regmap_get_device(st->map); 478 478 - int64_t val64, min, max; 478 478 + s64 val64, min, max; 479 479 unsigned int reg, regval; 480 480 - int16_t offset; 480 480 + s16 offset; 481 481 int ret; 482 482 483 483 if (chan->type != IIO_ANGL_VEL) ··· 498 498 } 499 499 500 500 /* inv_icm42600_gyro_calibbias: min - step - max in nano */ 501 501 - min = (int64_t)inv_icm42600_gyro_calibbias[0] * 1000000000LL + 502 502 - (int64_t)inv_icm42600_gyro_calibbias[1]; 503 503 - max = (int64_t)inv_icm42600_gyro_calibbias[4] * 1000000000LL + 504 504 - (int64_t)inv_icm42600_gyro_calibbias[5]; 505 505 - val64 = (int64_t)val * 1000000000LL + (int64_t)val2; 501 501 + min = (s64)inv_icm42600_gyro_calibbias[0] * 1000000000LL + 502 502 + (s64)inv_icm42600_gyro_calibbias[1]; 503 503 + max = (s64)inv_icm42600_gyro_calibbias[4] * 1000000000LL + 504 504 + (s64)inv_icm42600_gyro_calibbias[5]; 505 505 + val64 = (s64)val * 1000000000LL + (s64)val2; 506 506 if (val64 < min || val64 > max) 507 507 return -EINVAL; 508 508 ··· 577 577 int *val, int *val2, long mask) 578 578 { 579 579 struct inv_icm42600_state *st = iio_device_get_drvdata(indio_dev); 580 580 - int16_t data; 580 580 + s16 data; 581 581 int ret; 582 582 583 583 switch (chan->type) { ··· 803 803 ssize_t i, size; 804 804 unsigned int no; 805 805 const void *accel, *gyro, *timestamp; 806 806 - const int8_t *temp; 806 806 + const s8 *temp; 807 807 unsigned int odr; 808 808 - int64_t ts_val; 809 809 - struct inv_icm42600_gyro_buffer buffer; 808 808 + s64 ts_val; 809 809 + /* buffer is copied to userspace, zeroing it to avoid any data leak */ 810 810 + struct inv_icm42600_gyro_buffer buffer = { }; 810 811 811 812 /* parse all fifo packets */ 812 813 for (i = 0, no = 0; i < st->fifo.count; i += size, ++no) { ··· 826 825 inv_sensors_timestamp_apply_odr(ts, st->fifo.period, 827 826 st->fifo.nb.total, no); 828 827 829 829 - /* buffer is copied to userspace, zeroing it to avoid any data leak */ 830 830 - memset(&buffer, 0, sizeof(buffer)); 831 828 memcpy(&buffer.gyro, gyro, sizeof(buffer.gyro)); 832 829 /* convert 8 bits FIFO temperature in high resolution format */ 833 830 buffer.temp = temp ? (*temp * 64) : 0;

+3 -3

drivers/iio/imu/inv_icm42600/inv_icm42600_temp.c

reviewed

··· 13 13 #include "inv_icm42600.h" 14 14 #include "inv_icm42600_temp.h" 15 15 16 16 - static int inv_icm42600_temp_read(struct inv_icm42600_state *st, int16_t *temp) 16 16 + static int inv_icm42600_temp_read(struct inv_icm42600_state *st, s16 *temp) 17 17 { 18 18 struct device *dev = regmap_get_device(st->map); 19 19 __be16 *raw; ··· 31 31 if (ret) 32 32 goto exit; 33 33 34 34 - *temp = (int16_t)be16_to_cpup(raw); 34 34 + *temp = (s16)be16_to_cpup(raw); 35 35 if (*temp == INV_ICM42600_DATA_INVALID) 36 36 ret = -EINVAL; 37 37 ··· 48 48 int *val, int *val2, long mask) 49 49 { 50 50 struct inv_icm42600_state *st = iio_device_get_drvdata(indio_dev); 51 51 - int16_t temp; 51 51 + s16 temp; 52 52 int ret; 53 53 54 54 if (chan->type != IIO_TEMP)

+1 -3

drivers/iio/imu/inv_mpu6050/inv_mpu_acpi.c

reviewed

··· 130 130 131 131 st->mux_client = NULL; 132 132 if (adev) { 133 133 - struct i2c_board_info info; 133 133 + struct i2c_board_info info = { }; 134 134 struct i2c_client *mux_client; 135 135 int ret = -1; 136 136 - 137 137 - memset(&info, 0, sizeof(info)); 138 136 139 137 dmi_check_system(inv_mpu_dev_list); 140 138 switch (matched_product_name) {

+20 -36

drivers/iio/imu/inv_mpu6050/inv_mpu_aux.c

reviewed

··· 14 14 /* 15 15 * i2c master auxiliary bus transfer function. 16 16 * Requires the i2c operations to be correctly setup before. 17 17 + * Disables SLV0 and checks for NACK status internally. 18 18 + * Assumes that only SLV0 is used for transfers. 17 19 */ 18 20 static int inv_mpu_i2c_master_xfer(const struct inv_mpu6050_state *st) 19 21 { ··· 25 23 uint8_t d; 26 24 unsigned int user_ctrl; 27 25 int ret; 26 26 + unsigned int status; 28 27 29 28 /* set sample rate */ 30 29 d = INV_MPU6050_FIFO_RATE_TO_DIVIDER(freq); ··· 54 51 if (ret) 55 52 goto error_restore_rate; 56 53 54 54 + /* disable i2c slave */ 55 55 + ret = regmap_write(st->map, INV_MPU6050_REG_I2C_SLV_CTRL(0), 0); 56 56 + if (ret) 57 57 + goto error_disable_i2c; 58 58 + 59 59 + /* check i2c status */ 60 60 + ret = regmap_read(st->map, INV_MPU6050_REG_I2C_MST_STATUS, &status); 61 61 + if (ret) 62 62 + return ret; 63 63 + 64 64 + if (status & INV_MPU6050_BIT_I2C_SLV0_NACK) 65 65 + return -EIO; 66 66 + 57 67 return 0; 58 68 59 69 error_stop_i2c: 60 70 regmap_write(st->map, st->reg->user_ctrl, st->chip_config.user_ctrl); 61 71 error_restore_rate: 62 72 regmap_write(st->map, st->reg->sample_rate_div, st->chip_config.divider); 73 73 + error_disable_i2c: 74 74 + regmap_write(st->map, INV_MPU6050_REG_I2C_SLV_CTRL(0), 0); 63 75 return ret; 64 76 } 65 77 ··· 135 117 int inv_mpu_aux_read(const struct inv_mpu6050_state *st, uint8_t addr, 136 118 uint8_t reg, uint8_t *val, size_t size) 137 119 { 138 138 - unsigned int status; 139 120 int ret; 140 121 141 122 if (size > 0x0F) ··· 153 136 if (ret) 154 137 return ret; 155 138 156 156 - /* do i2c xfer */ 139 139 + /* do i2c xfer, disable i2c slave and check status*/ 157 140 ret = inv_mpu_i2c_master_xfer(st); 158 141 if (ret) 159 159 - goto error_disable_i2c; 160 160 - 161 161 - /* disable i2c slave */ 162 162 - ret = regmap_write(st->map, INV_MPU6050_REG_I2C_SLV_CTRL(0), 0); 163 163 - if (ret) 164 164 - goto error_disable_i2c; 165 165 - 166 166 - /* check i2c status */ 167 167 - ret = regmap_read(st->map, INV_MPU6050_REG_I2C_MST_STATUS, &status); 168 168 - if (ret) 169 142 return ret; 170 170 - if (status & INV_MPU6050_BIT_I2C_SLV0_NACK) 171 171 - return -EIO; 172 143 173 144 /* read data in registers */ 174 145 return regmap_bulk_read(st->map, INV_MPU6050_REG_EXT_SENS_DATA, 175 146 val, size); 176 176 - 177 177 - error_disable_i2c: 178 178 - regmap_write(st->map, INV_MPU6050_REG_I2C_SLV_CTRL(0), 0); 179 179 - return ret; 180 147 } 181 148 182 149 /** ··· 175 174 int inv_mpu_aux_write(const struct inv_mpu6050_state *st, uint8_t addr, 176 175 uint8_t reg, uint8_t val) 177 176 { 178 178 - unsigned int status; 179 177 int ret; 180 178 181 179 /* setup i2c SLV0 control: i2c addr, register, value, enable + size */ ··· 192 192 if (ret) 193 193 return ret; 194 194 195 195 - /* do i2c xfer */ 195 195 + /* do i2c xfer, disable i2c slave and check status*/ 196 196 ret = inv_mpu_i2c_master_xfer(st); 197 197 if (ret) 198 198 - goto error_disable_i2c; 199 199 - 200 200 - /* disable i2c slave */ 201 201 - ret = regmap_write(st->map, INV_MPU6050_REG_I2C_SLV_CTRL(0), 0); 202 202 - if (ret) 203 203 - goto error_disable_i2c; 204 204 - 205 205 - /* check i2c status */ 206 206 - ret = regmap_read(st->map, INV_MPU6050_REG_I2C_MST_STATUS, &status); 207 207 - if (ret) 208 198 return ret; 209 209 - if (status & INV_MPU6050_BIT_I2C_SLV0_NACK) 210 210 - return -EIO; 211 199 212 200 return 0; 213 213 - 214 214 - error_disable_i2c: 215 215 - regmap_write(st->map, INV_MPU6050_REG_I2C_SLV_CTRL(0), 0); 216 216 - return ret; 217 201 }

+2 -3

drivers/iio/imu/inv_mpu6050/inv_mpu_core.c

reviewed

··· 1382 1382 fifo_rate = INV_MPU6050_DIVIDER_TO_FIFO_RATE(st->chip_config.divider); 1383 1383 mutex_unlock(&st->lock); 1384 1384 1385 1385 - return scnprintf(buf, PAGE_SIZE, "%u\n", fifo_rate); 1385 1385 + return sysfs_emit(buf, "%u\n", fifo_rate); 1386 1386 } 1387 1387 1388 1388 /* ··· 1409 1409 case ATTR_ACCL_MATRIX: 1410 1410 m = st->plat_data.orientation; 1411 1411 1412 1412 - return scnprintf(buf, PAGE_SIZE, 1413 1413 - "%d, %d, %d; %d, %d, %d; %d, %d, %d\n", 1412 1412 + return sysfs_emit(buf, "%d, %d, %d; %d, %d, %d; %d, %d, %d\n", 1414 1413 m[0], m[1], m[2], m[3], m[4], m[5], m[6], m[7], m[8]); 1415 1414 default: 1416 1415 return -EINVAL;

+2 -4

drivers/iio/imu/inv_mpu6050/inv_mpu_ring.c

reviewed

··· 50 50 u16 fifo_count; 51 51 u32 fifo_period; 52 52 s64 timestamp; 53 53 - u8 data[INV_MPU6050_OUTPUT_DATA_SIZE] __aligned(8); 53 53 + /* clear internal data buffer for avoiding kernel data leak */ 54 54 + u8 data[INV_MPU6050_OUTPUT_DATA_SIZE] __aligned(8) = { }; 54 55 size_t i, nb; 55 56 56 57 mutex_lock(&st->lock); ··· 103 102 fifo_period = NSEC_PER_SEC / INV_MPU6050_DIVIDER_TO_FIFO_RATE(st->chip_config.divider); 104 103 inv_sensors_timestamp_interrupt(&st->timestamp, 1, pf->timestamp); 105 104 inv_sensors_timestamp_apply_odr(&st->timestamp, fifo_period, 1, 0); 106 106 - 107 107 - /* clear internal data buffer for avoiding kernel data leak */ 108 108 - memset(data, 0, sizeof(data)); 109 105 110 106 /* read all data once and process every samples */ 111 107 result = regmap_noinc_read(st->map, st->reg->fifo_r_w, st->data, fifo_count);

+2 -5

drivers/iio/imu/kmx61.c

reviewed

··· 22 22 #include <linux/iio/triggered_buffer.h> 23 23 #include <linux/iio/trigger_consumer.h> 24 24 25 25 - #define KMX61_DRV_NAME "kmx61" 26 26 - #define KMX61_IRQ_NAME "kmx61_event" 27 27 - 28 25 #define KMX61_REG_WHO_AM_I 0x00 29 26 #define KMX61_REG_INS1 0x01 30 27 #define KMX61_REG_INS2 0x02 ··· 1309 1312 kmx61_data_rdy_trig_poll, 1310 1313 kmx61_event_handler, 1311 1314 IRQF_TRIGGER_RISING, 1312 1312 - KMX61_IRQ_NAME, 1315 1315 + "kmx61_event", 1313 1316 data); 1314 1317 if (ret) 1315 1318 goto err_chip_uninit; ··· 1491 1494 1492 1495 static struct i2c_driver kmx61_driver = { 1493 1496 .driver = { 1494 1494 - .name = KMX61_DRV_NAME, 1497 1497 + .name = "kmx61", 1495 1498 .pm = pm_ptr(&kmx61_pm_ops), 1496 1499 }, 1497 1500 .probe = kmx61_probe,

+60 -1

drivers/iio/industrialio-backend.c

reviewed

··· 720 720 * 0 on success, negative error number on failure. 721 721 */ 722 722 int iio_backend_oversampling_ratio_set(struct iio_backend *back, 723 723 + unsigned int chan, 723 724 unsigned int ratio) 724 725 { 725 725 - return iio_backend_op_call(back, oversampling_ratio_set, ratio); 726 726 + return iio_backend_op_call(back, oversampling_ratio_set, chan, ratio); 726 727 } 727 728 EXPORT_SYMBOL_NS_GPL(iio_backend_oversampling_ratio_set, "IIO_BACKEND"); 728 729 ··· 808 807 809 808 return 0; 810 809 } 810 810 + 811 811 + /** 812 812 + * iio_backend_filter_type_set - Set filter type 813 813 + * @back: Backend device 814 814 + * @type: Filter type. 815 815 + * 816 816 + * RETURNS: 817 817 + * 0 on success, negative error number on failure. 818 818 + */ 819 819 + int iio_backend_filter_type_set(struct iio_backend *back, 820 820 + enum iio_backend_filter_type type) 821 821 + { 822 822 + if (type >= IIO_BACKEND_FILTER_TYPE_MAX) 823 823 + return -EINVAL; 824 824 + 825 825 + return iio_backend_op_call(back, filter_type_set, type); 826 826 + } 827 827 + EXPORT_SYMBOL_NS_GPL(iio_backend_filter_type_set, "IIO_BACKEND"); 828 828 + 829 829 + /** 830 830 + * iio_backend_interface_data_align - Perform the data alignment process. 831 831 + * @back: Backend device 832 832 + * @timeout_us: Timeout value in us. 833 833 + * 834 834 + * When activated, it initates a proccess that aligns the sample's most 835 835 + * significant bit (MSB) based solely on the captured data, without 836 836 + * considering any other external signals. 837 837 + * 838 838 + * The timeout_us value must be greater than 0. 839 839 + * 840 840 + * RETURNS: 841 841 + * 0 on success, negative error number on failure. 842 842 + */ 843 843 + int iio_backend_interface_data_align(struct iio_backend *back, u32 timeout_us) 844 844 + { 845 845 + if (!timeout_us) 846 846 + return -EINVAL; 847 847 + 848 848 + return iio_backend_op_call(back, interface_data_align, timeout_us); 849 849 + } 850 850 + EXPORT_SYMBOL_NS_GPL(iio_backend_interface_data_align, "IIO_BACKEND"); 851 851 + 852 852 + /** 853 853 + * iio_backend_num_lanes_set - Number of lanes enabled. 854 854 + * @back: Backend device 855 855 + * @num_lanes: Number of lanes. 856 856 + * 857 857 + * RETURNS: 858 858 + * 0 on success, negative error number on failure. 859 859 + */ 860 860 + int iio_backend_num_lanes_set(struct iio_backend *back, unsigned int num_lanes) 861 861 + { 862 862 + if (!num_lanes) 863 863 + return -EINVAL; 864 864 + 865 865 + return iio_backend_op_call(back, num_lanes_set, num_lanes); 866 866 + } 867 867 + EXPORT_SYMBOL_NS_GPL(iio_backend_num_lanes_set, "IIO_BACKEND"); 811 868 812 869 /** 813 870 * iio_backend_ddr_enable - Enable interface DDR (Double Data Rate) mode

+1

drivers/iio/industrialio-core.c

reviewed

··· 188 188 [IIO_CHAN_INFO_CALIBAMBIENT] = "calibambient", 189 189 [IIO_CHAN_INFO_ZEROPOINT] = "zeropoint", 190 190 [IIO_CHAN_INFO_TROUGH] = "trough_raw", 191 191 + [IIO_CHAN_INFO_CONVDELAY] = "convdelay", 191 192 }; 192 193 /** 193 194 * iio_device_id() - query the unique ID for the device

+1 -2

drivers/iio/light/adux1020.c

reviewed

··· 23 23 #include <linux/iio/sysfs.h> 24 24 #include <linux/iio/events.h> 25 25 26 26 - #define ADUX1020_REGMAP_NAME "adux1020_regmap" 27 26 #define ADUX1020_DRV_NAME "adux1020" 28 27 29 28 /* System registers */ ··· 113 114 }; 114 115 115 116 static const struct regmap_config adux1020_regmap_config = { 116 116 - .name = ADUX1020_REGMAP_NAME, 117 117 + .name = "adux1020_regmap", 117 118 .reg_bits = 8, 118 119 .val_bits = 16, 119 120 .max_register = 0x6F,

+1 -3

drivers/iio/light/apds9160.c

reviewed

··· 25 25 26 26 #include <linux/unaligned.h> 27 27 28 28 - #define APDS9160_REGMAP_NAME "apds9160_regmap" 29 29 - 30 28 /* Main control register */ 31 29 #define APDS9160_REG_CTRL 0x00 32 30 #define APDS9160_CTRL_SWRESET BIT(4) /* 1: Activate reset */ ··· 159 161 }; 160 162 161 163 static const struct regmap_config apds9160_regmap_config = { 162 162 - .name = APDS9160_REGMAP_NAME, 164 164 + .name = "apds9160_regmap", 163 165 .reg_bits = 8, 164 166 .val_bits = 8, 165 167 .use_single_read = true,

+1 -2

drivers/iio/light/apds9300.c

reviewed

··· 17 17 #include <linux/iio/events.h> 18 18 19 19 #define APDS9300_DRV_NAME "apds9300" 20 20 - #define APDS9300_IRQ_NAME "apds9300_event" 21 20 22 21 /* Command register bits */ 23 22 #define APDS9300_CMD BIT(7) /* Select command register. Must write as 1 */ ··· 431 432 ret = devm_request_threaded_irq(&client->dev, client->irq, 432 433 NULL, apds9300_interrupt_handler, 433 434 IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 434 434 - APDS9300_IRQ_NAME, indio_dev); 435 435 + "apds9300_event", indio_dev); 435 436 if (ret) { 436 437 dev_err(&client->dev, "irq request error %d\n", -ret); 437 438 goto err;

+20 -16

drivers/iio/light/apds9306.c

reviewed

··· 744 744 return regmap_field_write(rf->int_persist_val, val); 745 745 } 746 746 747 747 + static int apds9306_get_thresh_reg(int dir) 748 748 + { 749 749 + if (dir == IIO_EV_DIR_RISING) 750 750 + return APDS9306_ALS_THRES_UP_0_REG; 751 751 + else if (dir == IIO_EV_DIR_FALLING) 752 752 + return APDS9306_ALS_THRES_LOW_0_REG; 753 753 + else 754 754 + return -EINVAL; 755 755 + } 756 756 + 747 757 static int apds9306_event_thresh_get(struct apds9306_data *data, int dir, 748 758 int *val) 749 759 { 750 750 - int var, ret; 760 760 + int reg, ret; 751 761 u8 buff[3]; 752 762 753 753 - if (dir == IIO_EV_DIR_RISING) 754 754 - var = APDS9306_ALS_THRES_UP_0_REG; 755 755 - else if (dir == IIO_EV_DIR_FALLING) 756 756 - var = APDS9306_ALS_THRES_LOW_0_REG; 757 757 - else 758 758 - return -EINVAL; 763 763 + reg = apds9306_get_thresh_reg(dir); 764 764 + if (reg < 0) 765 765 + return reg; 759 766 760 760 - ret = regmap_bulk_read(data->regmap, var, buff, sizeof(buff)); 767 767 + ret = regmap_bulk_read(data->regmap, reg, buff, sizeof(buff)); 761 768 if (ret) 762 769 return ret; 763 770 ··· 776 769 static int apds9306_event_thresh_set(struct apds9306_data *data, int dir, 777 770 int val) 778 771 { 779 779 - int var; 772 772 + int reg; 780 773 u8 buff[3]; 781 774 782 782 - if (dir == IIO_EV_DIR_RISING) 783 783 - var = APDS9306_ALS_THRES_UP_0_REG; 784 784 - else if (dir == IIO_EV_DIR_FALLING) 785 785 - var = APDS9306_ALS_THRES_LOW_0_REG; 786 786 - else 787 787 - return -EINVAL; 775 775 + reg = apds9306_get_thresh_reg(dir); 776 776 + if (reg < 0) 777 777 + return reg; 788 778 789 779 if (!in_range(val, 0, APDS9306_ALS_THRES_VAL_MAX)) 790 780 return -EINVAL; 791 781 792 782 put_unaligned_le24(val, buff); 793 783 794 794 - return regmap_bulk_write(data->regmap, var, buff, sizeof(buff)); 784 784 + return regmap_bulk_write(data->regmap, reg, buff, sizeof(buff)); 795 785 } 796 786 797 787 static int apds9306_event_thresh_adaptive_get(struct apds9306_data *data, int *val)

+1 -2

drivers/iio/light/apds9960.c

reviewed

··· 25 25 #include <linux/iio/kfifo_buf.h> 26 26 #include <linux/iio/sysfs.h> 27 27 28 28 - #define APDS9960_REGMAP_NAME "apds9960_regmap" 29 28 #define APDS9960_DRV_NAME "apds9960" 30 29 31 30 #define APDS9960_REG_RAM_START 0x00 ··· 220 221 }; 221 222 222 223 static const struct regmap_config apds9960_regmap_config = { 223 223 - .name = APDS9960_REGMAP_NAME, 224 224 + .name = "apds9960_regmap", 224 225 .reg_bits = 8, 225 226 .val_bits = 8, 226 227 .use_single_read = true,

+1 -3

drivers/iio/light/bh1745.c

reviewed

··· 740 740 struct { 741 741 u16 chans[4]; 742 742 aligned_s64 timestamp; 743 743 - } scan; 743 743 + } scan = { }; 744 744 u16 value; 745 745 int ret; 746 746 int i; 747 747 int j = 0; 748 748 - 749 749 - memset(&scan, 0, sizeof(scan)); 750 748 751 749 iio_for_each_active_channel(indio_dev, i) { 752 750 ret = regmap_bulk_read(data->regmap, BH1745_RED_LSB + 2 * i,

+8 -10

drivers/iio/light/cm3232.c

reviewed

··· 54 54 struct cm3232_als_info { 55 55 u8 regs_cmd_default; 56 56 u8 hw_id; 57 57 - int calibscale; 58 57 int mlux_per_bit; 59 58 int mlux_per_bit_base_it; 60 59 }; 61 60 62 62 - static struct cm3232_als_info cm3232_als_info_default = { 61 61 + static const struct cm3232_als_info cm3232_als_info_default = { 63 62 .regs_cmd_default = CM3232_CMD_DEFAULT, 64 63 .hw_id = CM3232_HW_ID, 65 65 - .calibscale = CM3232_CALIBSCALE_DEFAULT, 66 64 .mlux_per_bit = CM3232_MLUX_PER_BIT_DEFAULT, 67 65 .mlux_per_bit_base_it = CM3232_MLUX_PER_BIT_BASE_IT, 68 66 }; 69 67 70 68 struct cm3232_chip { 71 69 struct i2c_client *client; 72 72 - struct cm3232_als_info *als_info; 70 70 + const struct cm3232_als_info *als_info; 71 71 + int calibscale; 73 72 u8 regs_cmd; 74 73 u16 regs_als; 75 74 }; ··· 198 199 static int cm3232_get_lux(struct cm3232_chip *chip) 199 200 { 200 201 struct i2c_client *client = chip->client; 201 201 - struct cm3232_als_info *als_info = chip->als_info; 202 202 + const struct cm3232_als_info *als_info = chip->als_info; 202 203 int ret; 203 204 int val, val2; 204 205 int als_it; ··· 221 222 222 223 chip->regs_als = (u16)ret; 223 224 lux *= chip->regs_als; 224 224 - lux *= als_info->calibscale; 225 225 + lux *= chip->calibscale; 225 226 lux = div_u64(lux, CM3232_CALIBSCALE_RESOLUTION); 226 227 lux = div_u64(lux, CM3232_MLUX_PER_LUX); 227 228 ··· 236 237 int *val, int *val2, long mask) 237 238 { 238 239 struct cm3232_chip *chip = iio_priv(indio_dev); 239 239 - struct cm3232_als_info *als_info = chip->als_info; 240 240 int ret; 241 241 242 242 switch (mask) { ··· 246 248 *val = ret; 247 249 return IIO_VAL_INT; 248 250 case IIO_CHAN_INFO_CALIBSCALE: 249 249 - *val = als_info->calibscale; 251 251 + *val = chip->calibscale; 250 252 return IIO_VAL_INT; 251 253 case IIO_CHAN_INFO_INT_TIME: 252 254 return cm3232_read_als_it(chip, val, val2); ··· 260 262 int val, int val2, long mask) 261 263 { 262 264 struct cm3232_chip *chip = iio_priv(indio_dev); 263 263 - struct cm3232_als_info *als_info = chip->als_info; 264 265 265 266 switch (mask) { 266 267 case IIO_CHAN_INFO_CALIBSCALE: 267 267 - als_info->calibscale = val; 268 268 + chip->calibscale = val; 268 269 return 0; 269 270 case IIO_CHAN_INFO_INT_TIME: 270 271 return cm3232_write_als_it(chip, val, val2); ··· 336 339 chip = iio_priv(indio_dev); 337 340 i2c_set_clientdata(client, indio_dev); 338 341 chip->client = client; 342 342 + chip->calibscale = CM3232_CALIBSCALE_DEFAULT; 339 343 340 344 indio_dev->channels = cm3232_channels; 341 345 indio_dev->num_channels = ARRAY_SIZE(cm3232_channels);

+1 -1

drivers/iio/light/isl29028.c

reviewed

··· 562 562 .volatile_reg = isl29028_is_volatile_reg, 563 563 .max_register = ISL29028_NUM_REGS - 1, 564 564 .num_reg_defaults_raw = ISL29028_NUM_REGS, 565 565 - .cache_type = REGCACHE_RBTREE, 565 565 + .cache_type = REGCACHE_MAPLE, 566 566 }; 567 567 568 568 static int isl29028_probe(struct i2c_client *client)

+1 -1

drivers/iio/light/isl76682.c

reviewed

··· 59 59 u32 ir; 60 60 }; 61 61 62 62 - static struct isl76682_range isl76682_range_table[] = { 62 62 + static const struct isl76682_range isl76682_range_table[] = { 63 63 { ISL76682_COMMAND_RANGE_LUX_1K, 15000, 10500 }, 64 64 { ISL76682_COMMAND_RANGE_LUX_4K, 60000, 42000 }, 65 65 { ISL76682_COMMAND_RANGE_LUX_16K, 240000, 168000 },

+1 -2

drivers/iio/light/jsa1212.c

reviewed

··· 106 106 #define JSA1212_PXS_DELAY_MS 100 107 107 108 108 #define JSA1212_DRIVER_NAME "jsa1212" 109 109 - #define JSA1212_REGMAP_NAME "jsa1212_regmap" 110 109 111 110 enum jsa1212_op_mode { 112 111 JSA1212_OPMODE_ALS_EN, ··· 299 300 } 300 301 301 302 static const struct regmap_config jsa1212_regmap_config = { 302 302 - .name = JSA1212_REGMAP_NAME, 303 303 + .name = "jsa1212_regmap", 303 304 .reg_bits = 8, 304 305 .val_bits = 8, 305 306 .max_register = JSA1212_MAX_REG,

+4 -10

drivers/iio/light/ltr501.c

reviewed

··· 24 24 #include <linux/iio/buffer.h> 25 25 #include <linux/iio/triggered_buffer.h> 26 26 27 27 - #define LTR501_DRV_NAME "ltr501" 28 28 - 29 27 #define LTR501_ALS_CONTR 0x80 /* ALS operation mode, SW reset */ 30 28 #define LTR501_PS_CONTR 0x81 /* PS operation mode */ 31 29 #define LTR501_PS_MEAS_RATE 0x84 /* measurement rate*/ ··· 62 64 63 65 #define LTR501_ALS_DEF_PERIOD 500000 64 66 #define LTR501_PS_DEF_PERIOD 100000 65 65 - 66 66 - #define LTR501_REGMAP_NAME "ltr501_regmap" 67 67 68 68 #define LTR501_LUX_CONV(vis_coeff, vis_data, ir_coeff, ir_data) \ 69 69 ((vis_coeff * vis_data) - (ir_coeff * ir_data)) ··· 1279 1283 struct { 1280 1284 u16 channels[3]; 1281 1285 aligned_s64 ts; 1282 1282 - } scan; 1286 1286 + } scan = { }; 1283 1287 __le16 als_buf[2]; 1284 1288 u8 mask = 0; 1285 1289 int j = 0; 1286 1290 int ret, psdata; 1287 1287 - 1288 1288 - memset(&scan, 0, sizeof(scan)); 1289 1291 1290 1292 /* figure out which data needs to be ready */ 1291 1293 if (test_bit(0, indio_dev->active_scan_mask) || ··· 1398 1404 } 1399 1405 1400 1406 static const struct regmap_config ltr501_regmap_config = { 1401 1401 - .name = LTR501_REGMAP_NAME, 1407 1407 + .name = "ltr501_regmap", 1402 1408 .reg_bits = 8, 1403 1409 .val_bits = 8, 1404 1410 .max_register = LTR501_MAX_REG, 1405 1405 - .cache_type = REGCACHE_RBTREE, 1411 1411 + .cache_type = REGCACHE_MAPLE, 1406 1412 .volatile_reg = ltr501_is_volatile_reg, 1407 1413 }; 1408 1414 ··· 1620 1626 1621 1627 static struct i2c_driver ltr501_driver = { 1622 1628 .driver = { 1623 1623 - .name = LTR501_DRV_NAME, 1629 1629 + .name = "ltr501", 1624 1630 .of_match_table = ltr501_of_match, 1625 1631 .pm = pm_sleep_ptr(&ltr501_pm_ops), 1626 1632 .acpi_match_table = ltr_acpi_match,

+2 -4

drivers/iio/light/opt4060.c

reviewed

··· 1063 1063 .name = "opt4060", 1064 1064 .reg_bits = 8, 1065 1065 .val_bits = 16, 1066 1066 - .cache_type = REGCACHE_RBTREE, 1066 1066 + .cache_type = REGCACHE_MAPLE, 1067 1067 .max_register = OPT4060_DEVICE_ID, 1068 1068 .readable_reg = opt4060_readable_reg, 1069 1069 .writeable_reg = opt4060_writable_reg, ··· 1083 1083 struct { 1084 1084 u32 chan[OPT4060_NUM_CHANS]; 1085 1085 aligned_s64 ts; 1086 1086 - } raw; 1086 1086 + } raw = { }; 1087 1087 int i = 0; 1088 1088 int chan, ret; 1089 1089 1090 1090 /* If the trigger is not from this driver, a new sample is needed.*/ 1091 1091 if (iio_trigger_validate_own_device(idev->trig, idev)) 1092 1092 opt4060_trigger_new_samples(idev); 1093 1093 - 1094 1094 - memset(&raw, 0, sizeof(raw)); 1095 1093 1096 1094 iio_for_each_active_channel(idev, chan) { 1097 1095 if (chan == OPT4060_ILLUM)

+2 -4

drivers/iio/light/rpr0521.c

reviewed

··· 69 69 #define RPR0521_DEFAULT_MEAS_TIME 0x06 /* ALS - 100ms, PXS - 100ms */ 70 70 71 71 #define RPR0521_DRV_NAME "RPR0521" 72 72 - #define RPR0521_IRQ_NAME "rpr0521_event" 73 73 - #define RPR0521_REGMAP_NAME "rpr0521_regmap" 74 72 75 73 #define RPR0521_SLEEP_DELAY_MS 2000 76 74 ··· 912 914 } 913 915 914 916 static const struct regmap_config rpr0521_regmap_config = { 915 915 - .name = RPR0521_REGMAP_NAME, 917 917 + .name = "rpr0521_regmap", 916 918 917 919 .reg_bits = 8, 918 920 .val_bits = 8, ··· 989 991 ret = devm_request_threaded_irq(&client->dev, client->irq, 990 992 rpr0521_drdy_irq_handler, rpr0521_drdy_irq_thread, 991 993 IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 992 992 - RPR0521_IRQ_NAME, indio_dev); 994 994 + "rpr0521_event", indio_dev); 993 995 if (ret < 0) { 994 996 dev_err(&client->dev, "request irq %d for trigger0 failed\n", 995 997 client->irq);

+2 -4

drivers/iio/light/stk3310.c

reviewed

··· 46 46 #define STK3310_PS_MAX_VAL 0xFFFF 47 47 48 48 #define STK3310_DRIVER_NAME "stk3310" 49 49 - #define STK3310_REGMAP_NAME "stk3310_regmap" 50 50 - #define STK3310_EVENT "stk3310_event" 51 49 52 50 #define STK3310_SCALE_AVAILABLE "6.4 1.6 0.4 0.1" 53 51 ··· 525 527 } 526 528 527 529 static const struct regmap_config stk3310_regmap_config = { 528 528 - .name = STK3310_REGMAP_NAME, 530 530 + .name = "stk3310_regmap", 529 531 .reg_bits = 8, 530 532 .val_bits = 8, 531 533 .max_register = STK3310_MAX_REG, ··· 641 643 stk3310_irq_event_handler, 642 644 IRQF_TRIGGER_FALLING | 643 645 IRQF_ONESHOT, 644 644 - STK3310_EVENT, indio_dev); 646 646 + "stk3310_event", indio_dev); 645 647 if (ret < 0) { 646 648 dev_err(&client->dev, "request irq %d failed\n", 647 649 client->irq);

+2 -4

drivers/iio/light/vcnl4035.c

reviewed

··· 23 23 #include <linux/iio/triggered_buffer.h> 24 24 25 25 #define VCNL4035_DRV_NAME "vcnl4035" 26 26 - #define VCNL4035_IRQ_NAME "vcnl4035_event" 27 27 - #define VCNL4035_REGMAP_NAME "vcnl4035_regmap" 28 26 29 27 /* Device registers */ 30 28 #define VCNL4035_ALS_CONF 0x00 ··· 501 503 } 502 504 503 505 static const struct regmap_config vcnl4035_regmap_config = { 504 504 - .name = VCNL4035_REGMAP_NAME, 506 506 + .name = "vcnl4035_regmap", 505 507 .reg_bits = 8, 506 508 .val_bits = 16, 507 509 .max_register = VCNL4035_DEV_ID, ··· 543 545 ret = devm_request_threaded_irq(&data->client->dev, data->client->irq, 544 546 NULL, vcnl4035_drdy_irq_thread, 545 547 IRQF_TRIGGER_LOW | IRQF_ONESHOT, 546 546 - VCNL4035_IRQ_NAME, indio_dev); 548 548 + "vcnl4035_event", indio_dev); 547 549 if (ret < 0) 548 550 dev_err(&data->client->dev, "request irq %d for trigger0 failed\n", 549 551 data->client->irq);

+1 -3

drivers/iio/light/veml6030.c

reviewed

··· 892 892 struct { 893 893 u16 chans[2]; 894 894 aligned_s64 timestamp; 895 895 - } scan; 896 896 - 897 897 - memset(&scan, 0, sizeof(scan)); 895 895 + } scan = { }; 898 896 899 897 iio_for_each_active_channel(iio, ch) { 900 898 ret = regmap_read(data->regmap, VEML6030_REG_DATA(ch),

+3 -3

drivers/iio/light/zopt2201.c

reviewed

··· 119 119 u8 res; /* resolution register value */ 120 120 }; 121 121 122 122 - static struct zopt2201_scale zopt2201_scale_als[] = { 122 122 + static const struct zopt2201_scale zopt2201_scale_als[] = { 123 123 { 19, 200000, 0, 5 }, 124 124 { 6, 400000, 1, 5 }, 125 125 { 3, 200000, 2, 5 }, ··· 144 144 { 0, 8333, 4, 0 }, 145 145 }; 146 146 147 147 - static struct zopt2201_scale zopt2201_scale_uvb[] = { 147 147 + static const struct zopt2201_scale zopt2201_scale_uvb[] = { 148 148 { 0, 460800, 0, 5 }, 149 149 { 0, 153600, 1, 5 }, 150 150 { 0, 76800, 2, 5 }, ··· 347 347 } 348 348 349 349 static int zopt2201_write_scale_by_idx(struct zopt2201_data *data, int idx, 350 350 - struct zopt2201_scale *zopt2201_scale_array) 350 350 + const struct zopt2201_scale *zopt2201_scale_array) 351 351 { 352 352 int ret; 353 353

+1 -3

drivers/iio/magnetometer/af8133j.c

reviewed

··· 361 361 struct { 362 362 __le16 values[3]; 363 363 aligned_s64 timestamp; 364 364 - } sample; 364 364 + } sample = { }; 365 365 int ret; 366 366 - 367 367 - memset(&sample, 0, sizeof(sample)); 368 366 369 367 ret = af8133j_read_measurement(data, sample.values); 370 368 if (ret)

+1 -4

drivers/iio/magnetometer/bmc150_magn.c

reviewed

··· 28 28 29 29 #include "bmc150_magn.h" 30 30 31 31 - #define BMC150_MAGN_DRV_NAME "bmc150_magn" 32 32 - #define BMC150_MAGN_IRQ_NAME "bmc150_magn_event" 33 33 - 34 31 #define BMC150_MAGN_REG_CHIP_ID 0x40 35 32 #define BMC150_MAGN_CHIP_ID_VAL 0x32 36 33 ··· 915 918 iio_trigger_generic_data_rdy_poll, 916 919 NULL, 917 920 IRQF_TRIGGER_RISING | IRQF_ONESHOT, 918 918 - BMC150_MAGN_IRQ_NAME, 921 921 + "bmc150_magn_event", 919 922 data->dready_trig); 920 923 if (ret < 0) { 921 924 dev_err(dev, "request irq %d failed\n", irq);

+1 -2

drivers/iio/magnetometer/mmc35240.c

reviewed

··· 21 21 #include <linux/iio/sysfs.h> 22 22 23 23 #define MMC35240_DRV_NAME "mmc35240" 24 24 - #define MMC35240_REGMAP_NAME "mmc35240_regmap" 25 24 26 25 #define MMC35240_REG_XOUT_L 0x00 27 26 #define MMC35240_REG_XOUT_H 0x01 ··· 462 463 }; 463 464 464 465 static const struct regmap_config mmc35240_regmap_config = { 465 465 - .name = MMC35240_REGMAP_NAME, 466 466 + .name = "mmc35240_regmap", 466 467 467 468 .reg_bits = 8, 468 469 .val_bits = 8,

-1

drivers/iio/potentiometer/ds1803.c

reviewed

··· 13 13 */ 14 14 15 15 #include <linux/err.h> 16 16 - #include <linux/export.h> 17 16 #include <linux/i2c.h> 18 17 #include <linux/iio/iio.h> 19 18 #include <linux/module.h>

-1

drivers/iio/potentiometer/mcp4131.c

reviewed

··· 33 33 34 34 #include <linux/cache.h> 35 35 #include <linux/err.h> 36 36 - #include <linux/export.h> 37 36 #include <linux/iio/iio.h> 38 37 #include <linux/iio/types.h> 39 38 #include <linux/module.h>

+2 -2

drivers/iio/pressure/abp060mg.c

reviewed

··· 35 35 int max; 36 36 }; 37 37 38 38 - static struct abp_config abp_config[] = { 38 38 + static const struct abp_config abp_config[] = { 39 39 /* mbar & kPa variants */ 40 40 [ABP006KG] = { .min = 0, .max = 6000 }, 41 41 [ABP010KG] = { .min = 0, .max = 10000 }, ··· 165 165 static void abp060mg_init_device(struct iio_dev *indio_dev, unsigned long id) 166 166 { 167 167 struct abp_state *state = iio_priv(indio_dev); 168 168 - struct abp_config *cfg = &abp_config[id]; 168 168 + const struct abp_config *cfg = &abp_config[id]; 169 169 170 170 state->scale = cfg->max - cfg->min; 171 171 state->offset = -ABP060MG_MIN_COUNTS;

+1 -4

drivers/iio/pressure/bmp280-core.c

reviewed

··· 1234 1234 s32 comp_temp; 1235 1235 u32 comp_humidity; 1236 1236 aligned_s64 timestamp; 1237 1237 - } buffer; 1237 1237 + } buffer = { }; /* Don't leak uninitialized stack to userspace. */ 1238 1238 int ret; 1239 1239 - 1240 1240 - /* Don't leak uninitialized stack to userspace. */ 1241 1241 - memset(&buffer, 0, sizeof(buffer)); 1242 1239 1243 1240 guard(mutex)(&data->lock); 1244 1241

+21 -26

drivers/iio/pressure/dlhl60d.c

reviewed

··· 32 32 /* DLH timings */ 33 33 #define DLH_SINGLE_DUT_MS 5 34 34 35 35 - enum dhl_ids { 36 36 - dlhl60d, 37 37 - dlhl60g, 38 38 - }; 39 39 - 40 35 struct dlh_info { 36 36 + const char *name; /* chip name */ 41 37 u8 osdig; /* digital offset factor */ 42 38 unsigned int fss; /* full scale span (inch H2O) */ 43 39 }; 44 40 45 41 struct dlh_state { 46 42 struct i2c_client *client; 47 47 - struct dlh_info info; 43 43 + const struct dlh_info *info; 48 44 bool use_interrupt; 49 45 struct completion completion; 50 46 u8 rx_buf[DLH_NUM_READ_BYTES]; 51 47 }; 52 48 53 53 - static struct dlh_info dlh_info_tbl[] = { 54 54 - [dlhl60d] = { 55 55 - .osdig = 2, 56 56 - .fss = 120, 57 57 - }, 58 58 - [dlhl60g] = { 59 59 - .osdig = 10, 60 60 - .fss = 60, 61 61 - }, 49 49 + static const struct dlh_info dlhl60d_info = { 50 50 + .name = "dlhl60d", 51 51 + .osdig = 2, 52 52 + .fss = 120, 62 53 }; 63 54 55 55 + static const struct dlh_info dlhl60g_info = { 56 56 + .name = "dlhl60g", 57 57 + .osdig = 10, 58 58 + .fss = 60, 59 59 + }; 64 60 65 61 static int dlh_cmd_start_single(struct dlh_state *st) 66 62 { ··· 166 170 case IIO_CHAN_INFO_SCALE: 167 171 switch (channel->type) { 168 172 case IIO_PRESSURE: 169 169 - tmp = div_s64(125LL * st->info.fss * 24909 * 100, 173 173 + tmp = div_s64(125LL * st->info->fss * 24909 * 100, 170 174 1 << DLH_NUM_PR_BITS); 171 175 tmp = div_s64_rem(tmp, 1000000000LL, &rem); 172 176 *value = tmp; ··· 184 188 case IIO_CHAN_INFO_OFFSET: 185 189 switch (channel->type) { 186 190 case IIO_PRESSURE: 187 187 - *value = -125 * st->info.fss * 24909; 188 188 - *value2 = 100 * st->info.osdig * 100000; 191 191 + *value = -125 * st->info->fss * 24909; 192 192 + *value2 = 100 * st->info->osdig * 100000; 189 193 return IIO_VAL_FRACTIONAL; 190 194 191 195 case IIO_TEMP: ··· 277 281 278 282 static int dlh_probe(struct i2c_client *client) 279 283 { 280 280 - const struct i2c_device_id *id = i2c_client_get_device_id(client); 281 284 struct dlh_state *st; 282 285 struct iio_dev *indio_dev; 283 286 int ret; ··· 297 302 i2c_set_clientdata(client, indio_dev); 298 303 299 304 st = iio_priv(indio_dev); 300 300 - st->info = dlh_info_tbl[id->driver_data]; 305 305 + st->info = i2c_get_match_data(client); 301 306 st->client = client; 302 307 st->use_interrupt = false; 303 308 304 304 - indio_dev->name = id->name; 309 309 + indio_dev->name = st->info->name; 305 310 indio_dev->info = &dlh_info; 306 311 indio_dev->modes = INDIO_DIRECT_MODE; 307 312 indio_dev->channels = dlh_channels; ··· 311 316 ret = devm_request_threaded_irq(&client->dev, client->irq, 312 317 dlh_interrupt, NULL, 313 318 IRQF_TRIGGER_RISING | IRQF_ONESHOT, 314 314 - id->name, indio_dev); 319 319 + st->info->name, indio_dev); 315 320 if (ret) { 316 321 dev_err(&client->dev, "failed to allocate threaded irq"); 317 322 return ret; ··· 336 341 } 337 342 338 343 static const struct of_device_id dlh_of_match[] = { 339 339 - { .compatible = "asc,dlhl60d" }, 340 340 - { .compatible = "asc,dlhl60g" }, 344 344 + { .compatible = "asc,dlhl60d", .data = &dlhl60d_info }, 345 345 + { .compatible = "asc,dlhl60g", .data = &dlhl60g_info }, 341 346 { } 342 347 }; 343 348 MODULE_DEVICE_TABLE(of, dlh_of_match); 344 349 345 350 static const struct i2c_device_id dlh_id[] = { 346 346 - { "dlhl60d", dlhl60d }, 347 347 - { "dlhl60g", dlhl60g }, 351 351 + { "dlhl60d", (kernel_ulong_t)&dlhl60d_info }, 352 352 + { "dlhl60g", (kernel_ulong_t)&dlhl60g_info }, 348 353 { } 349 354 }; 350 355 MODULE_DEVICE_TABLE(i2c, dlh_id);

+1 -2

drivers/iio/pressure/mpl3115.c

reviewed

··· 160 160 * of the buffer may be either 16 or 32-bits. As such we cannot 161 161 * use a simple structure definition to express this data layout. 162 162 */ 163 163 - u8 buffer[16] __aligned(8); 163 163 + u8 buffer[16] __aligned(8) = { }; 164 164 int ret, pos = 0; 165 165 166 166 mutex_lock(&data->lock); ··· 170 170 goto done; 171 171 } 172 172 173 173 - memset(buffer, 0, sizeof(buffer)); 174 173 if (test_bit(0, indio_dev->active_scan_mask)) { 175 174 ret = i2c_smbus_read_i2c_block_data(data->client, 176 175 MPL3115_OUT_PRESS, 3, &buffer[pos]);

+1 -4

drivers/iio/pressure/mprls0025pa_i2c.c

reviewed

··· 44 44 { 45 45 int ret; 46 46 struct i2c_client *client = to_i2c_client(data->dev); 47 47 - u8 wdata[MPR_PKT_SYNC_LEN]; 48 48 - 49 49 - memset(wdata, 0, sizeof(wdata)); 50 50 - wdata[0] = cmd; 47 47 + u8 wdata[MPR_PKT_SYNC_LEN] = { cmd }; 51 48 52 49 ret = i2c_master_send(client, wdata, MPR_PKT_SYNC_LEN); 53 50 if (ret < 0)

+1 -3

drivers/iio/pressure/zpa2326.c

reviewed

··· 583 583 u32 pressure; 584 584 u16 temperature; 585 585 aligned_s64 timestamp; 586 586 - } sample; 586 586 + } sample = { }; 587 587 int err; 588 588 - 589 589 - memset(&sample, 0, sizeof(sample)); 590 588 591 589 if (test_bit(0, indio_dev->active_scan_mask)) { 592 590 /* Get current pressure from hardware FIFO. */

+9

drivers/iio/proximity/Kconfig

reviewed

··· 32 32 To compile this driver as a module, choose M here: the 33 33 module will be called cros_ec_mkbp_proximity. 34 34 35 35 + config D3323AA 36 36 + tristate "Nicera (Nippon Ceramic Co.) D3-323-AA PIR sensor" 37 37 + depends on GPIOLIB 38 38 + help 39 39 + Say Y here to build a driver for the Nicera D3-323-AA PIR sensor. 40 40 + 41 41 + To compile this driver as a module, choose M here: the module will be 42 42 + called d3323aa. 43 43 + 35 44 config HX9023S 36 45 tristate "TYHX HX9023S SAR sensor" 37 46 select IIO_BUFFER

+1

drivers/iio/proximity/Makefile

reviewed

··· 6 6 # When adding new entries keep the list in alphabetical order 7 7 obj-$(CONFIG_AS3935) += as3935.o 8 8 obj-$(CONFIG_CROS_EC_MKBP_PROXIMITY) += cros_ec_mkbp_proximity.o 9 9 + obj-$(CONFIG_D3323AA) += d3323aa.o 9 10 obj-$(CONFIG_HX9023S) += hx9023s.o 10 11 obj-$(CONFIG_IRSD200) += irsd200.o 11 12 obj-$(CONFIG_ISL29501) += isl29501.o

+816

drivers/iio/proximity/d3323aa.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0-only 2 2 + /* 3 3 + * Driver for Nicera D3-323-AA PIR sensor. 4 4 + * 5 5 + * Copyright (C) 2025 Axis Communications AB 6 6 + */ 7 7 + 8 8 + #include <linux/bitmap.h> 9 9 + #include <linux/cleanup.h> 10 10 + #include <linux/completion.h> 11 11 + #include <linux/delay.h> 12 12 + #include <linux/device.h> 13 13 + #include <linux/gpio/consumer.h> 14 14 + #include <linux/interrupt.h> 15 15 + #include <linux/jiffies.h> 16 16 + #include <linux/mod_devicetable.h> 17 17 + #include <linux/module.h> 18 18 + #include <linux/mutex.h> 19 19 + #include <linux/platform_device.h> 20 20 + #include <linux/regulator/consumer.h> 21 21 + #include <linux/types.h> 22 22 + 23 23 + #include <linux/iio/events.h> 24 24 + #include <linux/iio/iio.h> 25 25 + 26 26 + /* 27 27 + * Register bitmap. 28 28 + * For some reason the first bit is denoted as F37 in the datasheet, the second 29 29 + * as F38 and so on. Note the gap between F60 and F64. 30 30 + */ 31 31 + #define D3323AA_REG_BIT_SLAVEA1 0 /* F37. */ 32 32 + #define D3323AA_REG_BIT_SLAVEA2 1 /* F38. */ 33 33 + #define D3323AA_REG_BIT_SLAVEA3 2 /* F39. */ 34 34 + #define D3323AA_REG_BIT_SLAVEA4 3 /* F40. */ 35 35 + #define D3323AA_REG_BIT_SLAVEA5 4 /* F41. */ 36 36 + #define D3323AA_REG_BIT_SLAVEA6 5 /* F42. */ 37 37 + #define D3323AA_REG_BIT_SLAVEA7 6 /* F43. */ 38 38 + #define D3323AA_REG_BIT_SLAVEA8 7 /* F44. */ 39 39 + #define D3323AA_REG_BIT_SLAVEA9 8 /* F45. */ 40 40 + #define D3323AA_REG_BIT_SLAVEA10 9 /* F46. */ 41 41 + #define D3323AA_REG_BIT_DETLVLABS0 10 /* F47. */ 42 42 + #define D3323AA_REG_BIT_DETLVLABS1 11 /* F48. */ 43 43 + #define D3323AA_REG_BIT_DETLVLABS2 12 /* F49. */ 44 44 + #define D3323AA_REG_BIT_DETLVLABS3 13 /* F50. */ 45 45 + #define D3323AA_REG_BIT_DETLVLABS4 14 /* F51. */ 46 46 + #define D3323AA_REG_BIT_DETLVLABS5 15 /* F52. */ 47 47 + #define D3323AA_REG_BIT_DETLVLABS6 16 /* F53. */ 48 48 + #define D3323AA_REG_BIT_DETLVLABS7 17 /* F54. */ 49 49 + #define D3323AA_REG_BIT_DSLP 18 /* F55. */ 50 50 + #define D3323AA_REG_BIT_FSTEP0 19 /* F56. */ 51 51 + #define D3323AA_REG_BIT_FSTEP1 20 /* F57. */ 52 52 + #define D3323AA_REG_BIT_FILSEL0 21 /* F58. */ 53 53 + #define D3323AA_REG_BIT_FILSEL1 22 /* F59. */ 54 54 + #define D3323AA_REG_BIT_FILSEL2 23 /* F60. */ 55 55 + #define D3323AA_REG_BIT_FDSET 24 /* F64. */ 56 56 + #define D3323AA_REG_BIT_F65 25 57 57 + #define D3323AA_REG_BIT_F87 (D3323AA_REG_BIT_F65 + (87 - 65)) 58 58 + 59 59 + #define D3323AA_REG_NR_BITS (D3323AA_REG_BIT_F87 - D3323AA_REG_BIT_SLAVEA1 + 1) 60 60 + #define D3323AA_THRESH_REG_NR_BITS \ 61 61 + (D3323AA_REG_BIT_DETLVLABS7 - D3323AA_REG_BIT_DETLVLABS0 + 1) 62 62 + #define D3323AA_FILTER_TYPE_NR_BITS \ 63 63 + (D3323AA_REG_BIT_FILSEL2 - D3323AA_REG_BIT_FILSEL0 + 1) 64 64 + #define D3323AA_FILTER_GAIN_REG_NR_BITS \ 65 65 + (D3323AA_REG_BIT_FSTEP1 - D3323AA_REG_BIT_FSTEP0 + 1) 66 66 + 67 67 + #define D3323AA_THRESH_DEFAULT_VAL 56 68 68 + #define D3323AA_FILTER_GAIN_DEFAULT_IDX 1 69 69 + #define D3323AA_LP_FILTER_FREQ_DEFAULT_IDX 1 70 70 + 71 71 + /* 72 72 + * The pattern is 0b01101, but store it reversed (0b10110) due to writing from 73 73 + * LSB on the wire (c.f. d3323aa_write_settings()). 74 74 + */ 75 75 + #define D3323AA_SETTING_END_PATTERN 0x16 76 76 + #define D3323AA_SETTING_END_PATTERN_NR_BITS 5 77 77 + 78 78 + /* 79 79 + * Device should be ready for configuration after this many milliseconds. 80 80 + * Datasheet mentions "approx. 1.2 s". Measurements show around 1.23 s, 81 81 + * therefore add 100 ms of slack. 82 82 + */ 83 83 + #define D3323AA_RESET_TIMEOUT (1200 + 100) 84 84 + 85 85 + /* 86 86 + * The configuration of the device (write and read) should be done within this 87 87 + * many milliseconds. 88 88 + */ 89 89 + #define D3323AA_CONFIG_TIMEOUT 1400 90 90 + 91 91 + /* Number of IRQs needed for configuration stage after reset. */ 92 92 + #define D3323AA_IRQ_RESET_COUNT 2 93 93 + 94 94 + /* 95 95 + * High-pass filter cutoff frequency for the band-pass filter. There is a 96 96 + * corresponding low-pass cutoff frequency for each of the filter types 97 97 + * (denoted A, B, C and D in the datasheet). The index in this array matches 98 98 + * that corresponding value in d3323aa_lp_filter_freq. 99 99 + * Note that this represents a fractional value (e.g. the first value 100 100 + * corresponds to 40 / 100 = 0.4 Hz). 101 101 + */ 102 102 + static const int d3323aa_hp_filter_freq[][2] = { 103 103 + { 40, 100 }, 104 104 + { 30, 100 }, 105 105 + { 30, 100 }, 106 106 + { 1, 100 }, 107 107 + }; 108 108 + 109 109 + /* 110 110 + * Low-pass filter cutoff frequency for the band-pass filter. There is a 111 111 + * corresponding high-pass cutoff frequency for each of the filter types 112 112 + * (denoted A, B, C and D in the datasheet). The index in this array matches 113 113 + * that corresponding value in d3323aa_hp_filter_freq. 114 114 + * Note that this represents a fractional value (e.g. the first value 115 115 + * corresponds to 27 / 10 = 2.7 Hz). 116 116 + */ 117 117 + static const int d3323aa_lp_filter_freq[][2] = { 118 118 + { 27, 10 }, 119 119 + { 15, 10 }, 120 120 + { 5, 1 }, 121 121 + { 100, 1 }, 122 122 + }; 123 123 + 124 124 + /* 125 125 + * Register bitmap values for filter types (denoted A, B, C and D in the 126 126 + * datasheet). The index in this array matches the corresponding value in 127 127 + * d3323aa_lp_filter_freq (which in turn matches d3323aa_hp_filter_freq). For 128 128 + * example, the first value 7 corresponds to 2.7 Hz low-pass and 0.4 Hz 129 129 + * high-pass cutoff frequency. 130 130 + */ 131 131 + static const int d3323aa_lp_filter_regval[] = { 132 132 + 7, 133 133 + 0, 134 134 + 1, 135 135 + 2, 136 136 + }; 137 137 + 138 138 + /* 139 139 + * This is denoted as "step" in datasheet and corresponds to the gain at peak 140 140 + * for the band-pass filter. The index in this array is the corresponding index 141 141 + * in d3323aa_filter_gain_regval for the register bitmap value. 142 142 + */ 143 143 + static const int d3323aa_filter_gain[] = { 1, 2, 3 }; 144 144 + 145 145 + /* 146 146 + * Register bitmap values for the filter gain. The index in this array is the 147 147 + * corresponding index in d3323aa_filter_gain for the gain value. 148 148 + */ 149 149 + static const u8 d3323aa_filter_gain_regval[] = { 1, 3, 0 }; 150 150 + 151 151 + struct d3323aa_data { 152 152 + struct completion reset_completion; 153 153 + /* 154 154 + * Since the setup process always requires a complete write of _all_ 155 155 + * the state variables, we need to synchronize them with a lock. 156 156 + */ 157 157 + struct mutex statevar_lock; 158 158 + 159 159 + struct device *dev; 160 160 + 161 161 + /* Supply voltage. */ 162 162 + struct regulator *regulator_vdd; 163 163 + /* Input clock or output detection signal (Vout). */ 164 164 + struct gpio_desc *gpiod_clkin_detectout; 165 165 + /* Input (setting) or output data. */ 166 166 + struct gpio_desc *gpiod_data; 167 167 + 168 168 + /* 169 169 + * We only need the low-pass cutoff frequency to unambiguously choose 170 170 + * the type of band-pass filter. For example, both filter type B and C 171 171 + * have 0.3 Hz as high-pass cutoff frequency (see 172 172 + * d3323aa_hp_filter_freq). 173 173 + */ 174 174 + size_t lp_filter_freq_idx; 175 175 + size_t filter_gain_idx; 176 176 + u8 detect_thresh; 177 177 + u8 irq_reset_count; 178 178 + 179 179 + /* Indicator for operational mode (configuring or detecting). */ 180 180 + bool detecting; 181 181 + }; 182 182 + 183 183 + static int d3323aa_read_settings(struct iio_dev *indio_dev, 184 184 + unsigned long *regbitmap) 185 185 + { 186 186 + struct d3323aa_data *data = iio_priv(indio_dev); 187 187 + size_t i; 188 188 + int ret; 189 189 + 190 190 + /* Bit bang the clock and data pins. */ 191 191 + ret = gpiod_direction_output(data->gpiod_clkin_detectout, 0); 192 192 + if (ret) 193 193 + return ret; 194 194 + 195 195 + ret = gpiod_direction_input(data->gpiod_data); 196 196 + if (ret) 197 197 + return ret; 198 198 + 199 199 + dev_dbg(data->dev, "Reading settings...\n"); 200 200 + 201 201 + for (i = 0; i < D3323AA_REG_NR_BITS; ++i) { 202 202 + /* Clock frequency needs to be 1 kHz. */ 203 203 + gpiod_set_value(data->gpiod_clkin_detectout, 1); 204 204 + udelay(500); 205 205 + 206 206 + /* The data seems to change when clock signal is high. */ 207 207 + if (gpiod_get_value(data->gpiod_data)) 208 208 + set_bit(i, regbitmap); 209 209 + 210 210 + gpiod_set_value(data->gpiod_clkin_detectout, 0); 211 211 + udelay(500); 212 212 + } 213 213 + 214 214 + /* The first bit (F37) is just dummy data. Discard it. */ 215 215 + clear_bit(0, regbitmap); 216 216 + 217 217 + /* Datasheet says to wait 30 ms after reading the settings. */ 218 218 + msleep(30); 219 219 + 220 220 + return 0; 221 221 + } 222 222 + 223 223 + static int d3323aa_write_settings(struct iio_dev *indio_dev, 224 224 + unsigned long *written_regbitmap) 225 225 + { 226 226 + #define REGBITMAP_LEN \ 227 227 + (D3323AA_REG_NR_BITS + D3323AA_SETTING_END_PATTERN_NR_BITS) 228 228 + DECLARE_BITMAP(regbitmap, REGBITMAP_LEN); 229 229 + struct d3323aa_data *data = iio_priv(indio_dev); 230 230 + size_t i; 231 231 + int ret; 232 232 + 233 233 + /* Build the register bitmap. */ 234 234 + bitmap_zero(regbitmap, REGBITMAP_LEN); 235 235 + bitmap_write(regbitmap, data->detect_thresh, D3323AA_REG_BIT_DETLVLABS0, 236 236 + D3323AA_REG_BIT_DETLVLABS7 - D3323AA_REG_BIT_DETLVLABS0 + 237 237 + 1); 238 238 + bitmap_write(regbitmap, 239 239 + d3323aa_filter_gain_regval[data->filter_gain_idx], 240 240 + D3323AA_REG_BIT_FSTEP0, 241 241 + D3323AA_REG_BIT_FSTEP1 - D3323AA_REG_BIT_FSTEP0 + 1); 242 242 + bitmap_write(regbitmap, 243 243 + d3323aa_lp_filter_regval[data->lp_filter_freq_idx], 244 244 + D3323AA_REG_BIT_FILSEL0, 245 245 + D3323AA_REG_BIT_FILSEL2 - D3323AA_REG_BIT_FILSEL0 + 1); 246 246 + /* Compulsory end pattern. */ 247 247 + bitmap_write(regbitmap, D3323AA_SETTING_END_PATTERN, 248 248 + D3323AA_REG_NR_BITS, D3323AA_SETTING_END_PATTERN_NR_BITS); 249 249 + 250 250 + /* Bit bang the clock and data pins. */ 251 251 + ret = gpiod_direction_output(data->gpiod_clkin_detectout, 0); 252 252 + if (ret) 253 253 + return ret; 254 254 + 255 255 + ret = gpiod_direction_output(data->gpiod_data, 0); 256 256 + if (ret) 257 257 + return ret; 258 258 + 259 259 + dev_dbg(data->dev, "Writing settings...\n"); 260 260 + 261 261 + /* First bit (F37) is not used when writing the register bitmap. */ 262 262 + for (i = 1; i < REGBITMAP_LEN; ++i) { 263 263 + gpiod_set_value(data->gpiod_data, test_bit(i, regbitmap)); 264 264 + 265 265 + /* Clock frequency needs to be 1 kHz. */ 266 266 + gpiod_set_value(data->gpiod_clkin_detectout, 1); 267 267 + udelay(500); 268 268 + gpiod_set_value(data->gpiod_clkin_detectout, 0); 269 269 + udelay(500); 270 270 + } 271 271 + 272 272 + /* Datasheet says to wait 30 ms after writing the settings. */ 273 273 + msleep(30); 274 274 + 275 275 + bitmap_copy(written_regbitmap, regbitmap, D3323AA_REG_NR_BITS); 276 276 + 277 277 + return 0; 278 278 + } 279 279 + 280 280 + static irqreturn_t d3323aa_irq_handler(int irq, void *dev_id) 281 281 + { 282 282 + struct iio_dev *indio_dev = dev_id; 283 283 + struct d3323aa_data *data = iio_priv(indio_dev); 284 284 + enum iio_event_direction dir; 285 285 + int val; 286 286 + 287 287 + val = gpiod_get_value(data->gpiod_clkin_detectout); 288 288 + if (val < 0) { 289 289 + dev_err_ratelimited(data->dev, 290 290 + "Could not read from GPIO vout-clk (%d)\n", 291 291 + val); 292 292 + return IRQ_HANDLED; 293 293 + } 294 294 + 295 295 + if (!data->detecting) { 296 296 + /* Reset interrupt counting falling edges. */ 297 297 + if (!val && ++data->irq_reset_count == D3323AA_IRQ_RESET_COUNT) 298 298 + complete(&data->reset_completion); 299 299 + 300 300 + return IRQ_HANDLED; 301 301 + } 302 302 + 303 303 + /* Detection interrupt. */ 304 304 + dir = val ? IIO_EV_DIR_RISING : IIO_EV_DIR_FALLING; 305 305 + iio_push_event(indio_dev, 306 306 + IIO_UNMOD_EVENT_CODE(IIO_PROXIMITY, 0, 307 307 + IIO_EV_TYPE_THRESH, dir), 308 308 + iio_get_time_ns(indio_dev)); 309 309 + 310 310 + return IRQ_HANDLED; 311 311 + } 312 312 + 313 313 + static int d3323aa_reset(struct iio_dev *indio_dev) 314 314 + { 315 315 + struct d3323aa_data *data = iio_priv(indio_dev); 316 316 + long time; 317 317 + int ret; 318 318 + 319 319 + /* During probe() the regulator may already be disabled. */ 320 320 + if (regulator_is_enabled(data->regulator_vdd)) { 321 321 + ret = regulator_disable(data->regulator_vdd); 322 322 + if (ret) 323 323 + return ret; 324 324 + } 325 325 + 326 326 + /* 327 327 + * Datasheet says VDD needs to be low at least for 30 ms. Let's add a 328 328 + * couple more to allow VDD to completely discharge as well. 329 329 + */ 330 330 + fsleep((30 + 5) * USEC_PER_MSEC); 331 331 + 332 332 + /* 333 333 + * When later enabling VDD, the device will signal with 334 334 + * D3323AA_IRQ_RESET_COUNT falling edges on Vout/CLK that it is now 335 335 + * ready for configuration. Datasheet says that this should happen 336 336 + * within D3323AA_RESET_TIMEOUT ms. Count these two edges within that 337 337 + * timeout. 338 338 + */ 339 339 + data->irq_reset_count = 0; 340 340 + reinit_completion(&data->reset_completion); 341 341 + data->detecting = false; 342 342 + 343 343 + ret = gpiod_direction_input(data->gpiod_clkin_detectout); 344 344 + if (ret) 345 345 + return ret; 346 346 + 347 347 + dev_dbg(data->dev, "Resetting...\n"); 348 348 + 349 349 + ret = regulator_enable(data->regulator_vdd); 350 350 + if (ret) 351 351 + return ret; 352 352 + 353 353 + /* 354 354 + * Wait for VDD to completely charge up. Measurements have shown that 355 355 + * Vout/CLK signal slowly ramps up during this period. Thus, the digital 356 356 + * signal will have bogus values. It is therefore necessary to wait 357 357 + * before we can count the "real" falling edges. 358 358 + */ 359 359 + fsleep(2000); 360 360 + 361 361 + time = wait_for_completion_killable_timeout( 362 362 + &data->reset_completion, 363 363 + msecs_to_jiffies(D3323AA_RESET_TIMEOUT)); 364 364 + if (time == 0) { 365 365 + return -ETIMEDOUT; 366 366 + } else if (time < 0) { 367 367 + /* Got interrupted. */ 368 368 + return time; 369 369 + } 370 370 + 371 371 + dev_dbg(data->dev, "Reset completed\n"); 372 372 + 373 373 + return 0; 374 374 + } 375 375 + 376 376 + static int d3323aa_setup(struct iio_dev *indio_dev, size_t lp_filter_freq_idx, 377 377 + size_t filter_gain_idx, u8 detect_thresh) 378 378 + { 379 379 + DECLARE_BITMAP(write_regbitmap, D3323AA_REG_NR_BITS); 380 380 + DECLARE_BITMAP(read_regbitmap, D3323AA_REG_NR_BITS); 381 381 + struct d3323aa_data *data = iio_priv(indio_dev); 382 382 + unsigned long start_time; 383 383 + int ret; 384 384 + 385 385 + ret = d3323aa_reset(indio_dev); 386 386 + if (ret) { 387 387 + if (ret != -ERESTARTSYS) 388 388 + dev_err(data->dev, "Could not reset device (%d)\n", 389 389 + ret); 390 390 + 391 391 + return ret; 392 392 + } 393 393 + 394 394 + /* 395 395 + * Datasheet says to wait 10 us before setting the configuration. 396 396 + * Moreover, the total configuration should be done within 397 397 + * D3323AA_CONFIG_TIMEOUT ms. Clock it. 398 398 + */ 399 399 + fsleep(10); 400 400 + start_time = jiffies; 401 401 + 402 402 + ret = d3323aa_write_settings(indio_dev, write_regbitmap); 403 403 + if (ret) { 404 404 + dev_err(data->dev, "Could not write settings (%d)\n", ret); 405 405 + return ret; 406 406 + } 407 407 + 408 408 + ret = d3323aa_read_settings(indio_dev, read_regbitmap); 409 409 + if (ret) { 410 410 + dev_err(data->dev, "Could not read settings (%d)\n", ret); 411 411 + return ret; 412 412 + } 413 413 + 414 414 + if (time_is_before_jiffies(start_time + 415 415 + msecs_to_jiffies(D3323AA_CONFIG_TIMEOUT))) { 416 416 + dev_err(data->dev, "Could not set up configuration in time\n"); 417 417 + return -EAGAIN; 418 418 + } 419 419 + 420 420 + /* Check if settings were set successfully. */ 421 421 + if (!bitmap_equal(write_regbitmap, read_regbitmap, 422 422 + D3323AA_REG_NR_BITS)) { 423 423 + dev_err(data->dev, "Settings data mismatch\n"); 424 424 + return -EIO; 425 425 + } 426 426 + 427 427 + /* Now in operational mode. */ 428 428 + ret = gpiod_direction_input(data->gpiod_clkin_detectout); 429 429 + if (ret) { 430 430 + dev_err(data->dev, 431 431 + "Could not set GPIO vout-clk as input (%d)\n", ret); 432 432 + return ret; 433 433 + } 434 434 + 435 435 + ret = gpiod_direction_input(data->gpiod_data); 436 436 + if (ret) { 437 437 + dev_err(data->dev, "Could not set GPIO data as input (%d)\n", 438 438 + ret); 439 439 + return ret; 440 440 + } 441 441 + 442 442 + data->lp_filter_freq_idx = lp_filter_freq_idx; 443 443 + data->filter_gain_idx = filter_gain_idx; 444 444 + data->detect_thresh = detect_thresh; 445 445 + data->detecting = true; 446 446 + 447 447 + dev_dbg(data->dev, "Setup done\n"); 448 448 + 449 449 + return 0; 450 450 + } 451 451 + 452 452 + static int d3323aa_set_lp_filter_freq(struct iio_dev *indio_dev, const int val, 453 453 + int val2) 454 454 + { 455 455 + struct d3323aa_data *data = iio_priv(indio_dev); 456 456 + size_t idx; 457 457 + 458 458 + /* Truncate fractional part to one digit. */ 459 459 + val2 /= 100000; 460 460 + 461 461 + for (idx = 0; idx < ARRAY_SIZE(d3323aa_lp_filter_freq); ++idx) { 462 462 + int integer = d3323aa_lp_filter_freq[idx][0] / 463 463 + d3323aa_lp_filter_freq[idx][1]; 464 464 + int fract = d3323aa_lp_filter_freq[idx][0] % 465 465 + d3323aa_lp_filter_freq[idx][1]; 466 466 + 467 467 + if (val == integer && val2 == fract) 468 468 + break; 469 469 + } 470 470 + 471 471 + if (idx == ARRAY_SIZE(d3323aa_lp_filter_freq)) 472 472 + return -EINVAL; 473 473 + 474 474 + return d3323aa_setup(indio_dev, idx, data->filter_gain_idx, 475 475 + data->detect_thresh); 476 476 + } 477 477 + 478 478 + static int d3323aa_set_hp_filter_freq(struct iio_dev *indio_dev, const int val, 479 479 + int val2) 480 480 + { 481 481 + struct d3323aa_data *data = iio_priv(indio_dev); 482 482 + size_t idx; 483 483 + 484 484 + /* Truncate fractional part to two digits. */ 485 485 + val2 /= 10000; 486 486 + 487 487 + for (idx = 0; idx < ARRAY_SIZE(d3323aa_hp_filter_freq); ++idx) { 488 488 + int integer = d3323aa_hp_filter_freq[idx][0] / 489 489 + d3323aa_hp_filter_freq[idx][1]; 490 490 + int fract = d3323aa_hp_filter_freq[idx][0] % 491 491 + d3323aa_hp_filter_freq[idx][1]; 492 492 + 493 493 + if (val == integer && val2 == fract) 494 494 + break; 495 495 + } 496 496 + 497 497 + if (idx == ARRAY_SIZE(d3323aa_hp_filter_freq)) 498 498 + return -EINVAL; 499 499 + 500 500 + if (idx == data->lp_filter_freq_idx) { 501 501 + /* Corresponding filter frequency already set. */ 502 502 + return 0; 503 503 + } 504 504 + 505 505 + if (idx == 1 && data->lp_filter_freq_idx == 2) { 506 506 + /* 507 507 + * The low-pass cutoff frequency is the only way to 508 508 + * unambiguously choose the type of band-pass filter. For 509 509 + * example, both filter type B (index 1) and C (index 2) have 510 510 + * 0.3 Hz as high-pass cutoff frequency (see 511 511 + * d3323aa_hp_filter_freq). Therefore, if one of these are 512 512 + * requested _and_ the corresponding low-pass filter frequency 513 513 + * is already set, we can't know which filter type is the wanted 514 514 + * one. The low-pass filter frequency is the decider (i.e. in 515 515 + * this case index 2). 516 516 + */ 517 517 + return 0; 518 518 + } 519 519 + 520 520 + return d3323aa_setup(indio_dev, idx, data->filter_gain_idx, 521 521 + data->detect_thresh); 522 522 + } 523 523 + 524 524 + static int d3323aa_set_filter_gain(struct iio_dev *indio_dev, const int val) 525 525 + { 526 526 + struct d3323aa_data *data = iio_priv(indio_dev); 527 527 + size_t idx; 528 528 + 529 529 + for (idx = 0; idx < ARRAY_SIZE(d3323aa_filter_gain); ++idx) { 530 530 + if (d3323aa_filter_gain[idx] == val) 531 531 + break; 532 532 + } 533 533 + 534 534 + if (idx == ARRAY_SIZE(d3323aa_filter_gain)) 535 535 + return -EINVAL; 536 536 + 537 537 + return d3323aa_setup(indio_dev, data->lp_filter_freq_idx, idx, 538 538 + data->detect_thresh); 539 539 + } 540 540 + 541 541 + static int d3323aa_set_threshold(struct iio_dev *indio_dev, const int val) 542 542 + { 543 543 + struct d3323aa_data *data = iio_priv(indio_dev); 544 544 + 545 545 + if (val > ((1 << D3323AA_THRESH_REG_NR_BITS) - 1)) 546 546 + return -EINVAL; 547 547 + 548 548 + return d3323aa_setup(indio_dev, data->lp_filter_freq_idx, 549 549 + data->filter_gain_idx, val); 550 550 + } 551 551 + 552 552 + static int d3323aa_read_avail(struct iio_dev *indio_dev, 553 553 + struct iio_chan_spec const *chan, 554 554 + const int **vals, int *type, int *length, 555 555 + long mask) 556 556 + { 557 557 + switch (mask) { 558 558 + case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY: 559 559 + *vals = (int *)d3323aa_hp_filter_freq; 560 560 + *type = IIO_VAL_FRACTIONAL; 561 561 + *length = 2 * ARRAY_SIZE(d3323aa_hp_filter_freq); 562 562 + return IIO_AVAIL_LIST; 563 563 + case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 564 564 + *vals = (int *)d3323aa_lp_filter_freq; 565 565 + *type = IIO_VAL_FRACTIONAL; 566 566 + *length = 2 * ARRAY_SIZE(d3323aa_lp_filter_freq); 567 567 + return IIO_AVAIL_LIST; 568 568 + case IIO_CHAN_INFO_HARDWAREGAIN: 569 569 + *vals = (int *)d3323aa_filter_gain; 570 570 + *type = IIO_VAL_INT; 571 571 + *length = ARRAY_SIZE(d3323aa_filter_gain); 572 572 + return IIO_AVAIL_LIST; 573 573 + default: 574 574 + return -EINVAL; 575 575 + } 576 576 + } 577 577 + 578 578 + static int d3323aa_read_raw(struct iio_dev *indio_dev, 579 579 + struct iio_chan_spec const *chan, int *val, 580 580 + int *val2, long mask) 581 581 + { 582 582 + struct d3323aa_data *data = iio_priv(indio_dev); 583 583 + 584 584 + guard(mutex)(&data->statevar_lock); 585 585 + 586 586 + switch (mask) { 587 587 + case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY: 588 588 + *val = d3323aa_hp_filter_freq[data->lp_filter_freq_idx][0]; 589 589 + *val2 = d3323aa_hp_filter_freq[data->lp_filter_freq_idx][1]; 590 590 + return IIO_VAL_FRACTIONAL; 591 591 + case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 592 592 + *val = d3323aa_lp_filter_freq[data->lp_filter_freq_idx][0]; 593 593 + *val2 = d3323aa_lp_filter_freq[data->lp_filter_freq_idx][1]; 594 594 + return IIO_VAL_FRACTIONAL; 595 595 + case IIO_CHAN_INFO_HARDWAREGAIN: 596 596 + *val = d3323aa_filter_gain[data->filter_gain_idx]; 597 597 + return IIO_VAL_INT; 598 598 + default: 599 599 + return -EINVAL; 600 600 + } 601 601 + } 602 602 + 603 603 + static int d3323aa_write_raw(struct iio_dev *indio_dev, 604 604 + struct iio_chan_spec const *chan, int val, 605 605 + int val2, long mask) 606 606 + { 607 607 + struct d3323aa_data *data = iio_priv(indio_dev); 608 608 + 609 609 + guard(mutex)(&data->statevar_lock); 610 610 + 611 611 + switch (mask) { 612 612 + case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY: 613 613 + return d3323aa_set_hp_filter_freq(indio_dev, val, val2); 614 614 + case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 615 615 + return d3323aa_set_lp_filter_freq(indio_dev, val, val2); 616 616 + case IIO_CHAN_INFO_HARDWAREGAIN: 617 617 + return d3323aa_set_filter_gain(indio_dev, val); 618 618 + default: 619 619 + return -EINVAL; 620 620 + } 621 621 + } 622 622 + 623 623 + static int d3323aa_read_event(struct iio_dev *indio_dev, 624 624 + const struct iio_chan_spec *chan, 625 625 + enum iio_event_type type, 626 626 + enum iio_event_direction dir, 627 627 + enum iio_event_info info, int *val, int *val2) 628 628 + { 629 629 + struct d3323aa_data *data = iio_priv(indio_dev); 630 630 + 631 631 + guard(mutex)(&data->statevar_lock); 632 632 + 633 633 + switch (info) { 634 634 + case IIO_EV_INFO_VALUE: 635 635 + *val = data->detect_thresh; 636 636 + return IIO_VAL_INT; 637 637 + default: 638 638 + return -EINVAL; 639 639 + } 640 640 + } 641 641 + 642 642 + static int d3323aa_write_event(struct iio_dev *indio_dev, 643 643 + const struct iio_chan_spec *chan, 644 644 + enum iio_event_type type, 645 645 + enum iio_event_direction dir, 646 646 + enum iio_event_info info, int val, int val2) 647 647 + { 648 648 + struct d3323aa_data *data = iio_priv(indio_dev); 649 649 + 650 650 + guard(mutex)(&data->statevar_lock); 651 651 + 652 652 + switch (info) { 653 653 + case IIO_EV_INFO_VALUE: 654 654 + return d3323aa_set_threshold(indio_dev, val); 655 655 + default: 656 656 + return -EINVAL; 657 657 + } 658 658 + } 659 659 + 660 660 + static const struct iio_info d3323aa_info = { 661 661 + .read_avail = d3323aa_read_avail, 662 662 + .read_raw = d3323aa_read_raw, 663 663 + .write_raw = d3323aa_write_raw, 664 664 + .read_event_value = d3323aa_read_event, 665 665 + .write_event_value = d3323aa_write_event, 666 666 + }; 667 667 + 668 668 + static const struct iio_event_spec d3323aa_event_spec[] = { 669 669 + { 670 670 + .type = IIO_EV_TYPE_THRESH, 671 671 + .dir = IIO_EV_DIR_RISING, 672 672 + .mask_separate = BIT(IIO_EV_INFO_VALUE), 673 673 + }, 674 674 + { 675 675 + .type = IIO_EV_TYPE_THRESH, 676 676 + .dir = IIO_EV_DIR_FALLING, 677 677 + .mask_separate = BIT(IIO_EV_INFO_VALUE), 678 678 + }, 679 679 + }; 680 680 + 681 681 + static const struct iio_chan_spec d3323aa_channels[] = { 682 682 + { 683 683 + .type = IIO_PROXIMITY, 684 684 + .info_mask_separate = 685 685 + BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY) | 686 686 + BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | 687 687 + BIT(IIO_CHAN_INFO_HARDWAREGAIN), 688 688 + .info_mask_separate_available = 689 689 + BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY) | 690 690 + BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | 691 691 + BIT(IIO_CHAN_INFO_HARDWAREGAIN), 692 692 + .event_spec = d3323aa_event_spec, 693 693 + .num_event_specs = ARRAY_SIZE(d3323aa_event_spec), 694 694 + }, 695 695 + }; 696 696 + 697 697 + static void d3323aa_disable_regulator(void *indata) 698 698 + { 699 699 + struct d3323aa_data *data = indata; 700 700 + int ret; 701 701 + 702 702 + /* 703 703 + * During probe() the regulator may be disabled. It is enabled during 704 704 + * device setup (in d3323aa_reset(), where it is also briefly disabled). 705 705 + * The check is therefore needed in order to have balanced 706 706 + * regulator_enable/disable() calls. 707 707 + */ 708 708 + if (!regulator_is_enabled(data->regulator_vdd)) 709 709 + return; 710 710 + 711 711 + ret = regulator_disable(data->regulator_vdd); 712 712 + if (ret) 713 713 + dev_err(data->dev, "Could not disable regulator (%d)\n", ret); 714 714 + } 715 715 + 716 716 + static int d3323aa_probe(struct platform_device *pdev) 717 717 + { 718 718 + struct device *dev = &pdev->dev; 719 719 + struct d3323aa_data *data; 720 720 + struct iio_dev *indio_dev; 721 721 + int ret; 722 722 + 723 723 + indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); 724 724 + if (!indio_dev) 725 725 + return dev_err_probe(dev, -ENOMEM, 726 726 + "Could not allocate iio device\n"); 727 727 + 728 728 + data = iio_priv(indio_dev); 729 729 + data->dev = dev; 730 730 + 731 731 + init_completion(&data->reset_completion); 732 732 + 733 733 + ret = devm_mutex_init(dev, &data->statevar_lock); 734 734 + if (ret) 735 735 + return dev_err_probe(dev, ret, "Could not initialize mutex\n"); 736 736 + 737 737 + data->regulator_vdd = devm_regulator_get_exclusive(dev, "vdd"); 738 738 + if (IS_ERR(data->regulator_vdd)) 739 739 + return dev_err_probe(dev, PTR_ERR(data->regulator_vdd), 740 740 + "Could not get regulator\n"); 741 741 + 742 742 + /* 743 743 + * The regulator will be enabled for the first time during the 744 744 + * device setup below (in d3323aa_reset()). However parameter changes 745 745 + * from userspace can require a temporary disable of the regulator. 746 746 + * To avoid complex handling of state, use a callback that will disable 747 747 + * the regulator if it happens to be enabled at time of devm unwind. 748 748 + */ 749 749 + ret = devm_add_action_or_reset(dev, d3323aa_disable_regulator, data); 750 750 + if (ret) 751 751 + return ret; 752 752 + 753 753 + data->gpiod_clkin_detectout = 754 754 + devm_gpiod_get(dev, "vout-clk", GPIOD_OUT_LOW); 755 755 + if (IS_ERR(data->gpiod_clkin_detectout)) 756 756 + return dev_err_probe(dev, PTR_ERR(data->gpiod_clkin_detectout), 757 757 + "Could not get GPIO vout-clk\n"); 758 758 + 759 759 + data->gpiod_data = devm_gpiod_get(dev, "data", GPIOD_OUT_LOW); 760 760 + if (IS_ERR(data->gpiod_data)) 761 761 + return dev_err_probe(dev, PTR_ERR(data->gpiod_data), 762 762 + "Could not get GPIO data\n"); 763 763 + 764 764 + ret = gpiod_to_irq(data->gpiod_clkin_detectout); 765 765 + if (ret < 0) 766 766 + return dev_err_probe(dev, ret, "Could not get IRQ\n"); 767 767 + 768 768 + /* 769 769 + * Device signals with a rising or falling detection signal when the 770 770 + * proximity data is above or below the threshold, respectively. 771 771 + */ 772 772 + ret = devm_request_irq(dev, ret, d3323aa_irq_handler, 773 773 + IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, 774 774 + dev_name(dev), indio_dev); 775 775 + if (ret) 776 776 + return dev_err_probe(dev, ret, "Could not request IRQ\n"); 777 777 + 778 778 + ret = d3323aa_setup(indio_dev, D3323AA_LP_FILTER_FREQ_DEFAULT_IDX, 779 779 + D3323AA_FILTER_GAIN_DEFAULT_IDX, 780 780 + D3323AA_THRESH_DEFAULT_VAL); 781 781 + if (ret) 782 782 + return ret; 783 783 + 784 784 + indio_dev->info = &d3323aa_info; 785 785 + indio_dev->name = "d3323aa"; 786 786 + indio_dev->channels = d3323aa_channels; 787 787 + indio_dev->num_channels = ARRAY_SIZE(d3323aa_channels); 788 788 + 789 789 + ret = devm_iio_device_register(dev, indio_dev); 790 790 + if (ret) 791 791 + return dev_err_probe(dev, ret, 792 792 + "Could not register iio device\n"); 793 793 + 794 794 + return 0; 795 795 + } 796 796 + 797 797 + static const struct of_device_id d3323aa_of_match[] = { 798 798 + { 799 799 + .compatible = "nicera,d3323aa", 800 800 + }, 801 801 + { } 802 802 + }; 803 803 + MODULE_DEVICE_TABLE(of, d3323aa_of_match); 804 804 + 805 805 + static struct platform_driver d3323aa_driver = { 806 806 + .probe = d3323aa_probe, 807 807 + .driver = { 808 808 + .name = "d3323aa", 809 809 + .of_match_table = d3323aa_of_match, 810 810 + }, 811 811 + }; 812 812 + module_platform_driver(d3323aa_driver); 813 813 + 814 814 + MODULE_AUTHOR("Waqar Hameed <waqar.hameed@axis.com>"); 815 815 + MODULE_DESCRIPTION("Nicera D3-323-AA PIR sensor driver"); 816 816 + MODULE_LICENSE("GPL");

+8 -14

drivers/iio/proximity/irsd200.c

reviewed

··· 763 763 struct { 764 764 s16 channel; 765 765 aligned_s64 ts; 766 766 - } scan; 766 766 + } scan = { }; 767 767 int ret; 768 768 769 769 - memset(&scan, 0, sizeof(scan)); 770 769 ret = irsd200_read_data(data, &scan.channel); 771 770 if (ret) 772 771 goto end; ··· 884 885 885 886 ret = devm_regulator_get_enable(data->dev, "vdd"); 886 887 if (ret) 887 887 - return dev_err_probe( 888 888 - data->dev, ret, 889 889 - "Could not get and enable regulator (%d)\n", ret); 888 888 + return dev_err_probe(data->dev, ret, 889 889 + "Could not get and enable regulator\n"); 890 890 891 891 ret = irsd200_setup(data); 892 892 if (ret) ··· 903 905 ret = devm_iio_triggered_buffer_setup(data->dev, indio_dev, NULL, 904 906 irsd200_trigger_handler, NULL); 905 907 if (ret) 906 906 - return dev_err_probe( 907 907 - data->dev, ret, 908 908 - "Could not setup iio triggered buffer (%d)\n", ret); 908 908 + return dev_err_probe(data->dev, ret, 909 909 + "Could not setup iio triggered buffer\n"); 909 910 910 911 ret = devm_request_threaded_irq(data->dev, client->irq, NULL, 911 912 irsd200_irq_thread, 912 913 IRQF_TRIGGER_RISING | IRQF_ONESHOT, 913 914 NULL, indio_dev); 914 915 if (ret) 915 915 - return dev_err_probe(data->dev, ret, 916 916 - "Could not request irq (%d)\n", ret); 916 916 + return dev_err_probe(data->dev, ret, "Could not request irq\n"); 917 917 918 918 trigger = devm_iio_trigger_alloc(data->dev, "%s-dev%d", indio_dev->name, 919 919 iio_device_id(indio_dev)); ··· 925 929 ret = devm_iio_trigger_register(data->dev, trigger); 926 930 if (ret) 927 931 return dev_err_probe(data->dev, ret, 928 928 - "Could not register iio trigger (%d)\n", 929 929 - ret); 932 932 + "Could not register iio trigger\n"); 930 933 931 934 ret = devm_iio_device_register(data->dev, indio_dev); 932 935 if (ret) 933 936 return dev_err_probe(data->dev, ret, 934 934 - "Could not register iio device (%d)\n", 935 935 - ret); 937 937 + "Could not register iio device\n"); 936 938 937 939 return 0; 938 940 }

+1 -2

drivers/iio/proximity/sx9500.c

reviewed

··· 27 27 #include <linux/iio/trigger_consumer.h> 28 28 29 29 #define SX9500_DRIVER_NAME "sx9500" 30 30 - #define SX9500_IRQ_NAME "sx9500_event" 31 30 32 31 /* Register definitions. */ 33 32 #define SX9500_REG_IRQ_SRC 0x00 ··· 937 938 ret = devm_request_threaded_irq(&client->dev, client->irq, 938 939 sx9500_irq_handler, sx9500_irq_thread_handler, 939 940 IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 940 940 - SX9500_IRQ_NAME, indio_dev); 941 941 + "sx9500_event", indio_dev); 941 942 if (ret < 0) 942 943 return ret; 943 944

+8 -8

drivers/iio/proximity/vcnl3020.c

reviewed

··· 102 102 return *val /= 10000; 103 103 }; 104 104 105 105 - static struct vcnl3020_property vcnl3020_led_current_property = { 105 105 + static const struct vcnl3020_property vcnl3020_led_current_property = { 106 106 .name = "vishay,led-current-microamp", 107 107 .reg = VCNL_LED_CURRENT, 108 108 .conversion_func = microamp_to_reg, 109 109 }; 110 110 111 111 static int vcnl3020_get_and_apply_property(struct vcnl3020_data *data, 112 112 - struct vcnl3020_property prop) 112 112 + const struct vcnl3020_property *prop) 113 113 { 114 114 int rc; 115 115 u32 val; 116 116 117 117 - rc = device_property_read_u32(data->dev, prop.name, &val); 117 117 + rc = device_property_read_u32(data->dev, prop->name, &val); 118 118 if (rc) 119 119 return 0; 120 120 121 121 - if (prop.conversion_func) 122 122 - prop.conversion_func(&val); 121 121 + if (prop->conversion_func) 122 122 + prop->conversion_func(&val); 123 123 124 124 - rc = regmap_write(data->regmap, prop.reg, val); 124 124 + rc = regmap_write(data->regmap, prop->reg, val); 125 125 if (rc) { 126 126 dev_err(data->dev, "Error (%d) setting property (%s)\n", 127 127 - rc, prop.name); 127 127 + rc, prop->name); 128 128 } 129 129 130 130 return rc; ··· 153 153 mutex_init(&data->lock); 154 154 155 155 return vcnl3020_get_and_apply_property(data, 156 156 - vcnl3020_led_current_property); 156 156 + &vcnl3020_led_current_property); 157 157 }; 158 158 159 159 static bool vcnl3020_is_in_periodic_mode(struct vcnl3020_data *data)

+1 -2

drivers/iio/resolver/ad2s1200.c

reviewed

··· 21 21 #include <linux/iio/iio.h> 22 22 #include <linux/iio/sysfs.h> 23 23 24 24 - #define DRV_NAME "ad2s1200" 25 24 26 25 /* input clock on serial interface */ 27 26 #define AD2S1200_HZ 8192000 ··· 191 192 192 193 static struct spi_driver ad2s1200_driver = { 193 194 .driver = { 194 194 - .name = DRV_NAME, 195 195 + .name = "ad2s1200", 195 196 .of_match_table = ad2s1200_of_match, 196 197 }, 197 198 .probe = ad2s1200_probe,

+1 -3

drivers/iio/temperature/tmp006.c

reviewed

··· 254 254 struct { 255 255 s16 channels[2]; 256 256 aligned_s64 ts; 257 257 - } scan; 257 257 + } scan = { }; 258 258 s32 ret; 259 259 - 260 260 - memset(&scan, 0, sizeof(scan)); 261 259 262 260 ret = i2c_smbus_read_word_data(data->client, TMP006_VOBJECT); 263 261 if (ret < 0)

+1

drivers/iio/trigger/stm32-lptimer-trigger.c

reviewed

··· 9 9 * Inspired by Benjamin Gaignard's stm32-timer-trigger driver 10 10 */ 11 11 12 12 + #include <linux/export.h> 12 13 #include <linux/iio/timer/stm32-lptim-trigger.h> 13 14 #include <linux/mfd/stm32-lptimer.h> 14 15 #include <linux/mod_devicetable.h>

+1

drivers/iio/trigger/stm32-timer-trigger.c

reviewed

··· 6 6 * 7 7 */ 8 8 9 9 + #include <linux/export.h> 9 10 #include <linux/iio/iio.h> 10 11 #include <linux/iio/sysfs.h> 11 12 #include <linux/iio/timer/stm32-timer-trigger.h>

+10

include/dt-bindings/iio/adc/adi,ad7768-1.h

reviewed

··· 1 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 2 + 3 3 + #ifndef _DT_BINDINGS_ADI_AD7768_1_H 4 4 + #define _DT_BINDINGS_ADI_AD7768_1_H 5 5 + 6 6 + #define AD7768_TRIGGER_SOURCE_SYNC_OUT 0 7 7 + #define AD7768_TRIGGER_SOURCE_GPIO3 1 8 8 + #define AD7768_TRIGGER_SOURCE_DRDY 2 9 9 + 10 10 + #endif /* _DT_BINDINGS_ADI_AD7768_1_H */

+24

include/dt-bindings/iio/adc/mediatek,mt6363-auxadc.h

reviewed

··· 1 1 + /* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ 2 2 + 3 3 + #ifndef _DT_BINDINGS_MEDIATEK_MT6363_AUXADC_H 4 4 + #define _DT_BINDINGS_MEDIATEK_MT6363_AUXADC_H 5 5 + 6 6 + /* ADC Channel Index */ 7 7 + #define MT6363_AUXADC_BATADC 0 8 8 + #define MT6363_AUXADC_VCDT 1 9 9 + #define MT6363_AUXADC_BAT_TEMP 2 10 10 + #define MT6363_AUXADC_CHIP_TEMP 3 11 11 + #define MT6363_AUXADC_VSYSSNS 4 12 12 + #define MT6363_AUXADC_VTREF 5 13 13 + #define MT6363_AUXADC_VCORE_TEMP 6 14 14 + #define MT6363_AUXADC_VPROC_TEMP 7 15 15 + #define MT6363_AUXADC_VGPU_TEMP 8 16 16 + #define MT6363_AUXADC_VIN1 9 17 17 + #define MT6363_AUXADC_VIN2 10 18 18 + #define MT6363_AUXADC_VIN3 11 19 19 + #define MT6363_AUXADC_VIN4 12 20 20 + #define MT6363_AUXADC_VIN5 13 21 21 + #define MT6363_AUXADC_VIN6 14 22 22 + #define MT6363_AUXADC_VIN7 15 23 23 + 24 24 + #endif

+19

include/dt-bindings/iio/adc/mediatek,mt6373-auxadc.h

reviewed

··· 1 1 + /* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ 2 2 + 3 3 + #ifndef _DT_BINDINGS_MEDIATEK_MT6373_AUXADC_H 4 4 + #define _DT_BINDINGS_MEDIATEK_MT6373_AUXADC_H 5 5 + 6 6 + /* ADC Channel Index */ 7 7 + #define MT6373_AUXADC_CHIP_TEMP 0 8 8 + #define MT6373_AUXADC_VCORE_TEMP 1 9 9 + #define MT6373_AUXADC_VPROC_TEMP 2 10 10 + #define MT6373_AUXADC_VGPU_TEMP 3 11 11 + #define MT6373_AUXADC_VIN1 4 12 12 + #define MT6373_AUXADC_VIN2 5 13 13 + #define MT6373_AUXADC_VIN3 6 14 14 + #define MT6373_AUXADC_VIN4 7 15 15 + #define MT6373_AUXADC_VIN5 8 16 16 + #define MT6373_AUXADC_VIN6 9 17 17 + #define MT6373_AUXADC_VIN7 10 18 18 + 19 19 + #endif

+22 -5

include/linux/iio/adc/ad_sigma_delta.h

reviewed

··· 31 31 struct device; 32 32 struct gpio_desc; 33 33 struct iio_dev; 34 34 + struct spi_offload; 35 35 + struct spi_offload_trigger; 34 36 35 37 /** 36 38 * struct ad_sigma_delta_info - Sigma Delta driver specific callbacks and options ··· 49 47 * @has_registers: true if the device has writable and readable registers, false 50 48 * if there is just one read-only sample data shift register. 51 49 * @has_named_irqs: Set to true if there is more than one IRQ line. 50 50 + * @supports_spi_offload: Set to true if the driver supports SPI offload. Often 51 51 + * special considerations are needed for scan_type and other channel 52 52 + * info, so individual drivers have to set this to let the core 53 53 + * code know that it can use SPI offload if it is available. 52 54 * @addr_shift: Shift of the register address in the communications register. 53 55 * @read_mask: Mask for the communications register having the read bit set. 54 56 * @status_ch_mask: Mask for the channel number stored in status register. ··· 71 65 int (*postprocess_sample)(struct ad_sigma_delta *, unsigned int raw_sample); 72 66 bool has_registers; 73 67 bool has_named_irqs; 68 68 + bool supports_spi_offload; 74 69 unsigned int addr_shift; 75 70 unsigned int read_mask; 76 71 unsigned int status_ch_mask; ··· 101 94 bool bus_locked; 102 95 bool keep_cs_asserted; 103 96 104 104 - uint8_t comm; 97 97 + u8 comm; 105 98 106 99 const struct ad_sigma_delta_info *info; 107 100 unsigned int active_slots; ··· 112 105 bool status_appended; 113 106 /* map slots to channels in order to know what to expect from devices */ 114 107 unsigned int *slots; 115 115 - uint8_t *samples_buf; 108 108 + struct spi_message sample_msg; 109 109 + struct spi_transfer sample_xfer[2]; 110 110 + u8 *samples_buf; 111 111 + struct spi_offload *offload; 112 112 + struct spi_offload_trigger *offload_trigger; 116 113 117 114 /* 118 115 * DMA (thus cache coherency maintenance) requires the ··· 125 114 * 'rx_buf' is up to 32 bits per sample + 64 bit timestamp, 126 115 * rounded to 16 bytes to take into account padding. 127 116 */ 128 128 - uint8_t tx_buf[4] __aligned(IIO_DMA_MINALIGN); 129 129 - uint8_t rx_buf[16] __aligned(8); 117 117 + u8 tx_buf[4] __aligned(IIO_DMA_MINALIGN); 118 118 + u8 rx_buf[16] __aligned(8); 119 119 + u8 sample_addr; 130 120 }; 121 121 + 122 122 + static inline bool ad_sigma_delta_has_spi_offload(struct ad_sigma_delta *sd) 123 123 + { 124 124 + return sd->offload != NULL; 125 125 + } 131 126 132 127 static inline int ad_sigma_delta_set_channel(struct ad_sigma_delta *sd, 133 128 unsigned int channel) ··· 194 177 return 0; 195 178 } 196 179 197 197 - void ad_sd_set_comm(struct ad_sigma_delta *sigma_delta, uint8_t comm); 180 180 + void ad_sd_set_comm(struct ad_sigma_delta *sigma_delta, u8 comm); 198 181 int ad_sd_write_reg(struct ad_sigma_delta *sigma_delta, unsigned int reg, 199 182 unsigned int size, unsigned int val); 200 183 int ad_sd_read_reg(struct ad_sigma_delta *sigma_delta, unsigned int reg,

+21 -1

include/linux/iio/backend.h

reviewed

··· 76 76 IIO_BACKEND_INTERFACE_MAX 77 77 }; 78 78 79 79 + enum iio_backend_filter_type { 80 80 + IIO_BACKEND_FILTER_TYPE_DISABLED, 81 81 + IIO_BACKEND_FILTER_TYPE_SINC1, 82 82 + IIO_BACKEND_FILTER_TYPE_SINC5, 83 83 + IIO_BACKEND_FILTER_TYPE_SINC5_PLUS_COMP, 84 84 + IIO_BACKEND_FILTER_TYPE_MAX 85 85 + }; 86 86 + 79 87 /** 80 88 * struct iio_backend_ops - operations structure for an iio_backend 81 89 * @enable: Enable backend. ··· 109 101 * @read_raw: Read a channel attribute from a backend device 110 102 * @debugfs_print_chan_status: Print channel status into a buffer. 111 103 * @debugfs_reg_access: Read or write register value of backend. 104 104 + * @filter_type_set: Set filter type. 105 105 + * @interface_data_align: Perform the data alignment process. 106 106 + * @num_lanes_set: Set the number of lanes enabled. 112 107 * @ddr_enable: Enable interface DDR (Double Data Rate) mode. 113 108 * @ddr_disable: Disable interface DDR (Double Data Rate) mode. 114 109 * @data_stream_enable: Enable data stream. ··· 155 144 enum iio_backend_interface_type *type); 156 145 int (*data_size_set)(struct iio_backend *back, unsigned int size); 157 146 int (*oversampling_ratio_set)(struct iio_backend *back, 158 158 - unsigned int ratio); 147 147 + unsigned int chan, unsigned int ratio); 159 148 int (*read_raw)(struct iio_backend *back, 160 149 struct iio_chan_spec const *chan, int *val, int *val2, 161 150 long mask); ··· 164 153 size_t len); 165 154 int (*debugfs_reg_access)(struct iio_backend *back, unsigned int reg, 166 155 unsigned int writeval, unsigned int *readval); 156 156 + int (*filter_type_set)(struct iio_backend *back, 157 157 + enum iio_backend_filter_type type); 158 158 + int (*interface_data_align)(struct iio_backend *back, u32 timeout_us); 159 159 + int (*num_lanes_set)(struct iio_backend *back, unsigned int num_lanes); 167 160 int (*ddr_enable)(struct iio_backend *back); 168 161 int (*ddr_disable)(struct iio_backend *back); 169 162 int (*data_stream_enable)(struct iio_backend *back); ··· 210 195 int devm_iio_backend_request_buffer(struct device *dev, 211 196 struct iio_backend *back, 212 197 struct iio_dev *indio_dev); 198 198 + int iio_backend_filter_type_set(struct iio_backend *back, 199 199 + enum iio_backend_filter_type type); 200 200 + int iio_backend_interface_data_align(struct iio_backend *back, u32 timeout_us); 201 201 + int iio_backend_num_lanes_set(struct iio_backend *back, unsigned int num_lanes); 213 202 int iio_backend_ddr_enable(struct iio_backend *back); 214 203 int iio_backend_ddr_disable(struct iio_backend *back); 215 204 int iio_backend_data_stream_enable(struct iio_backend *back); ··· 228 209 enum iio_backend_interface_type *type); 229 210 int iio_backend_data_size_set(struct iio_backend *back, unsigned int size); 230 211 int iio_backend_oversampling_ratio_set(struct iio_backend *back, 212 212 + unsigned int chan, 231 213 unsigned int ratio); 232 214 int iio_backend_read_raw(struct iio_backend *back, 233 215 struct iio_chan_spec const *chan, int *val, int *val2,

+1

include/linux/iio/common/cros_ec_sensors_core.h

reviewed

··· 126 126 127 127 /* List of extended channel specification for all sensors. */ 128 128 extern const struct iio_chan_spec_ext_info cros_ec_sensors_ext_info[]; 129 129 + extern const struct iio_chan_spec_ext_info cros_ec_sensors_limited_info[]; 129 130 130 131 #endif /* __CROS_EC_SENSORS_CORE_H */

+1

include/linux/iio/types.h

reviewed

··· 69 69 IIO_CHAN_INFO_CALIBAMBIENT, 70 70 IIO_CHAN_INFO_ZEROPOINT, 71 71 IIO_CHAN_INFO_TROUGH, 72 72 + IIO_CHAN_INFO_CONVDELAY, 72 73 }; 73 74 74 75 #endif /* _IIO_TYPES_H_ */

+24 -2

include/linux/platform_data/cros_ec_commands.h

reviewed

··· 2388 2388 */ 2389 2389 MOTIONSENSE_CMD_SENSOR_SCALE = 18, 2390 2390 2391 2391 + /* 2392 2392 + * Activity management 2393 2393 + * Retrieve current status of given activity. 2394 2394 + */ 2395 2395 + MOTIONSENSE_CMD_GET_ACTIVITY = 20, 2396 2396 + 2391 2397 /* Number of motionsense sub-commands. */ 2392 2398 MOTIONSENSE_NUM_CMDS 2393 2399 }; ··· 2453 2447 MOTIONSENSE_ORIENTATION_UNKNOWN = 4, 2454 2448 }; 2455 2449 2450 2450 + struct ec_response_activity_data { 2451 2451 + uint8_t activity; /* motionsensor_activity */ 2452 2452 + uint8_t state; 2453 2453 + } __ec_todo_packed; 2454 2454 + 2456 2455 struct ec_response_motion_sensor_data { 2457 2456 /* Flags for each sensor. */ 2458 2457 uint8_t flags; ··· 2471 2460 uint32_t timestamp; 2472 2461 }; 2473 2462 struct __ec_todo_unpacked { 2474 2474 - uint8_t activity; /* motionsensor_activity */ 2475 2475 - uint8_t state; 2463 2463 + struct ec_response_activity_data activity_data; 2476 2464 int16_t add_info[2]; 2477 2465 }; 2478 2466 }; ··· 2504 2494 MOTIONSENSE_ACTIVITY_SIG_MOTION = 1, 2505 2495 MOTIONSENSE_ACTIVITY_DOUBLE_TAP = 2, 2506 2496 MOTIONSENSE_ACTIVITY_ORIENTATION = 3, 2497 2497 + MOTIONSENSE_ACTIVITY_BODY_DETECTION = 4, 2507 2498 }; 2508 2499 2509 2500 struct ec_motion_sense_activity { ··· 2682 2671 uint32_t max_data_vector; 2683 2672 } fifo_read; 2684 2673 2674 2674 + /* Used for MOTIONSENSE_CMD_SET_ACTIVITY */ 2685 2675 struct ec_motion_sense_activity set_activity; 2686 2676 2687 2677 /* Used for MOTIONSENSE_CMD_LID_ANGLE */ ··· 2728 2716 */ 2729 2717 int16_t hys_degree; 2730 2718 } tablet_mode_threshold; 2719 2719 + 2720 2720 + /* Used for MOTIONSENSE_CMD_GET_ACTIVITY */ 2721 2721 + struct __ec_todo_unpacked { 2722 2722 + uint8_t sensor_num; 2723 2723 + uint8_t activity; /* enum motionsensor_activity */ 2724 2724 + } get_activity; 2731 2725 }; 2732 2726 } __ec_todo_packed; 2733 2727 ··· 2851 2833 uint16_t hys_degree; 2852 2834 } tablet_mode_threshold; 2853 2835 2836 2836 + /* USED for MOTIONSENSE_CMD_GET_ACTIVITY. */ 2837 2837 + struct __ec_todo_unpacked { 2838 2838 + uint8_t state; 2839 2839 + } get_activity; 2854 2840 }; 2855 2841 } __ec_todo_packed; 2856 2842