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linux
phy: qcom-qmp-ufs: Remove _tbl suffix from qmp_phy_init_tbl definitions
Following the other QMP PHY drivers like PCIe, let's remove the "_tbl"
suffix from the qmp_phy_init_tbl definitions. This helps in maintaining
the uniformity across all of the QMP PHY drivers.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20230114071009.88102-2-manivannan.sadhasivam@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
Manivannan Sadhasivam
and committed by
Vinod Koul
342ab21d
43108bb2
+73
-73
+73
-73
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+73
-73
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
···
99
99
[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_UFS_POWER_DOWN_CONTROL,
100
100
};
101
101
102
-
static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
102
+
static const struct qmp_phy_init_tbl msm8996_ufs_serdes[] = {
103
103
QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
104
104
QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
105
105
QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
···
148
148
QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
149
149
};
150
150
151
-
static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = {
151
+
static const struct qmp_phy_init_tbl msm8996_ufs_tx[] = {
152
152
QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
153
153
QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
154
154
};
155
155
156
-
static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = {
156
+
static const struct qmp_phy_init_tbl msm8996_ufs_rx[] = {
157
157
QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
158
158
QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
159
159
QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
···
167
167
QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
168
168
};
169
169
170
-
static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = {
170
+
static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes[] = {
171
171
QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
172
172
QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
173
173
QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
···
223
223
QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44),
224
224
};
225
225
226
-
static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] = {
226
+
static const struct qmp_phy_init_tbl sm6115_ufsphy_tx[] = {
227
227
QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
228
228
QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
229
229
};
230
230
231
-
static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = {
231
+
static const struct qmp_phy_init_tbl sm6115_ufsphy_rx[] = {
232
232
QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
233
233
QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F),
234
234
QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40),
···
246
246
QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B),
247
247
};
248
248
249
-
static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = {
249
+
static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs[] = {
250
250
QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_PWM_GEAR_BAND, 0x15),
251
251
QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
252
252
QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
···
258
258
QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
259
259
};
260
260
261
-
static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
261
+
static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes[] = {
262
262
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
263
263
QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
264
264
QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
···
300
300
QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
301
301
};
302
302
303
-
static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
303
+
static const struct qmp_phy_init_tbl sdm845_ufsphy_tx[] = {
304
304
QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
305
305
QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
306
306
QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
307
307
};
308
308
309
-
static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
309
+
static const struct qmp_phy_init_tbl sdm845_ufsphy_rx[] = {
310
310
QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
311
311
QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
312
312
QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
···
325
325
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
326
326
};
327
327
328
-
static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
328
+
static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs[] = {
329
329
QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2, 0x6e),
330
330
QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
331
331
QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
···
336
336
QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
337
337
};
338
338
339
-
static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
339
+
static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes[] = {
340
340
QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
341
341
QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
342
342
QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
···
366
366
QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
367
367
};
368
368
369
-
static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = {
369
+
static const struct qmp_phy_init_tbl sm8150_ufsphy_tx[] = {
370
370
QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
371
371
QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
372
372
QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
···
375
375
QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
376
376
};
377
377
378
-
static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = {
378
+
static const struct qmp_phy_init_tbl sm8150_ufsphy_rx[] = {
379
379
QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
380
380
QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
381
381
QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
···
413
413
414
414
};
415
415
416
-
static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = {
416
+
static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs[] = {
417
417
QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
418
418
QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
419
419
QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
···
423
423
QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
424
424
};
425
425
426
-
static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = {
426
+
static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes[] = {
427
427
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
428
428
QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
429
429
QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
···
453
453
QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
454
454
};
455
455
456
-
static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = {
456
+
static const struct qmp_phy_init_tbl sm8350_ufsphy_tx[] = {
457
457
QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
458
458
QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
459
459
QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
···
465
465
QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),
466
466
};
467
467
468
-
static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = {
468
+
static const struct qmp_phy_init_tbl sm8350_ufsphy_rx[] = {
469
469
QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),
470
470
QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),
471
471
QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
···
505
505
QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
506
506
};
507
507
508
-
static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = {
508
+
static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs[] = {
509
509
QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
510
510
QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
511
511
QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
···
637
637
static const struct qmp_phy_cfg msm8996_ufs_cfg = {
638
638
.lanes = 1,
639
639
640
-
.serdes_tbl = msm8996_ufs_serdes_tbl,
641
-
.serdes_tbl_num = ARRAY_SIZE(msm8996_ufs_serdes_tbl),
642
-
.tx_tbl = msm8996_ufs_tx_tbl,
643
-
.tx_tbl_num = ARRAY_SIZE(msm8996_ufs_tx_tbl),
644
-
.rx_tbl = msm8996_ufs_rx_tbl,
645
-
.rx_tbl_num = ARRAY_SIZE(msm8996_ufs_rx_tbl),
640
+
.serdes_tbl = msm8996_ufs_serdes,
641
+
.serdes_tbl_num = ARRAY_SIZE(msm8996_ufs_serdes),
642
+
.tx_tbl = msm8996_ufs_tx,
643
+
.tx_tbl_num = ARRAY_SIZE(msm8996_ufs_tx),
644
+
.rx_tbl = msm8996_ufs_rx,
645
+
.rx_tbl_num = ARRAY_SIZE(msm8996_ufs_rx),
646
646
647
647
.clk_list = msm8996_ufs_phy_clk_l,
648
648
.num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
···
660
660
661
661
.offsets = &qmp_ufs_offsets_v5,
662
662
663
-
.serdes_tbl = sm8350_ufsphy_serdes_tbl,
664
-
.serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
665
-
.tx_tbl = sm8350_ufsphy_tx_tbl,
666
-
.tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
667
-
.rx_tbl = sm8350_ufsphy_rx_tbl,
668
-
.rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
669
-
.pcs_tbl = sm8350_ufsphy_pcs_tbl,
670
-
.pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
663
+
.serdes_tbl = sm8350_ufsphy_serdes,
664
+
.serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
665
+
.tx_tbl = sm8350_ufsphy_tx,
666
+
.tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx),
667
+
.rx_tbl = sm8350_ufsphy_rx,
668
+
.rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx),
669
+
.pcs_tbl = sm8350_ufsphy_pcs,
670
+
.pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs),
671
671
.clk_list = sdm845_ufs_phy_clk_l,
672
672
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
673
673
.vreg_list = qmp_phy_vreg_l,
···
678
678
static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
679
679
.lanes = 2,
680
680
681
-
.serdes_tbl = sdm845_ufsphy_serdes_tbl,
682
-
.serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
683
-
.tx_tbl = sdm845_ufsphy_tx_tbl,
684
-
.tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
685
-
.rx_tbl = sdm845_ufsphy_rx_tbl,
686
-
.rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
687
-
.pcs_tbl = sdm845_ufsphy_pcs_tbl,
688
-
.pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
681
+
.serdes_tbl = sdm845_ufsphy_serdes,
682
+
.serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes),
683
+
.tx_tbl = sdm845_ufsphy_tx,
684
+
.tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx),
685
+
.rx_tbl = sdm845_ufsphy_rx,
686
+
.rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx),
687
+
.pcs_tbl = sdm845_ufsphy_pcs,
688
+
.pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs),
689
689
.clk_list = sdm845_ufs_phy_clk_l,
690
690
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
691
691
.vreg_list = qmp_phy_vreg_l,
···
700
700
701
701
.offsets = &qmp_ufs_offsets_v5,
702
702
703
-
.serdes_tbl = sm6115_ufsphy_serdes_tbl,
704
-
.serdes_tbl_num = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl),
705
-
.tx_tbl = sm6115_ufsphy_tx_tbl,
706
-
.tx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_tx_tbl),
707
-
.rx_tbl = sm6115_ufsphy_rx_tbl,
708
-
.rx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_rx_tbl),
709
-
.pcs_tbl = sm6115_ufsphy_pcs_tbl,
710
-
.pcs_tbl_num = ARRAY_SIZE(sm6115_ufsphy_pcs_tbl),
703
+
.serdes_tbl = sm6115_ufsphy_serdes,
704
+
.serdes_tbl_num = ARRAY_SIZE(sm6115_ufsphy_serdes),
705
+
.tx_tbl = sm6115_ufsphy_tx,
706
+
.tx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_tx),
707
+
.rx_tbl = sm6115_ufsphy_rx,
708
+
.rx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_rx),
709
+
.pcs_tbl = sm6115_ufsphy_pcs,
710
+
.pcs_tbl_num = ARRAY_SIZE(sm6115_ufsphy_pcs),
711
711
.clk_list = sdm845_ufs_phy_clk_l,
712
712
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
713
713
.vreg_list = qmp_phy_vreg_l,
···
720
720
static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
721
721
.lanes = 2,
722
722
723
-
.serdes_tbl = sm8150_ufsphy_serdes_tbl,
724
-
.serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl),
725
-
.tx_tbl = sm8150_ufsphy_tx_tbl,
726
-
.tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx_tbl),
727
-
.rx_tbl = sm8150_ufsphy_rx_tbl,
728
-
.rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx_tbl),
729
-
.pcs_tbl = sm8150_ufsphy_pcs_tbl,
730
-
.pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl),
723
+
.serdes_tbl = sm8150_ufsphy_serdes,
724
+
.serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes),
725
+
.tx_tbl = sm8150_ufsphy_tx,
726
+
.tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx),
727
+
.rx_tbl = sm8150_ufsphy_rx,
728
+
.rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx),
729
+
.pcs_tbl = sm8150_ufsphy_pcs,
730
+
.pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs),
731
731
.clk_list = sdm845_ufs_phy_clk_l,
732
732
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
733
733
.vreg_list = qmp_phy_vreg_l,
···
738
738
static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
739
739
.lanes = 2,
740
740
741
-
.serdes_tbl = sm8350_ufsphy_serdes_tbl,
742
-
.serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
743
-
.tx_tbl = sm8350_ufsphy_tx_tbl,
744
-
.tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
745
-
.rx_tbl = sm8350_ufsphy_rx_tbl,
746
-
.rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
747
-
.pcs_tbl = sm8350_ufsphy_pcs_tbl,
748
-
.pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
741
+
.serdes_tbl = sm8350_ufsphy_serdes,
742
+
.serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
743
+
.tx_tbl = sm8350_ufsphy_tx,
744
+
.tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx),
745
+
.rx_tbl = sm8350_ufsphy_rx,
746
+
.rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx),
747
+
.pcs_tbl = sm8350_ufsphy_pcs,
748
+
.pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs),
749
749
.clk_list = sdm845_ufs_phy_clk_l,
750
750
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
751
751
.vreg_list = qmp_phy_vreg_l,
···
756
756
static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
757
757
.lanes = 2,
758
758
759
-
.serdes_tbl = sm8350_ufsphy_serdes_tbl,
760
-
.serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
761
-
.tx_tbl = sm8350_ufsphy_tx_tbl,
762
-
.tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
763
-
.rx_tbl = sm8350_ufsphy_rx_tbl,
764
-
.rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
765
-
.pcs_tbl = sm8350_ufsphy_pcs_tbl,
766
-
.pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
759
+
.serdes_tbl = sm8350_ufsphy_serdes,
760
+
.serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
761
+
.tx_tbl = sm8350_ufsphy_tx,
762
+
.tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx),
763
+
.rx_tbl = sm8350_ufsphy_rx,
764
+
.rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx),
765
+
.pcs_tbl = sm8350_ufsphy_pcs,
766
+
.pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs),
767
767
.clk_list = sm8450_ufs_phy_clk_l,
768
768
.num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
769
769
.vreg_list = qmp_phy_vreg_l,