Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'dmaengine-fix-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine
Pull dmaengine fixes from Vinod Koul:
"Driver fixes for:
- stm32 dma residue calculation and chaining
- stm32 mdma for setting inflight bytes, residue calculation and
resume abort
- channel request, channel enable and dma error in fsl_edma
- runtime pm imbalance in ste_dma40 driver
- deadlock fix in mediatek driver"
* tag 'dmaengine-fix-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine:
dmaengine: fsl-edma: fix all channels requested when call fsl_edma3_xlate()
dmaengine: stm32-dma: fix residue in case of MDMA chaining
dmaengine: stm32-dma: fix stm32_dma_prep_slave_sg in case of MDMA chaining
dmaengine: stm32-mdma: set in_flight_bytes in case CRQA flag is set
dmaengine: stm32-mdma: use Link Address Register to compute residue
dmaengine: stm32-mdma: abort resume if no ongoing transfer
dmaengine: ste_dma40: Fix PM disable depth imbalance in d40_probe
dmaengine: mediatek: Fix deadlock caused by synchronize_irq()
dmaengine: idxd: use spin_lock_irqsave before wait_event_lock_irq
dmaengine: fsl-edma: fix edma4 channel enable failure on second attempt
dt-bindings: dmaengine: zynqmp_dma: add xlnx,bus-width required property
dmaengine: fsl-dma: fix DMA error when enabling sg if 'DONE' bit is set
+79
-24
+3
Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml
+3
Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml
···
13
13
14
14
maintainers:
15
15
- Michael Tretter <m.tretter@pengutronix.de>
16
+
- Harini Katakam <harini.katakam@amd.com>
17
+
- Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
16
18
17
19
allOf:
18
20
- $ref: ../dma-controller.yaml#
···
67
65
- interrupts
68
66
- clocks
69
67
- clock-names
68
+
- xlnx,bus-width
70
69
71
70
additionalProperties: false
72
71
+22
-3
drivers/dma/fsl-edma-common.c
+22
-3
drivers/dma/fsl-edma-common.c
···
92
92
93
93
edma_writel_chreg(fsl_chan, val, ch_sbr);
94
94
95
-
if (flags & FSL_EDMA_DRV_HAS_CHMUX)
96
-
edma_writel_chreg(fsl_chan, fsl_chan->srcid, ch_mux);
95
+
if (flags & FSL_EDMA_DRV_HAS_CHMUX) {
96
+
/*
97
+
* ch_mux: With the exception of 0, attempts to write a value
98
+
* already in use will be forced to 0.
99
+
*/
100
+
if (!edma_readl_chreg(fsl_chan, ch_mux))
101
+
edma_writel_chreg(fsl_chan, fsl_chan->srcid, ch_mux);
102
+
}
97
103
98
104
val = edma_readl_chreg(fsl_chan, ch_csr);
99
105
val |= EDMA_V3_CH_CSR_ERQ;
···
454
448
455
449
edma_write_tcdreg(fsl_chan, tcd->dlast_sga, dlast_sga);
456
450
451
+
csr = le16_to_cpu(tcd->csr);
452
+
457
453
if (fsl_chan->is_sw) {
458
-
csr = le16_to_cpu(tcd->csr);
459
454
csr |= EDMA_TCD_CSR_START;
460
455
tcd->csr = cpu_to_le16(csr);
461
456
}
457
+
458
+
/*
459
+
* Must clear CHn_CSR[DONE] bit before enable TCDn_CSR[ESG] at EDMAv3
460
+
* eDMAv4 have not such requirement.
461
+
* Change MLINK need clear CHn_CSR[DONE] for both eDMAv3 and eDMAv4.
462
+
*/
463
+
if (((fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_CLEAR_DONE_E_SG) &&
464
+
(csr & EDMA_TCD_CSR_E_SG)) ||
465
+
((fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_CLEAR_DONE_E_LINK) &&
466
+
(csr & EDMA_TCD_CSR_E_LINK)))
467
+
edma_writel_chreg(fsl_chan, edma_readl_chreg(fsl_chan, ch_csr), ch_csr);
468
+
462
469
463
470
edma_write_tcdreg(fsl_chan, tcd->csr, csr);
464
471
}
+13
-1
drivers/dma/fsl-edma-common.h
+13
-1
drivers/dma/fsl-edma-common.h
···
183
183
#define FSL_EDMA_DRV_BUS_8BYTE BIT(10)
184
184
#define FSL_EDMA_DRV_DEV_TO_DEV BIT(11)
185
185
#define FSL_EDMA_DRV_ALIGN_64BYTE BIT(12)
186
+
/* Need clean CHn_CSR DONE before enable TCD's ESG */
187
+
#define FSL_EDMA_DRV_CLEAR_DONE_E_SG BIT(13)
188
+
/* Need clean CHn_CSR DONE before enable TCD's MAJORELINK */
189
+
#define FSL_EDMA_DRV_CLEAR_DONE_E_LINK BIT(14)
186
190
187
191
#define FSL_EDMA_DRV_EDMA3 (FSL_EDMA_DRV_SPLIT_REG | \
188
192
FSL_EDMA_DRV_BUS_8BYTE | \
189
193
FSL_EDMA_DRV_DEV_TO_DEV | \
190
-
FSL_EDMA_DRV_ALIGN_64BYTE)
194
+
FSL_EDMA_DRV_ALIGN_64BYTE | \
195
+
FSL_EDMA_DRV_CLEAR_DONE_E_SG | \
196
+
FSL_EDMA_DRV_CLEAR_DONE_E_LINK)
197
+
198
+
#define FSL_EDMA_DRV_EDMA4 (FSL_EDMA_DRV_SPLIT_REG | \
199
+
FSL_EDMA_DRV_BUS_8BYTE | \
200
+
FSL_EDMA_DRV_DEV_TO_DEV | \
201
+
FSL_EDMA_DRV_ALIGN_64BYTE | \
202
+
FSL_EDMA_DRV_CLEAR_DONE_E_LINK)
191
203
192
204
struct fsl_edma_drvdata {
193
205
u32 dmamuxs; /* only used before v3 */
+5
-3
drivers/dma/fsl-edma-main.c
+5
-3
drivers/dma/fsl-edma-main.c
···
154
154
fsl_chan = to_fsl_edma_chan(chan);
155
155
i = fsl_chan - fsl_edma->chans;
156
156
157
-
chan = dma_get_slave_channel(chan);
158
-
chan->device->privatecnt++;
159
157
fsl_chan->priority = dma_spec->args[1];
160
158
fsl_chan->is_rxchan = dma_spec->args[2] & ARGS_RX;
161
159
fsl_chan->is_remote = dma_spec->args[2] & ARGS_REMOTE;
162
160
fsl_chan->is_multi_fifo = dma_spec->args[2] & ARGS_MULTI_FIFO;
163
161
164
162
if (!b_chmux && i == dma_spec->args[0]) {
163
+
chan = dma_get_slave_channel(chan);
164
+
chan->device->privatecnt++;
165
165
mutex_unlock(&fsl_edma->fsl_edma_mutex);
166
166
return chan;
167
167
} else if (b_chmux && !fsl_chan->srcid) {
168
168
/* if controller support channel mux, choose a free channel */
169
+
chan = dma_get_slave_channel(chan);
170
+
chan->device->privatecnt++;
169
171
fsl_chan->srcid = dma_spec->args[0];
170
172
mutex_unlock(&fsl_edma->fsl_edma_mutex);
171
173
return chan;
···
357
355
};
358
356
359
357
static struct fsl_edma_drvdata imx93_data4 = {
360
-
.flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_EDMA3,
358
+
.flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_EDMA4,
361
359
.chreg_space_sz = 0x8000,
362
360
.chreg_off = 0x10000,
363
361
.setup_irq = fsl_edma3_irq_init,
+3
-2
drivers/dma/idxd/device.c
+3
-2
drivers/dma/idxd/device.c
···
477
477
union idxd_command_reg cmd;
478
478
DECLARE_COMPLETION_ONSTACK(done);
479
479
u32 stat;
480
+
unsigned long flags;
480
481
481
482
if (idxd_device_is_halted(idxd)) {
482
483
dev_warn(&idxd->pdev->dev, "Device is HALTED!\n");
···
491
490
cmd.operand = operand;
492
491
cmd.int_req = 1;
493
492
494
-
spin_lock(&idxd->cmd_lock);
493
+
spin_lock_irqsave(&idxd->cmd_lock, flags);
495
494
wait_event_lock_irq(idxd->cmd_waitq,
496
495
!test_bit(IDXD_FLAG_CMD_RUNNING, &idxd->flags),
497
496
idxd->cmd_lock);
···
508
507
* After command submitted, release lock and go to sleep until
509
508
* the command completes via interrupt.
510
509
*/
511
-
spin_unlock(&idxd->cmd_lock);
510
+
spin_unlock_irqrestore(&idxd->cmd_lock, flags);
512
511
wait_for_completion(&done);
513
512
stat = ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET);
514
513
spin_lock(&idxd->cmd_lock);
+1
-2
drivers/dma/mediatek/mtk-uart-apdma.c
+1
-2
drivers/dma/mediatek/mtk-uart-apdma.c
+1
drivers/dma/ste_dma40.c
+1
drivers/dma/ste_dma40.c
+7
-4
drivers/dma/stm32-dma.c
+7
-4
drivers/dma/stm32-dma.c
···
1113
1113
chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_PFCTRL;
1114
1114
1115
1115
/* Activate Double Buffer Mode if DMA triggers STM32 MDMA and more than 1 sg */
1116
-
if (chan->trig_mdma && sg_len > 1)
1116
+
if (chan->trig_mdma && sg_len > 1) {
1117
1117
chan->chan_reg.dma_scr |= STM32_DMA_SCR_DBM;
1118
+
chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_CT;
1119
+
}
1118
1120
1119
1121
for_each_sg(sgl, sg, sg_len, i) {
1120
1122
ret = stm32_dma_set_xfer_param(chan, direction, &buswidth,
···
1389
1387
1390
1388
residue = stm32_dma_get_remaining_bytes(chan);
1391
1389
1392
-
if (chan->desc->cyclic && !stm32_dma_is_current_sg(chan)) {
1390
+
if ((chan->desc->cyclic || chan->trig_mdma) && !stm32_dma_is_current_sg(chan)) {
1393
1391
n_sg++;
1394
1392
if (n_sg == chan->desc->num_sgs)
1395
1393
n_sg = 0;
1396
-
residue = sg_req->len;
1394
+
if (!chan->trig_mdma)
1395
+
residue = sg_req->len;
1397
1396
}
1398
1397
1399
1398
/*
···
1404
1401
* residue = remaining bytes from NDTR + remaining
1405
1402
* periods/sg to be transferred
1406
1403
*/
1407
-
if (!chan->desc->cyclic || n_sg != 0)
1404
+
if ((!chan->desc->cyclic && !chan->trig_mdma) || n_sg != 0)
1408
1405
for (i = n_sg; i < desc->num_sgs; i++)
1409
1406
residue += desc->sg_req[i].len;
1410
1407
+24
-9
drivers/dma/stm32-mdma.c
+24
-9
drivers/dma/stm32-mdma.c
···
777
777
/* Enable interrupts */
778
778
ccr &= ~STM32_MDMA_CCR_IRQ_MASK;
779
779
ccr |= STM32_MDMA_CCR_TEIE | STM32_MDMA_CCR_CTCIE;
780
-
if (sg_len > 1)
781
-
ccr |= STM32_MDMA_CCR_BTIE;
782
780
desc->ccr = ccr;
783
781
784
782
return 0;
···
1234
1236
unsigned long flags;
1235
1237
u32 status, reg;
1236
1238
1239
+
/* Transfer can be terminated */
1240
+
if (!chan->desc || (stm32_mdma_read(dmadev, STM32_MDMA_CCR(chan->id)) & STM32_MDMA_CCR_EN))
1241
+
return -EPERM;
1242
+
1237
1243
hwdesc = chan->desc->node[chan->curr_hwdesc].hwdesc;
1238
1244
1239
1245
spin_lock_irqsave(&chan->vchan.lock, flags);
···
1318
1316
1319
1317
static size_t stm32_mdma_desc_residue(struct stm32_mdma_chan *chan,
1320
1318
struct stm32_mdma_desc *desc,
1321
-
u32 curr_hwdesc)
1319
+
u32 curr_hwdesc,
1320
+
struct dma_tx_state *state)
1322
1321
{
1323
1322
struct stm32_mdma_device *dmadev = stm32_mdma_get_dev(chan);
1324
1323
struct stm32_mdma_hwdesc *hwdesc;
1325
-
u32 cbndtr, residue, modulo, burst_size;
1324
+
u32 cisr, clar, cbndtr, residue, modulo, burst_size;
1326
1325
int i;
1327
1326
1327
+
cisr = stm32_mdma_read(dmadev, STM32_MDMA_CISR(chan->id));
1328
+
1328
1329
residue = 0;
1329
-
for (i = curr_hwdesc + 1; i < desc->count; i++) {
1330
+
/* Get the next hw descriptor to process from current transfer */
1331
+
clar = stm32_mdma_read(dmadev, STM32_MDMA_CLAR(chan->id));
1332
+
for (i = desc->count - 1; i >= 0; i--) {
1330
1333
hwdesc = desc->node[i].hwdesc;
1334
+
1335
+
if (hwdesc->clar == clar)
1336
+
break;/* Current transfer found, stop cumulating */
1337
+
1338
+
/* Cumulate residue of unprocessed hw descriptors */
1331
1339
residue += STM32_MDMA_CBNDTR_BNDT(hwdesc->cbndtr);
1332
1340
}
1333
1341
cbndtr = stm32_mdma_read(dmadev, STM32_MDMA_CBNDTR(chan->id));
1334
1342
residue += cbndtr & STM32_MDMA_CBNDTR_BNDT_MASK;
1343
+
1344
+
state->in_flight_bytes = 0;
1345
+
if (chan->chan_config.m2m_hw && (cisr & STM32_MDMA_CISR_CRQA))
1346
+
state->in_flight_bytes = cbndtr & STM32_MDMA_CBNDTR_BNDT_MASK;
1335
1347
1336
1348
if (!chan->mem_burst)
1337
1349
return residue;
···
1376
1360
1377
1361
vdesc = vchan_find_desc(&chan->vchan, cookie);
1378
1362
if (chan->desc && cookie == chan->desc->vdesc.tx.cookie)
1379
-
residue = stm32_mdma_desc_residue(chan, chan->desc,
1380
-
chan->curr_hwdesc);
1363
+
residue = stm32_mdma_desc_residue(chan, chan->desc, chan->curr_hwdesc, state);
1381
1364
else if (vdesc)
1382
-
residue = stm32_mdma_desc_residue(chan,
1383
-
to_stm32_mdma_desc(vdesc), 0);
1365
+
residue = stm32_mdma_desc_residue(chan, to_stm32_mdma_desc(vdesc), 0, state);
1366
+
1384
1367
dma_set_residue(state, residue);
1385
1368
1386
1369
spin_unlock_irqrestore(&chan->vchan.lock, flags);