tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'sound-5.9-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound

Pull sound fixes from Takashi Iwai:
"Here is a collection of fixes for 5.9. All look small and are nothing
scary.

The majority of changes are about ASoC driver- specific fixes, while
there are a couple of ASoC core fixes (DAI lookup and lockdep stuff)
and usual HD-audio quirks"

* tag 'sound-5.9-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound: (23 commits)
ALSA: hda/realtek - The Mic on a RedmiBook doesn't work
ASoC: tlv320adcx140: Wake up codec before accessing register
ASoC: core: Do not cleanup uninitialized dais on soc_pcm_open failure
ALSA: hda: fixup headset for ASUS GX502 laptop
ASoC: Intel: bytcr_rt5640: Add quirk for MPMAN Converter9 2-in-1
ASoC: Intel: haswell: Fix power transition refactor
ASoC: tlv320adcx140: Fix accessing uninitialized adcx140->dev
ASoC: wm8994: Ensure the device is resumed in wm89xx_mic_detect functions
ASoC: wm8994: Skip setting of the WM8994_MICBIAS register for WM1811
ASoC: meson: axg-toddr: fix channel order on g12 platforms
ASoC: soc-core: add snd_soc_find_dai_with_mutex()
ASoC: qcom: common: Fix refcount imbalance on error
ASoC: rt700: Fix return check for devm_regmap_init_sdw()
ASoC: rt715: Fix return check for devm_regmap_init_sdw()
ASoC: rt711: Fix return check for devm_regmap_init_sdw()
ASoC: rt1308-sdw: Fix return check for devm_regmap_init_sdw()
ASoC: max98373: Fix return check for devm_regmap_init_sdw()
ASoC: ti: fixup ams_delta_mute() function name
ASoC: pcm3168a: ignore 0 Hz settings
ASoC: Intel: tgl_max98373: fix a runtime pm issue in multi-thread case
...

Linus Torvalds 343b529a 1fd79656

+285 -140
+4
include/sound/soc.h
··· 1193 1193 ((i) < (rtd)->num_cpus + (rtd)->num_codecs) && \ 1194 1194 ((dai) = (rtd)->dais[i]); \ 1195 1195 (i)++) 1196 + #define for_each_rtd_dais_rollback(rtd, i, dai) \ 1197 + for (; (--(i) >= 0) && ((dai) = (rtd)->dais[i]);) 1196 1198 1197 1199 void snd_soc_close_delayed_work(struct snd_soc_pcm_runtime *rtd); 1198 1200 ··· 1362 1360 void snd_soc_unregister_dai(struct snd_soc_dai *dai); 1363 1361 1364 1362 struct snd_soc_dai *snd_soc_find_dai( 1363 + const struct snd_soc_dai_link_component *dlc); 1364 + struct snd_soc_dai *snd_soc_find_dai_with_mutex( 1365 1365 const struct snd_soc_dai_link_component *dlc); 1366 1366 1367 1367 #include <sound/soc-dai.h>
+78
sound/pci/hda/patch_realtek.c
··· 5993 5993 snd_hda_codec_set_pin_target(codec, 0x19, PIN_VREFHIZ); 5994 5994 } 5995 5995 5996 + 5997 + static void alc294_gx502_toggle_output(struct hda_codec *codec, 5998 + struct hda_jack_callback *cb) 5999 + { 6000 + /* The Windows driver sets the codec up in a very different way where 6001 + * it appears to leave 0x10 = 0x8a20 set. For Linux we need to toggle it 6002 + */ 6003 + if (snd_hda_jack_detect_state(codec, 0x21) == HDA_JACK_PRESENT) 6004 + alc_write_coef_idx(codec, 0x10, 0x8a20); 6005 + else 6006 + alc_write_coef_idx(codec, 0x10, 0x0a20); 6007 + } 6008 + 6009 + static void alc294_fixup_gx502_hp(struct hda_codec *codec, 6010 + const struct hda_fixup *fix, int action) 6011 + { 6012 + /* Pin 0x21: headphones/headset mic */ 6013 + if (!is_jack_detectable(codec, 0x21)) 6014 + return; 6015 + 6016 + switch (action) { 6017 + case HDA_FIXUP_ACT_PRE_PROBE: 6018 + snd_hda_jack_detect_enable_callback(codec, 0x21, 6019 + alc294_gx502_toggle_output); 6020 + break; 6021 + case HDA_FIXUP_ACT_INIT: 6022 + /* Make sure to start in a correct state, i.e. if 6023 + * headphones have been plugged in before powering up the system 6024 + */ 6025 + alc294_gx502_toggle_output(codec, NULL); 6026 + break; 6027 + } 6028 + } 6029 + 5996 6030 static void alc285_fixup_hp_gpio_amp_init(struct hda_codec *codec, 5997 6031 const struct hda_fixup *fix, int action) 5998 6032 { ··· 6207 6173 ALC285_FIXUP_THINKPAD_HEADSET_JACK, 6208 6174 ALC294_FIXUP_ASUS_HPE, 6209 6175 ALC294_FIXUP_ASUS_COEF_1B, 6176 + ALC294_FIXUP_ASUS_GX502_HP, 6177 + ALC294_FIXUP_ASUS_GX502_PINS, 6178 + ALC294_FIXUP_ASUS_GX502_VERBS, 6210 6179 ALC285_FIXUP_HP_GPIO_LED, 6211 6180 ALC285_FIXUP_HP_MUTE_LED, 6212 6181 ALC236_FIXUP_HP_MUTE_LED, ··· 6228 6191 ALC269_FIXUP_LEMOTE_A1802, 6229 6192 ALC269_FIXUP_LEMOTE_A190X, 6230 6193 ALC256_FIXUP_INTEL_NUC8_RUGGED, 6194 + ALC255_FIXUP_XIAOMI_HEADSET_MIC, 6231 6195 }; 6232 6196 6233 6197 static const struct hda_fixup alc269_fixups[] = { ··· 7376 7338 .chained = true, 7377 7339 .chain_id = ALC294_FIXUP_ASUS_HEADSET_MIC 7378 7340 }, 7341 + [ALC294_FIXUP_ASUS_GX502_PINS] = { 7342 + .type = HDA_FIXUP_PINS, 7343 + .v.pins = (const struct hda_pintbl[]) { 7344 + { 0x19, 0x03a11050 }, /* front HP mic */ 7345 + { 0x1a, 0x01a11830 }, /* rear external mic */ 7346 + { 0x21, 0x03211020 }, /* front HP out */ 7347 + { } 7348 + }, 7349 + .chained = true, 7350 + .chain_id = ALC294_FIXUP_ASUS_GX502_VERBS 7351 + }, 7352 + [ALC294_FIXUP_ASUS_GX502_VERBS] = { 7353 + .type = HDA_FIXUP_VERBS, 7354 + .v.verbs = (const struct hda_verb[]) { 7355 + /* set 0x15 to HP-OUT ctrl */ 7356 + { 0x15, AC_VERB_SET_PIN_WIDGET_CONTROL, 0xc0 }, 7357 + /* unmute the 0x15 amp */ 7358 + { 0x15, AC_VERB_SET_AMP_GAIN_MUTE, 0xb000 }, 7359 + { } 7360 + }, 7361 + .chained = true, 7362 + .chain_id = ALC294_FIXUP_ASUS_GX502_HP 7363 + }, 7364 + [ALC294_FIXUP_ASUS_GX502_HP] = { 7365 + .type = HDA_FIXUP_FUNC, 7366 + .v.func = alc294_fixup_gx502_hp, 7367 + }, 7379 7368 [ALC294_FIXUP_ASUS_COEF_1B] = { 7380 7369 .type = HDA_FIXUP_VERBS, 7381 7370 .v.verbs = (const struct hda_verb[]) { ··· 7592 7527 .chained = true, 7593 7528 .chain_id = ALC269_FIXUP_HEADSET_MODE 7594 7529 }, 7530 + [ALC255_FIXUP_XIAOMI_HEADSET_MIC] = { 7531 + .type = HDA_FIXUP_VERBS, 7532 + .v.verbs = (const struct hda_verb[]) { 7533 + { 0x20, AC_VERB_SET_COEF_INDEX, 0x45 }, 7534 + { 0x20, AC_VERB_SET_PROC_COEF, 0x5089 }, 7535 + { } 7536 + }, 7537 + .chained = true, 7538 + .chain_id = ALC289_FIXUP_ASUS_GA401 7539 + }, 7595 7540 }; 7596 7541 7597 7542 static const struct snd_pci_quirk alc269_fixup_tbl[] = { ··· 7786 7711 SND_PCI_QUIRK(0x1043, 0x1ccd, "ASUS X555UB", ALC256_FIXUP_ASUS_MIC), 7787 7712 SND_PCI_QUIRK(0x1043, 0x1e11, "ASUS Zephyrus G15", ALC289_FIXUP_ASUS_GA502), 7788 7713 SND_PCI_QUIRK(0x1043, 0x1f11, "ASUS Zephyrus G14", ALC289_FIXUP_ASUS_GA401), 7714 + SND_PCI_QUIRK(0x1043, 0x1881, "ASUS Zephyrus S/M", ALC294_FIXUP_ASUS_GX502_PINS), 7789 7715 SND_PCI_QUIRK(0x1043, 0x3030, "ASUS ZN270IE", ALC256_FIXUP_ASUS_AIO_GPIO2), 7790 7716 SND_PCI_QUIRK(0x1043, 0x831a, "ASUS P901", ALC269_FIXUP_STEREO_DMIC), 7791 7717 SND_PCI_QUIRK(0x1043, 0x834a, "ASUS S101", ALC269_FIXUP_STEREO_DMIC), ··· 7899 7823 SND_PCI_QUIRK(0x1b35, 0x1236, "CZC TMI", ALC269_FIXUP_CZC_TMI), 7900 7824 SND_PCI_QUIRK(0x1b35, 0x1237, "CZC L101", ALC269_FIXUP_CZC_L101), 7901 7825 SND_PCI_QUIRK(0x1b7d, 0xa831, "Ordissimo EVE2 ", ALC269VB_FIXUP_ORDISSIMO_EVE2), /* Also known as Malata PC-B1303 */ 7826 + SND_PCI_QUIRK(0x1d72, 0x1602, "RedmiBook", ALC255_FIXUP_XIAOMI_HEADSET_MIC), 7902 7827 SND_PCI_QUIRK(0x1d72, 0x1901, "RedmiBook 14", ALC256_FIXUP_ASUS_HEADSET_MIC), 7903 7828 SND_PCI_QUIRK(0x10ec, 0x118c, "Medion EE4254 MD62100", ALC256_FIXUP_MEDION_HEADSET_NO_PRESENCE), 7904 7829 SND_PCI_QUIRK(0x1c06, 0x2013, "Lemote A1802", ALC269_FIXUP_LEMOTE_A1802), ··· 8077 8000 {.id = ALC298_FIXUP_HUAWEI_MBX_STEREO, .name = "huawei-mbx-stereo"}, 8078 8001 {.id = ALC256_FIXUP_MEDION_HEADSET_NO_PRESENCE, .name = "alc256-medion-headset"}, 8079 8002 {.id = ALC298_FIXUP_SAMSUNG_HEADPHONE_VERY_QUIET, .name = "alc298-samsung-headphone"}, 8003 + {.id = ALC255_FIXUP_XIAOMI_HEADSET_MIC, .name = "alc255-xiaomi-headset"}, 8080 8004 {} 8081 8005 }; 8082 8006 #define ALC225_STANDARD_PINS \
+2 -2
sound/soc/codecs/max98373-sdw.c
··· 838 838 839 839 /* Regmap Initialization */ 840 840 regmap = devm_regmap_init_sdw(slave, &max98373_sdw_regmap); 841 - if (!regmap) 842 - return -EINVAL; 841 + if (IS_ERR(regmap)) 842 + return PTR_ERR(regmap); 843 843 844 844 return max98373_init(slave, regmap); 845 845 }
+7
sound/soc/codecs/pcm3168a.c
··· 306 306 struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(dai->component); 307 307 int ret; 308 308 309 + /* 310 + * Some sound card sets 0 Hz as reset, 311 + * but it is impossible to set. Ignore it here 312 + */ 313 + if (freq == 0) 314 + return 0; 315 + 309 316 if (freq > PCM3168A_MAX_SYSCLK) 310 317 return -EINVAL; 311 318
+2 -2
sound/soc/codecs/rt1308-sdw.c
··· 684 684 685 685 /* Regmap Initialization */ 686 686 regmap = devm_regmap_init_sdw(slave, &rt1308_sdw_regmap); 687 - if (!regmap) 688 - return -EINVAL; 687 + if (IS_ERR(regmap)) 688 + return PTR_ERR(regmap); 689 689 690 690 rt1308_sdw_init(&slave->dev, regmap, slave); 691 691
+2 -2
sound/soc/codecs/rt700-sdw.c
··· 452 452 453 453 /* Regmap Initialization */ 454 454 sdw_regmap = devm_regmap_init_sdw(slave, &rt700_sdw_regmap); 455 - if (!sdw_regmap) 456 - return -EINVAL; 455 + if (IS_ERR(sdw_regmap)) 456 + return PTR_ERR(sdw_regmap); 457 457 458 458 regmap = devm_regmap_init(&slave->dev, NULL, 459 459 &slave->dev, &rt700_regmap);
+2 -2
sound/soc/codecs/rt711-sdw.c
··· 452 452 453 453 /* Regmap Initialization */ 454 454 sdw_regmap = devm_regmap_init_sdw(slave, &rt711_sdw_regmap); 455 - if (!sdw_regmap) 456 - return -EINVAL; 455 + if (IS_ERR(sdw_regmap)) 456 + return PTR_ERR(sdw_regmap); 457 457 458 458 regmap = devm_regmap_init(&slave->dev, NULL, 459 459 &slave->dev, &rt711_regmap);
+2 -2
sound/soc/codecs/rt715-sdw.c
··· 527 527 528 528 /* Regmap Initialization */ 529 529 sdw_regmap = devm_regmap_init_sdw(slave, &rt715_sdw_regmap); 530 - if (!sdw_regmap) 531 - return -EINVAL; 530 + if (IS_ERR(sdw_regmap)) 531 + return PTR_ERR(sdw_regmap); 532 532 533 533 regmap = devm_regmap_init(&slave->dev, NULL, &slave->dev, 534 534 &rt715_regmap);
+15 -13
sound/soc/codecs/tlv320adcx140.c
··· 842 842 if (ret) 843 843 goto out; 844 844 845 + if (adcx140->supply_areg == NULL) 846 + sleep_cfg_val |= ADCX140_AREG_INTERNAL; 847 + 848 + ret = regmap_write(adcx140->regmap, ADCX140_SLEEP_CFG, sleep_cfg_val); 849 + if (ret) { 850 + dev_err(adcx140->dev, "setting sleep config failed %d\n", ret); 851 + goto out; 852 + } 853 + 854 + /* 8.4.3: Wait >= 1ms after entering active mode. */ 855 + usleep_range(1000, 100000); 856 + 845 857 pdm_count = device_property_count_u32(adcx140->dev, 846 858 "ti,pdm-edge-select"); 847 859 if (pdm_count <= ADCX140_NUM_PDM_EDGES && pdm_count > 0) { ··· 900 888 ret = adcx140_configure_gpo(adcx140); 901 889 if (ret) 902 890 goto out; 903 - 904 - if (adcx140->supply_areg == NULL) 905 - sleep_cfg_val |= ADCX140_AREG_INTERNAL; 906 - 907 - ret = regmap_write(adcx140->regmap, ADCX140_SLEEP_CFG, sleep_cfg_val); 908 - if (ret) { 909 - dev_err(adcx140->dev, "setting sleep config failed %d\n", ret); 910 - goto out; 911 - } 912 - 913 - /* 8.4.3: Wait >= 1ms after entering active mode. */ 914 - usleep_range(1000, 100000); 915 891 916 892 ret = regmap_update_bits(adcx140->regmap, ADCX140_BIAS_CFG, 917 893 ADCX140_MIC_BIAS_VAL_MSK | ··· 980 980 if (!adcx140) 981 981 return -ENOMEM; 982 982 983 + adcx140->dev = &i2c->dev; 984 + 983 985 adcx140->gpio_reset = devm_gpiod_get_optional(adcx140->dev, 984 986 "reset", GPIOD_OUT_LOW); 985 987 if (IS_ERR(adcx140->gpio_reset)) ··· 1009 1007 ret); 1010 1008 return ret; 1011 1009 } 1012 - adcx140->dev = &i2c->dev; 1010 + 1013 1011 i2c_set_clientdata(i2c, adcx140); 1014 1012 1015 1013 return devm_snd_soc_register_component(&i2c->dev,
+10
sound/soc/codecs/wm8994.c
··· 3514 3514 return -EINVAL; 3515 3515 } 3516 3516 3517 + pm_runtime_get_sync(component->dev); 3518 + 3517 3519 switch (micbias) { 3518 3520 case 1: 3519 3521 micdet = &wm8994->micdet[0]; ··· 3562 3560 WM8994_MIC1_DET_DB | WM8994_MIC1_SHRT_DB); 3563 3561 3564 3562 snd_soc_dapm_sync(dapm); 3563 + 3564 + pm_runtime_put(component->dev); 3565 3565 3566 3566 return 0; 3567 3567 } ··· 3936 3932 return -EINVAL; 3937 3933 } 3938 3934 3935 + pm_runtime_get_sync(component->dev); 3936 + 3939 3937 if (jack) { 3940 3938 snd_soc_dapm_force_enable_pin(dapm, "CLK_SYS"); 3941 3939 snd_soc_dapm_sync(dapm); ··· 4005 3999 snd_soc_dapm_disable_pin(dapm, "CLK_SYS"); 4006 4000 snd_soc_dapm_sync(dapm); 4007 4001 } 4002 + 4003 + pm_runtime_put(component->dev); 4008 4004 4009 4005 return 0; 4010 4006 } ··· 4201 4193 wm8994->hubs.dcs_readback_mode = 2; 4202 4194 break; 4203 4195 } 4196 + wm8994->hubs.micd_scthr = true; 4204 4197 break; 4205 4198 4206 4199 case WM8958: 4207 4200 wm8994->hubs.dcs_readback_mode = 1; 4208 4201 wm8994->hubs.hp_startup_mode = 1; 4202 + wm8994->hubs.micd_scthr = true; 4209 4203 4210 4204 switch (control->revision) { 4211 4205 case 0:
+3
sound/soc/codecs/wm_hubs.c
··· 1223 1223 snd_soc_component_update_bits(component, WM8993_ADDITIONAL_CONTROL, 1224 1224 WM8993_LINEOUT2_FB, WM8993_LINEOUT2_FB); 1225 1225 1226 + if (!hubs->micd_scthr) 1227 + return 0; 1228 + 1226 1229 snd_soc_component_update_bits(component, WM8993_MICBIAS, 1227 1230 WM8993_JD_SCTHR_MASK | WM8993_JD_THR_MASK | 1228 1231 WM8993_MICB1_LVL | WM8993_MICB2_LVL,
+1
sound/soc/codecs/wm_hubs.h
··· 27 27 int hp_startup_mode; 28 28 int series_startup; 29 29 int no_series_update; 30 + bool micd_scthr; 30 31 31 32 bool no_cache_dac_hp_direct; 32 33 struct list_head dcs_cache;
+11
sound/soc/intel/atom/sst-mfld-platform-pcm.c
··· 333 333 if (ret_val < 0) 334 334 goto out_power_up; 335 335 336 + /* 337 + * Make sure the period to be multiple of 1ms to align the 338 + * design of firmware. Apply same rule to buffer size to make 339 + * sure alsa could always find a value for period size 340 + * regardless the buffer size given by user space. 341 + */ 342 + snd_pcm_hw_constraint_step(substream->runtime, 0, 343 + SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 48); 344 + snd_pcm_hw_constraint_step(substream->runtime, 0, 345 + SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 48); 346 + 336 347 /* Make sure, that the period size is always even */ 337 348 snd_pcm_hw_constraint_step(substream->runtime, 0, 338 349 SNDRV_PCM_HW_PARAM_PERIODS, 2);
+10
sound/soc/intel/boards/bytcr_rt5640.c
··· 591 591 BYT_RT5640_SSP0_AIF1 | 592 592 BYT_RT5640_MCLK_EN), 593 593 }, 594 + { /* MPMAN Converter 9, similar hw as the I.T.Works TW891 2-in-1 */ 595 + .matches = { 596 + DMI_MATCH(DMI_SYS_VENDOR, "MPMAN"), 597 + DMI_MATCH(DMI_PRODUCT_NAME, "Converter9"), 598 + }, 599 + .driver_data = (void *)(BYTCR_INPUT_DEFAULTS | 600 + BYT_RT5640_MONO_SPEAKER | 601 + BYT_RT5640_SSP0_AIF1 | 602 + BYT_RT5640_MCLK_EN), 603 + }, 594 604 { 595 605 /* MPMAN MPWIN895CL */ 596 606 .matches = {
+1 -1
sound/soc/intel/boards/skl_hda_dsp_generic.c
··· 181 181 struct snd_soc_dai *dai; 182 182 183 183 for_each_card_rtds(card, rtd) { 184 - if (!strstr(rtd->dai_link->codecs->name, "ehdaudio")) 184 + if (!strstr(rtd->dai_link->codecs->name, "ehdaudio0D0")) 185 185 continue; 186 186 dai = asoc_rtd_to_codec(rtd, 0); 187 187 hda_pvt = snd_soc_component_get_drvdata(dai->component);
+4 -3
sound/soc/intel/boards/sof_maxim_common.c
··· 66 66 int j; 67 67 int ret = 0; 68 68 69 + /* set spk pin by playback only */ 70 + if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 71 + return 0; 72 + 69 73 for_each_rtd_codec_dais(rtd, j, codec_dai) { 70 74 struct snd_soc_component *component = codec_dai->component; 71 75 struct snd_soc_dapm_context *dapm = ··· 90 86 case SNDRV_PCM_TRIGGER_STOP: 91 87 case SNDRV_PCM_TRIGGER_SUSPEND: 92 88 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 93 - /* Make sure no streams are active before disable pin */ 94 - if (snd_soc_dai_active(codec_dai) != 1) 95 - break; 96 89 ret = snd_soc_dapm_disable_pin(dapm, pin_name); 97 90 if (!ret) 98 91 snd_soc_dapm_sync(dapm);
+82 -105
sound/soc/intel/haswell/sst-haswell-dsp.c
··· 243 243 return ret; 244 244 } 245 245 246 - #define CSR_DEFAULT_VALUE 0x8480040E 247 - #define ISC_DEFAULT_VALUE 0x0 248 - #define ISD_DEFAULT_VALUE 0x0 249 - #define IMC_DEFAULT_VALUE 0x7FFF0003 250 - #define IMD_DEFAULT_VALUE 0x7FFF0003 251 - #define IPCC_DEFAULT_VALUE 0x0 252 - #define IPCD_DEFAULT_VALUE 0x0 253 - #define CLKCTL_DEFAULT_VALUE 0x7FF 254 - #define CSR2_DEFAULT_VALUE 0x0 255 - #define LTR_CTRL_DEFAULT_VALUE 0x0 256 - #define HMD_CTRL_DEFAULT_VALUE 0x0 257 - 258 - static void hsw_set_shim_defaults(struct sst_dsp *sst) 259 - { 260 - sst_dsp_shim_write_unlocked(sst, SST_CSR, CSR_DEFAULT_VALUE); 261 - sst_dsp_shim_write_unlocked(sst, SST_ISRX, ISC_DEFAULT_VALUE); 262 - sst_dsp_shim_write_unlocked(sst, SST_ISRD, ISD_DEFAULT_VALUE); 263 - sst_dsp_shim_write_unlocked(sst, SST_IMRX, IMC_DEFAULT_VALUE); 264 - sst_dsp_shim_write_unlocked(sst, SST_IMRD, IMD_DEFAULT_VALUE); 265 - sst_dsp_shim_write_unlocked(sst, SST_IPCX, IPCC_DEFAULT_VALUE); 266 - sst_dsp_shim_write_unlocked(sst, SST_IPCD, IPCD_DEFAULT_VALUE); 267 - sst_dsp_shim_write_unlocked(sst, SST_CLKCTL, CLKCTL_DEFAULT_VALUE); 268 - sst_dsp_shim_write_unlocked(sst, SST_CSR2, CSR2_DEFAULT_VALUE); 269 - sst_dsp_shim_write_unlocked(sst, SST_LTRC, LTR_CTRL_DEFAULT_VALUE); 270 - sst_dsp_shim_write_unlocked(sst, SST_HMDC, HMD_CTRL_DEFAULT_VALUE); 271 - } 272 - 273 - /* all clock-gating minus DCLCGE and DTCGE */ 274 - #define SST_VDRTCL2_CG_OTHER 0xB7D 275 - 276 246 static void hsw_set_dsp_D3(struct sst_dsp *sst) 277 247 { 248 + u32 val; 278 249 u32 reg; 279 250 280 - /* disable clock core gating */ 251 + /* Disable core clock gating (VDRTCTL2.DCLCGE = 0) */ 281 252 reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2); 282 - reg &= ~(SST_VDRTCL2_DCLCGE); 253 + reg &= ~(SST_VDRTCL2_DCLCGE | SST_VDRTCL2_DTCGE); 283 254 writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2); 284 255 285 - /* stall, reset and set 24MHz XOSC */ 286 - sst_dsp_shim_update_bits_unlocked(sst, SST_CSR, 287 - SST_CSR_24MHZ_LPCS | SST_CSR_STALL | SST_CSR_RST, 288 - SST_CSR_24MHZ_LPCS | SST_CSR_STALL | SST_CSR_RST); 256 + /* enable power gating and switch off DRAM & IRAM blocks */ 257 + val = readl(sst->addr.pci_cfg + SST_VDRTCTL0); 258 + val |= SST_VDRTCL0_DSRAMPGE_MASK | 259 + SST_VDRTCL0_ISRAMPGE_MASK; 260 + val &= ~(SST_VDRTCL0_D3PGD | SST_VDRTCL0_D3SRAMPGD); 261 + writel(val, sst->addr.pci_cfg + SST_VDRTCTL0); 289 262 290 - /* DRAM power gating all */ 291 - reg = readl(sst->addr.pci_cfg + SST_VDRTCTL0); 292 - reg |= SST_VDRTCL0_ISRAMPGE_MASK | 293 - SST_VDRTCL0_DSRAMPGE_MASK; 294 - reg &= ~(SST_VDRTCL0_D3SRAMPGD); 295 - reg |= SST_VDRTCL0_D3PGD; 296 - writel(reg, sst->addr.pci_cfg + SST_VDRTCTL0); 297 - udelay(50); 263 + /* switch off audio PLL */ 264 + val = readl(sst->addr.pci_cfg + SST_VDRTCTL2); 265 + val |= SST_VDRTCL2_APLLSE_MASK; 266 + writel(val, sst->addr.pci_cfg + SST_VDRTCTL2); 298 267 299 - /* PLL shutdown enable */ 300 - reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2); 301 - reg |= SST_VDRTCL2_APLLSE_MASK; 302 - writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2); 303 - 304 - /* disable MCLK */ 268 + /* disable MCLK(clkctl.smos = 0) */ 305 269 sst_dsp_shim_update_bits_unlocked(sst, SST_CLKCTL, 306 - SST_CLKCTL_MASK, 0); 270 + SST_CLKCTL_MASK, 0); 307 271 308 - /* switch clock gating */ 309 - reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2); 310 - reg |= SST_VDRTCL2_CG_OTHER; 311 - reg &= ~(SST_VDRTCL2_DTCGE); 312 - writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2); 313 - /* enable DTCGE separatelly */ 314 - reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2); 315 - reg |= SST_VDRTCL2_DTCGE; 316 - writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2); 317 - 318 - /* set shim defaults */ 319 - hsw_set_shim_defaults(sst); 320 - 321 - /* set D3 */ 322 - reg = readl(sst->addr.pci_cfg + SST_PMCS); 323 - reg |= SST_PMCS_PS_MASK; 324 - writel(reg, sst->addr.pci_cfg + SST_PMCS); 272 + /* Set D3 state, delay 50 us */ 273 + val = readl(sst->addr.pci_cfg + SST_PMCS); 274 + val |= SST_PMCS_PS_MASK; 275 + writel(val, sst->addr.pci_cfg + SST_PMCS); 325 276 udelay(50); 326 277 327 - /* enable clock core gating */ 278 + /* Enable core clock gating (VDRTCTL2.DCLCGE = 1), delay 50 us */ 328 279 reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2); 329 - reg |= SST_VDRTCL2_DCLCGE; 280 + reg |= SST_VDRTCL2_DCLCGE | SST_VDRTCL2_DTCGE; 330 281 writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2); 282 + 331 283 udelay(50); 284 + 332 285 } 333 286 334 287 static void hsw_reset(struct sst_dsp *sst) ··· 299 346 SST_CSR_RST | SST_CSR_STALL, SST_CSR_STALL); 300 347 } 301 348 302 - /* recommended CSR state for power-up */ 303 - #define SST_CSR_D0_MASK (0x18A09C0C | SST_CSR_DCS_MASK) 304 - 305 349 static int hsw_set_dsp_D0(struct sst_dsp *sst) 306 350 { 307 - u32 reg; 351 + int tries = 10; 352 + u32 reg, fw_dump_bit; 308 353 309 - /* disable clock core gating */ 354 + /* Disable core clock gating (VDRTCTL2.DCLCGE = 0) */ 310 355 reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2); 311 - reg &= ~(SST_VDRTCL2_DCLCGE); 356 + reg &= ~(SST_VDRTCL2_DCLCGE | SST_VDRTCL2_DTCGE); 312 357 writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2); 313 358 314 - /* switch clock gating */ 315 - reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2); 316 - reg |= SST_VDRTCL2_CG_OTHER; 317 - reg &= ~(SST_VDRTCL2_DTCGE); 318 - writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2); 319 - 320 - /* set D0 */ 321 - reg = readl(sst->addr.pci_cfg + SST_PMCS); 322 - reg &= ~(SST_PMCS_PS_MASK); 323 - writel(reg, sst->addr.pci_cfg + SST_PMCS); 324 - 325 - /* DRAM power gating none */ 359 + /* Disable D3PG (VDRTCTL0.D3PGD = 1) */ 326 360 reg = readl(sst->addr.pci_cfg + SST_VDRTCTL0); 327 - reg &= ~(SST_VDRTCL0_ISRAMPGE_MASK | 328 - SST_VDRTCL0_DSRAMPGE_MASK); 329 - reg |= SST_VDRTCL0_D3SRAMPGD; 330 361 reg |= SST_VDRTCL0_D3PGD; 331 362 writel(reg, sst->addr.pci_cfg + SST_VDRTCTL0); 332 - mdelay(10); 333 363 334 - /* set shim defaults */ 335 - hsw_set_shim_defaults(sst); 364 + /* Set D0 state */ 365 + reg = readl(sst->addr.pci_cfg + SST_PMCS); 366 + reg &= ~SST_PMCS_PS_MASK; 367 + writel(reg, sst->addr.pci_cfg + SST_PMCS); 336 368 337 - /* restore MCLK */ 369 + /* check that ADSP shim is enabled */ 370 + while (tries--) { 371 + reg = readl(sst->addr.pci_cfg + SST_PMCS) & SST_PMCS_PS_MASK; 372 + if (reg == 0) 373 + goto finish; 374 + 375 + msleep(1); 376 + } 377 + 378 + return -ENODEV; 379 + 380 + finish: 381 + /* select SSP1 19.2MHz base clock, SSP clock 0, turn off Low Power Clock */ 382 + sst_dsp_shim_update_bits_unlocked(sst, SST_CSR, 383 + SST_CSR_S1IOCS | SST_CSR_SBCS1 | SST_CSR_LPCS, 0x0); 384 + 385 + /* stall DSP core, set clk to 192/96Mhz */ 386 + sst_dsp_shim_update_bits_unlocked(sst, 387 + SST_CSR, SST_CSR_STALL | SST_CSR_DCS_MASK, 388 + SST_CSR_STALL | SST_CSR_DCS(4)); 389 + 390 + /* Set 24MHz MCLK, prevent local clock gating, enable SSP0 clock */ 338 391 sst_dsp_shim_update_bits_unlocked(sst, SST_CLKCTL, 339 - SST_CLKCTL_MASK, SST_CLKCTL_MASK); 392 + SST_CLKCTL_MASK | SST_CLKCTL_DCPLCG | SST_CLKCTL_SCOE0, 393 + SST_CLKCTL_MASK | SST_CLKCTL_DCPLCG | SST_CLKCTL_SCOE0); 340 394 341 - /* PLL shutdown disable */ 395 + /* Stall and reset core, set CSR */ 396 + hsw_reset(sst); 397 + 398 + /* Enable core clock gating (VDRTCTL2.DCLCGE = 1), delay 50 us */ 342 399 reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2); 343 - reg &= ~(SST_VDRTCL2_APLLSE_MASK); 400 + reg |= SST_VDRTCL2_DCLCGE | SST_VDRTCL2_DTCGE; 344 401 writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2); 345 402 346 - sst_dsp_shim_update_bits_unlocked(sst, SST_CSR, 347 - SST_CSR_D0_MASK, SST_CSR_SBCS0 | SST_CSR_SBCS1 | 348 - SST_CSR_STALL | SST_CSR_DCS(4)); 349 403 udelay(50); 350 404 351 - /* enable clock core gating */ 405 + /* switch on audio PLL */ 352 406 reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2); 353 - reg |= SST_VDRTCL2_DCLCGE; 407 + reg &= ~SST_VDRTCL2_APLLSE_MASK; 354 408 writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2); 355 409 356 - /* clear reset */ 357 - sst_dsp_shim_update_bits_unlocked(sst, SST_CSR, SST_CSR_RST, 0); 410 + /* set default power gating control, enable power gating control for all blocks. that is, 411 + can't be accessed, please enable each block before accessing. */ 412 + reg = readl(sst->addr.pci_cfg + SST_VDRTCTL0); 413 + reg |= SST_VDRTCL0_DSRAMPGE_MASK | SST_VDRTCL0_ISRAMPGE_MASK; 414 + /* for D0, always enable the block(DSRAM[0]) used for FW dump */ 415 + fw_dump_bit = 1 << SST_VDRTCL0_DSRAMPGE_SHIFT; 416 + writel(reg & ~fw_dump_bit, sst->addr.pci_cfg + SST_VDRTCTL0); 417 + 358 418 359 419 /* disable DMA finish function for SSP0 & SSP1 */ 360 420 sst_dsp_shim_update_bits_unlocked(sst, SST_CSR2, SST_CSR2_SDFD_SSP1, ··· 383 417 0x0); 384 418 sst_dsp_shim_update_bits(sst, SST_IMRD, (SST_IMRD_DONE | SST_IMRD_BUSY | 385 419 SST_IMRD_SSP0 | SST_IMRD_DMAC), 0x0); 420 + 421 + /* clear IPC registers */ 422 + sst_dsp_shim_write(sst, SST_IPCX, 0x0); 423 + sst_dsp_shim_write(sst, SST_IPCD, 0x0); 424 + sst_dsp_shim_write(sst, 0x80, 0x6); 425 + sst_dsp_shim_write(sst, 0xe0, 0x300a); 386 426 387 427 return 0; 388 428 } ··· 414 442 static void hsw_sleep(struct sst_dsp *sst) 415 443 { 416 444 dev_dbg(sst->dev, "HSW_PM dsp runtime suspend\n"); 445 + 446 + /* put DSP into reset and stall */ 447 + sst_dsp_shim_update_bits(sst, SST_CSR, 448 + SST_CSR_24MHZ_LPCS | SST_CSR_RST | SST_CSR_STALL, 449 + SST_CSR_RST | SST_CSR_STALL | SST_CSR_24MHZ_LPCS); 417 450 418 451 hsw_set_dsp_D3(sst); 419 452 dev_dbg(sst->dev, "HSW_PM dsp runtime suspend exit\n");
+23 -1
sound/soc/meson/axg-toddr.c
··· 18 18 #define CTRL0_TODDR_SEL_RESAMPLE BIT(30) 19 19 #define CTRL0_TODDR_EXT_SIGNED BIT(29) 20 20 #define CTRL0_TODDR_PP_MODE BIT(28) 21 + #define CTRL0_TODDR_SYNC_CH BIT(27) 21 22 #define CTRL0_TODDR_TYPE_MASK GENMASK(15, 13) 22 23 #define CTRL0_TODDR_TYPE(x) ((x) << 13) 23 24 #define CTRL0_TODDR_MSB_POS_MASK GENMASK(12, 8) ··· 190 189 .dai_drv = &axg_toddr_dai_drv 191 190 }; 192 191 192 + static int g12a_toddr_dai_startup(struct snd_pcm_substream *substream, 193 + struct snd_soc_dai *dai) 194 + { 195 + struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai); 196 + int ret; 197 + 198 + ret = axg_toddr_dai_startup(substream, dai); 199 + if (ret) 200 + return ret; 201 + 202 + /* 203 + * Make sure the first channel ends up in the at beginning of the output 204 + * As weird as it looks, without this the first channel may be misplaced 205 + * in memory, with a random shift of 2 channels. 206 + */ 207 + regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_TODDR_SYNC_CH, 208 + CTRL0_TODDR_SYNC_CH); 209 + 210 + return 0; 211 + } 212 + 193 213 static const struct snd_soc_dai_ops g12a_toddr_ops = { 194 214 .prepare = g12a_toddr_dai_prepare, 195 215 .hw_params = axg_toddr_dai_hw_params, 196 - .startup = axg_toddr_dai_startup, 216 + .startup = g12a_toddr_dai_startup, 197 217 .shutdown = axg_toddr_dai_shutdown, 198 218 }; 199 219
+1
sound/soc/qcom/apq8016_sbc.c
··· 143 143 144 144 card = &data->card; 145 145 card->dev = dev; 146 + card->owner = THIS_MODULE; 146 147 card->dapm_widgets = apq8016_sbc_dapm_widgets; 147 148 card->num_dapm_widgets = ARRAY_SIZE(apq8016_sbc_dapm_widgets); 148 149
+1
sound/soc/qcom/apq8096.c
··· 114 114 return -ENOMEM; 115 115 116 116 card->dev = dev; 117 + card->owner = THIS_MODULE; 117 118 dev_set_drvdata(dev, card); 118 119 ret = qcom_snd_parse_of(card); 119 120 if (ret)
+4 -2
sound/soc/qcom/common.c
··· 52 52 53 53 for_each_child_of_node(dev->of_node, np) { 54 54 dlc = devm_kzalloc(dev, 2 * sizeof(*dlc), GFP_KERNEL); 55 - if (!dlc) 56 - return -ENOMEM; 55 + if (!dlc) { 56 + ret = -ENOMEM; 57 + goto err; 58 + } 57 59 58 60 link->cpus = &dlc[0]; 59 61 link->platforms = &dlc[1];
+1
sound/soc/qcom/sdm845.c
··· 555 555 card->dapm_widgets = sdm845_snd_widgets; 556 556 card->num_dapm_widgets = ARRAY_SIZE(sdm845_snd_widgets); 557 557 card->dev = dev; 558 + card->owner = THIS_MODULE; 558 559 dev_set_drvdata(dev, card); 559 560 ret = qcom_snd_parse_of(card); 560 561 if (ret)
+1
sound/soc/qcom/storm.c
··· 96 96 return -ENOMEM; 97 97 98 98 card->dev = &pdev->dev; 99 + card->owner = THIS_MODULE; 99 100 100 101 ret = snd_soc_of_parse_card_name(card, "qcom,model"); 101 102 if (ret) {
+13
sound/soc/soc-core.c
··· 834 834 } 835 835 EXPORT_SYMBOL_GPL(snd_soc_find_dai); 836 836 837 + struct snd_soc_dai *snd_soc_find_dai_with_mutex( 838 + const struct snd_soc_dai_link_component *dlc) 839 + { 840 + struct snd_soc_dai *dai; 841 + 842 + mutex_lock(&client_mutex); 843 + dai = snd_soc_find_dai(dlc); 844 + mutex_unlock(&client_mutex); 845 + 846 + return dai; 847 + } 848 + EXPORT_SYMBOL_GPL(snd_soc_find_dai_with_mutex); 849 + 837 850 static int soc_dai_link_sanity_check(struct snd_soc_card *card, 838 851 struct snd_soc_dai_link *link) 839 852 {
+2 -2
sound/soc/soc-dai.c
··· 412 412 supported_codec = false; 413 413 414 414 for_each_link_cpus(dai_link, i, cpu) { 415 - dai = snd_soc_find_dai(cpu); 415 + dai = snd_soc_find_dai_with_mutex(cpu); 416 416 if (dai && snd_soc_dai_stream_valid(dai, direction)) { 417 417 supported_cpu = true; 418 418 break; 419 419 } 420 420 } 421 421 for_each_link_codecs(dai_link, i, codec) { 422 - dai = snd_soc_find_dai(codec); 422 + dai = snd_soc_find_dai_with_mutex(codec); 423 423 if (dai && snd_soc_dai_stream_valid(dai, direction)) { 424 424 supported_codec = true; 425 425 break;
+1 -1
sound/soc/soc-pcm.c
··· 812 812 return 0; 813 813 814 814 config_err: 815 - for_each_rtd_dais(rtd, i, dai) 815 + for_each_rtd_dais_rollback(rtd, i, dai) 816 816 snd_soc_dai_shutdown(dai, substream); 817 817 818 818 snd_soc_link_shutdown(substream);
+2 -2
sound/soc/ti/ams-delta.c
··· 446 446 /* Will be used if the codec ever has its own digital_mute function */ 447 447 static int ams_delta_startup(struct snd_pcm_substream *substream) 448 448 { 449 - return ams_delta_digital_mute(NULL, 0, substream->stream); 449 + return ams_delta_mute(NULL, 0, substream->stream); 450 450 } 451 451 452 452 static void ams_delta_shutdown(struct snd_pcm_substream *substream) 453 453 { 454 - ams_delta_digital_mute(NULL, 1, substream->stream); 454 + ams_delta_mute(NULL, 1, substream->stream); 455 455 } 456 456 457 457