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spi: axi-spi-engine: improve version checks

Merge series from David Lechner <dlechner@baylibre.com>:

We have a pending major version bump for the axi-spi-engine so to
prepare for that, improve the existing version checks for feature
enablement.

+28 -10
+7 -10
drivers/spi/spi-axi-spi-engine.c
··· 1050 1050 return -ENODEV; 1051 1051 } 1052 1052 1053 - if (ADI_AXI_PCORE_VER_MINOR(version) >= 1) { 1053 + if (adi_axi_pcore_ver_gteq(version, 1, 1)) { 1054 1054 unsigned int sizes = readl(spi_engine->base + 1055 1055 SPI_ENGINE_REG_OFFLOAD_MEM_ADDR_WIDTH); 1056 1056 ··· 1064 1064 } 1065 1065 1066 1066 /* IP v1.5 dropped the requirement for SYNC in offload messages. */ 1067 - spi_engine->offload_requires_sync = ADI_AXI_PCORE_VER_MINOR(version) < 5; 1067 + spi_engine->offload_requires_sync = !adi_axi_pcore_ver_gteq(version, 1, 5); 1068 1068 1069 1069 writel_relaxed(0x00, spi_engine->base + SPI_ENGINE_REG_RESET); 1070 1070 writel_relaxed(0xff, spi_engine->base + SPI_ENGINE_REG_INT_PENDING); ··· 1091 1091 host->put_offload = spi_engine_put_offload; 1092 1092 host->num_chipselect = 8; 1093 1093 1094 - /* Some features depend of the IP core version. */ 1095 - if (ADI_AXI_PCORE_VER_MAJOR(version) >= 1) { 1096 - if (ADI_AXI_PCORE_VER_MINOR(version) >= 2) { 1097 - host->mode_bits |= SPI_CS_HIGH; 1098 - host->setup = spi_engine_setup; 1099 - } 1100 - if (ADI_AXI_PCORE_VER_MINOR(version) >= 3) 1101 - host->mode_bits |= SPI_MOSI_IDLE_LOW | SPI_MOSI_IDLE_HIGH; 1094 + if (adi_axi_pcore_ver_gteq(version, 1, 2)) { 1095 + host->mode_bits |= SPI_CS_HIGH; 1096 + host->setup = spi_engine_setup; 1102 1097 } 1098 + if (adi_axi_pcore_ver_gteq(version, 1, 3)) 1099 + host->mode_bits |= SPI_MOSI_IDLE_LOW | SPI_MOSI_IDLE_HIGH; 1103 1100 1104 1101 if (host->max_speed_hz == 0) 1105 1102 return dev_err_probe(&pdev->dev, -EINVAL, "spi_clk rate is 0");
+21
include/linux/adi-axi-common.h
··· 8 8 * https://wiki.analog.com/resources/fpga/docs/hdl/regmap 9 9 */ 10 10 11 + #include <linux/types.h> 12 + 11 13 #ifndef ADI_AXI_COMMON_H_ 12 14 #define ADI_AXI_COMMON_H_ 13 15 ··· 22 20 #define ADI_AXI_PCORE_VER_MAJOR(version) (((version) >> 16) & 0xff) 23 21 #define ADI_AXI_PCORE_VER_MINOR(version) (((version) >> 8) & 0xff) 24 22 #define ADI_AXI_PCORE_VER_PATCH(version) ((version) & 0xff) 23 + 24 + /** 25 + * adi_axi_pcore_ver_gteq() - check if a version is satisfied 26 + * @version: the full version read from the hardware 27 + * @major: the major version to compare against 28 + * @minor: the minor version to compare against 29 + * 30 + * ADI AXI IP Cores use semantic versioning, so this can be used to check for 31 + * feature availability. 32 + * 33 + * Return: true if the version is greater than or equal to the specified 34 + * major and minor version, false otherwise. 35 + */ 36 + static inline bool adi_axi_pcore_ver_gteq(u32 version, u32 major, u32 minor) 37 + { 38 + return ADI_AXI_PCORE_VER_MAJOR(version) > (major) || 39 + (ADI_AXI_PCORE_VER_MAJOR(version) == (major) && 40 + ADI_AXI_PCORE_VER_MINOR(version) >= (minor)); 41 + } 25 42 26 43 #define ADI_AXI_INFO_FPGA_TECH(info) (((info) >> 24) & 0xff) 27 44 #define ADI_AXI_INFO_FPGA_FAMILY(info) (((info) >> 16) & 0xff)