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drm/amdgpu: Fix potential integer overflow in scheduler mask calculations

The use of 1 << i in scheduler mask calculations can result in an
unintentional integer overflow due to the expression being
evaluated as a 32-bit signed integer.

This patch replaces 1 << i with 1ULL << i to ensure the operation
is performed as a 64-bit unsigned integer, preventing overflow

Discovered in coverity scan, CID 1636393, 1636175, 1636007, 1635853

Fixes: c5c63d9cb5d3 ("drm/amdgpu: add amdgpu_gfx_sched_mask and amdgpu_compute_sched_mask debugfs")
Signed-off-by: Karol Przybylski <karprzy7@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Karol Przybylski and committed by
Alex Deucher 34c4eb7d 8f2cd106

+4 -4
+4 -4
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
··· 2124 2124 if (!adev) 2125 2125 return -ENODEV; 2126 2126 2127 - mask = (1 << adev->gfx.num_gfx_rings) - 1; 2127 + mask = (1ULL << adev->gfx.num_gfx_rings) - 1; 2128 2128 if ((val & mask) == 0) 2129 2129 return -EINVAL; 2130 2130 ··· 2152 2152 for (i = 0; i < adev->gfx.num_gfx_rings; ++i) { 2153 2153 ring = &adev->gfx.gfx_ring[i]; 2154 2154 if (ring->sched.ready) 2155 - mask |= 1 << i; 2155 + mask |= 1ULL << i; 2156 2156 } 2157 2157 2158 2158 *val = mask; ··· 2194 2194 if (!adev) 2195 2195 return -ENODEV; 2196 2196 2197 - mask = (1 << adev->gfx.num_compute_rings) - 1; 2197 + mask = (1ULL << adev->gfx.num_compute_rings) - 1; 2198 2198 if ((val & mask) == 0) 2199 2199 return -EINVAL; 2200 2200 ··· 2223 2223 for (i = 0; i < adev->gfx.num_compute_rings; ++i) { 2224 2224 ring = &adev->gfx.compute_ring[i]; 2225 2225 if (ring->sched.ready) 2226 - mask |= 1 << i; 2226 + mask |= 1ULL << i; 2227 2227 } 2228 2228 2229 2229 *val = mask;