Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'random-6.12-rc1-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/crng/random
Pull more random number generator updates from Jason Donenfeld:
- Christophe realized that the LoongArch64 instructions could be
scheduled more similar to how GCC generates code, which Ruoyao
implemented, for a 5% speedup from basically some rearrangements
- An update to MAINTAINERS to match the right files
* tag 'random-6.12-rc1-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/crng/random:
LoongArch: vDSO: Tune chacha implementation
MAINTAINERS: make vDSO getrandom matches more generic
+56
-41
+1
-4
MAINTAINERS
+1
-4
MAINTAINERS
···
19344
19344
F: include/linux/random.h
19345
19345
F: include/uapi/linux/random.h
19346
19346
F: drivers/virt/vmgenid.c
19347
-
F: include/vdso/getrandom.h
19348
-
F: lib/vdso/getrandom.c
19349
-
F: arch/x86/entry/vdso/vgetrandom*
19350
-
F: arch/x86/include/asm/vdso/getrandom*
19347
+
N: ^.*/vdso/[^/]*getrandom[^/]+$
19351
19348
19352
19349
RAPIDIO SUBSYSTEM
19353
19350
M: Matt Porter <mporter@kernel.crashing.org>
+55
-37
arch/loongarch/vdso/vgetrandom-chacha.S
+55
-37
arch/loongarch/vdso/vgetrandom-chacha.S
···
9
9
10
10
.text
11
11
12
-
/* Salsa20 quarter-round */
13
-
.macro QR a b c d
14
-
add.w \a, \a, \b
15
-
xor \d, \d, \a
16
-
rotri.w \d, \d, 16
17
-
18
-
add.w \c, \c, \d
19
-
xor \b, \b, \c
20
-
rotri.w \b, \b, 20
21
-
22
-
add.w \a, \a, \b
23
-
xor \d, \d, \a
24
-
rotri.w \d, \d, 24
25
-
26
-
add.w \c, \c, \d
27
-
xor \b, \b, \c
28
-
rotri.w \b, \b, 25
12
+
.macro OP_4REG op d0 d1 d2 d3 s0 s1 s2 s3
13
+
\op \d0, \d0, \s0
14
+
\op \d1, \d1, \s1
15
+
\op \d2, \d2, \s2
16
+
\op \d3, \d3, \s3
29
17
.endm
30
18
31
19
/*
···
61
73
62
74
/* Reuse i as copy3 */
63
75
#define copy3 i
76
+
77
+
/* Packs to be used with OP_4REG */
78
+
#define line0 state0, state1, state2, state3
79
+
#define line1 state4, state5, state6, state7
80
+
#define line2 state8, state9, state10, state11
81
+
#define line3 state12, state13, state14, state15
82
+
83
+
#define line1_perm state5, state6, state7, state4
84
+
#define line2_perm state10, state11, state8, state9
85
+
#define line3_perm state15, state12, state13, state14
86
+
87
+
#define copy copy0, copy1, copy2, copy3
88
+
89
+
#define _16 16, 16, 16, 16
90
+
#define _20 20, 20, 20, 20
91
+
#define _24 24, 24, 24, 24
92
+
#define _25 25, 25, 25, 25
64
93
65
94
/*
66
95
* The ABI requires s0-s9 saved, and sp aligned to 16-byte.
···
131
126
li.w i, 10
132
127
.Lpermute:
133
128
/* odd round */
134
-
QR state0, state4, state8, state12
135
-
QR state1, state5, state9, state13
136
-
QR state2, state6, state10, state14
137
-
QR state3, state7, state11, state15
129
+
OP_4REG add.w line0, line1
130
+
OP_4REG xor line3, line0
131
+
OP_4REG rotri.w line3, _16
132
+
133
+
OP_4REG add.w line2, line3
134
+
OP_4REG xor line1, line2
135
+
OP_4REG rotri.w line1, _20
136
+
137
+
OP_4REG add.w line0, line1
138
+
OP_4REG xor line3, line0
139
+
OP_4REG rotri.w line3, _24
140
+
141
+
OP_4REG add.w line2, line3
142
+
OP_4REG xor line1, line2
143
+
OP_4REG rotri.w line1, _25
138
144
139
145
/* even round */
140
-
QR state0, state5, state10, state15
141
-
QR state1, state6, state11, state12
142
-
QR state2, state7, state8, state13
143
-
QR state3, state4, state9, state14
146
+
OP_4REG add.w line0, line1_perm
147
+
OP_4REG xor line3_perm, line0
148
+
OP_4REG rotri.w line3_perm, _16
149
+
150
+
OP_4REG add.w line2_perm, line3_perm
151
+
OP_4REG xor line1_perm, line2_perm
152
+
OP_4REG rotri.w line1_perm, _20
153
+
154
+
OP_4REG add.w line0, line1_perm
155
+
OP_4REG xor line3_perm, line0
156
+
OP_4REG rotri.w line3_perm, _24
157
+
158
+
OP_4REG add.w line2_perm, line3_perm
159
+
OP_4REG xor line1_perm, line2_perm
160
+
OP_4REG rotri.w line1_perm, _25
144
161
145
162
addi.w i, i, -1
146
163
bnez i, .Lpermute
···
174
147
li.w copy3, 0x6b206574
175
148
176
149
/* output[0,1,2,3] = copy[0,1,2,3] + state[0,1,2,3] */
177
-
add.w state0, state0, copy0
178
-
add.w state1, state1, copy1
179
-
add.w state2, state2, copy2
180
-
add.w state3, state3, copy3
150
+
OP_4REG add.w line0, copy
181
151
st.w state0, output, 0
182
152
st.w state1, output, 4
183
153
st.w state2, output, 8
···
189
165
ld.w state3, key, 12
190
166
191
167
/* output[4,5,6,7] = state[0,1,2,3] + state[4,5,6,7] */
192
-
add.w state4, state4, state0
193
-
add.w state5, state5, state1
194
-
add.w state6, state6, state2
195
-
add.w state7, state7, state3
168
+
OP_4REG add.w line1, line0
196
169
st.w state4, output, 16
197
170
st.w state5, output, 20
198
171
st.w state6, output, 24
···
202
181
ld.w state3, key, 28
203
182
204
183
/* output[8,9,10,11] = state[0,1,2,3] + state[8,9,10,11] */
205
-
add.w state8, state8, state0
206
-
add.w state9, state9, state1
207
-
add.w state10, state10, state2
208
-
add.w state11, state11, state3
184
+
OP_4REG add.w line2, line0
209
185
st.w state8, output, 32
210
186
st.w state9, output, 36
211
187
st.w state10, output, 40