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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
dt-bindings: reset: mt8188: Add VDOSYS reset control bits
Add MT8188 VDOSYS0 and VDOSYS1 reset control bits.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
authored by
Hsiao Chien Sung
and committed by
AngeloGioacchino Del Regno
3526cfae
41b3a96c
+75
+75
include/dt-bindings/reset/mt8188-resets.h
+75
include/dt-bindings/reset/mt8188-resets.h
···
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#define MT8188_INFRA_RST1_THERMAL_CTRL_RST 1
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#define MT8188_INFRA_RST3_PTP_CTRL_RST 2
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#define MT8188_VDO0_RST_DISP_OVL0 0
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#define MT8188_VDO0_RST_FAKE_ENG0 1
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#define MT8188_VDO0_RST_DISP_CCORR0 2
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#define MT8188_VDO0_RST_DISP_MUTEX0 3
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#define MT8188_VDO0_RST_DISP_GAMMA0 4
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#define MT8188_VDO0_RST_DISP_DITHER0 5
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#define MT8188_VDO0_RST_DISP_WDMA0 6
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#define MT8188_VDO0_RST_DISP_RDMA0 7
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#define MT8188_VDO0_RST_DSI0 8
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#define MT8188_VDO0_RST_DSI1 9
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#define MT8188_VDO0_RST_DSC_WRAP0 10
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#define MT8188_VDO0_RST_VPP_MERGE0 11
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#define MT8188_VDO0_RST_DP_INTF0 12
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#define MT8188_VDO0_RST_DISP_AAL0 13
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#define MT8188_VDO0_RST_INLINEROT0 14
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#define MT8188_VDO0_RST_APB_BUS 15
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#define MT8188_VDO0_RST_DISP_COLOR0 16
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#define MT8188_VDO0_RST_MDP_WROT0 17
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#define MT8188_VDO0_RST_DISP_RSZ0 18
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#define MT8188_VDO1_RST_SMI_LARB2 0
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#define MT8188_VDO1_RST_SMI_LARB3 1
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#define MT8188_VDO1_RST_GALS 2
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#define MT8188_VDO1_RST_FAKE_ENG0 3
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#define MT8188_VDO1_RST_FAKE_ENG1 4
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#define MT8188_VDO1_RST_MDP_RDMA0 5
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#define MT8188_VDO1_RST_MDP_RDMA1 6
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#define MT8188_VDO1_RST_MDP_RDMA2 7
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#define MT8188_VDO1_RST_MDP_RDMA3 8
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#define MT8188_VDO1_RST_VPP_MERGE0 9
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#define MT8188_VDO1_RST_VPP_MERGE1 10
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#define MT8188_VDO1_RST_VPP_MERGE2 11
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#define MT8188_VDO1_RST_VPP_MERGE3 12
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#define MT8188_VDO1_RST_VPP_MERGE4 13
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#define MT8188_VDO1_RST_VPP2_TO_VDO1_DL_ASYNC 14
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#define MT8188_VDO1_RST_VPP3_TO_VDO1_DL_ASYNC 15
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#define MT8188_VDO1_RST_DISP_MUTEX 16
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#define MT8188_VDO1_RST_MDP_RDMA4 17
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#define MT8188_VDO1_RST_MDP_RDMA5 18
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#define MT8188_VDO1_RST_MDP_RDMA6 19
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#define MT8188_VDO1_RST_MDP_RDMA7 20
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#define MT8188_VDO1_RST_DP_INTF1_MMCK 21
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#define MT8188_VDO1_RST_DPI0_MM_CK 22
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#define MT8188_VDO1_RST_DPI1_MM_CK 23
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#define MT8188_VDO1_RST_MERGE0_DL_ASYNC 24
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#define MT8188_VDO1_RST_MERGE1_DL_ASYNC 25
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#define MT8188_VDO1_RST_MERGE2_DL_ASYNC 26
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#define MT8188_VDO1_RST_MERGE3_DL_ASYNC 27
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#define MT8188_VDO1_RST_MERGE4_DL_ASYNC 28
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#define MT8188_VDO1_RST_VDO0_DSC_TO_VDO1_DL_ASYNC 29
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#define MT8188_VDO1_RST_VDO0_MERGE_TO_VDO1_DL_ASYNC 30
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#define MT8188_VDO1_RST_PADDING0 31
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#define MT8188_VDO1_RST_PADDING1 32
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#define MT8188_VDO1_RST_PADDING2 33
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#define MT8188_VDO1_RST_PADDING3 34
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#define MT8188_VDO1_RST_PADDING4 35
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#define MT8188_VDO1_RST_PADDING5 36
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#define MT8188_VDO1_RST_PADDING6 37
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#define MT8188_VDO1_RST_PADDING7 38
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#define MT8188_VDO1_RST_DISP_RSZ0 39
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#define MT8188_VDO1_RST_DISP_RSZ1 40
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#define MT8188_VDO1_RST_DISP_RSZ2 41
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#define MT8188_VDO1_RST_DISP_RSZ3 42
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#define MT8188_VDO1_RST_HDR_VDO_FE0 43
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#define MT8188_VDO1_RST_HDR_GFX_FE0 44
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#define MT8188_VDO1_RST_HDR_VDO_BE 45
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#define MT8188_VDO1_RST_HDR_VDO_FE1 46
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#define MT8188_VDO1_RST_HDR_GFX_FE1 47
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#define MT8188_VDO1_RST_DISP_MIXER 48
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#define MT8188_VDO1_RST_HDR_VDO_FE0_DL_ASYNC 49
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#define MT8188_VDO1_RST_HDR_VDO_FE1_DL_ASYNC 50
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#define MT8188_VDO1_RST_HDR_GFX_FE0_DL_ASYNC 51
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#define MT8188_VDO1_RST_HDR_GFX_FE1_DL_ASYNC 52
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#define MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC 53
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#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8188 */