Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amd/display: Move FPU Guards From DML To DC - Part 1
[Why]
FPU guards (DC_FP_START/DC_FP_END) are required to wrap around code that
can manipulates floats. To do this properly, the FPU guards must be used
in a file that is not compiled as a FPU unit. If the guards are used in
a file that is a FPU unit, other sections in the file that aren't guarded
may be end up being compiled to use FPU operations.
[How]
Added DC_FP_START and DC_FP_END to DC functions that call DML functions
using FPU.
Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Rafal Ostrowski <rafal.ostrowski@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Rafal Ostrowski
and committed by
Alex Deucher
3539437f
02c3060e
+171
-54
+22
-3
drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c
+22
-3
drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c
···
53
53
{
54
54
int depth;
55
55
56
-
depth = __this_cpu_read(fpu_recursion_depth);
56
+
depth = this_cpu_read(fpu_recursion_depth);
57
57
58
58
ASSERT(depth >= 1);
59
+
}
60
+
61
+
/**
62
+
* dc_assert_fp_enabled - Check if FPU protection is enabled
63
+
*
64
+
* This function tells if the code is already under FPU protection or not. A
65
+
* function that works as an API for a set of FPU operations can use this
66
+
* function for checking if the caller invoked it after DC_FP_START(). For
67
+
* example, take a look at dcn20_fpu.c file.
68
+
*
69
+
* Similar to dc_assert_fp_enabled, but does not assert, returns status instead.
70
+
*/
71
+
inline bool dc_is_fp_enabled(void)
72
+
{
73
+
int depth;
74
+
75
+
depth = this_cpu_read(fpu_recursion_depth);
76
+
77
+
return (depth >= 1);
59
78
}
60
79
61
80
/**
···
96
77
97
78
WARN_ON_ONCE(!in_task());
98
79
preempt_disable();
99
-
depth = __this_cpu_inc_return(fpu_recursion_depth);
80
+
depth = this_cpu_inc_return(fpu_recursion_depth);
100
81
if (depth == 1) {
101
82
BUG_ON(!kernel_fpu_available());
102
83
kernel_fpu_begin();
···
119
100
{
120
101
int depth;
121
102
122
-
depth = __this_cpu_dec_return(fpu_recursion_depth);
103
+
depth = this_cpu_dec_return(fpu_recursion_depth);
123
104
if (depth == 0) {
124
105
kernel_fpu_end();
125
106
} else {
+16
-1
drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.h
+16
-1
drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.h
···
28
28
#define __DC_FPU_H__
29
29
30
30
void dc_assert_fp_enabled(void);
31
+
bool dc_is_fp_enabled(void);
31
32
void dc_fpu_begin(const char *function_name, const int line);
32
33
void dc_fpu_end(const char *function_name, const int line);
33
34
34
35
#ifndef _LINUX_FPU_COMPILATION_UNIT
35
36
#define DC_FP_START() dc_fpu_begin(__func__, __LINE__)
36
37
#define DC_FP_END() dc_fpu_end(__func__, __LINE__)
38
+
#ifdef CONFIG_DRM_AMD_DC_FP
39
+
#define DC_RUN_WITH_PREEMPTION_ENABLED(code) \
40
+
do { \
41
+
bool dc_fp_enabled = dc_is_fp_enabled(); \
42
+
if (dc_fp_enabled) \
43
+
DC_FP_END(); \
44
+
code; \
45
+
if (dc_fp_enabled) \
46
+
DC_FP_START(); \
47
+
} while (0)
48
+
#else
49
+
#define DC_RUN_WITH_PREEMPTION_ENABLED(code) code
50
+
#endif // !CONFIG_DRM_AMD_DC_FP
37
51
#else
38
52
#define DC_FP_START() BUILD_BUG()
39
53
#define DC_FP_END() BUILD_BUG()
40
-
#endif
54
+
#define DC_RUN_WITH_PREEMPTION_ENABLED(code) code
55
+
#endif // !_LINUX_FPU_COMPILATION_UNIT
41
56
42
57
#endif /* __DC_FPU_H__ */
-2
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
-2
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
···
421
421
clk_mgr_base->bw_params->dc_mode_softmax_memclk = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_UCLK);
422
422
423
423
/* Refresh bounding box */
424
-
DC_FP_START();
425
424
clk_mgr_base->ctx->dc->res_pool->funcs->update_bw_bounding_box(
426
425
clk_mgr->base.ctx->dc, clk_mgr_base->bw_params);
427
-
DC_FP_END();
428
426
}
429
427
430
428
static bool dcn3_is_smu_present(struct clk_mgr *clk_mgr_base)
-2
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
-2
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
···
1059
1059
if (!clk_mgr->dpm_present)
1060
1060
dcn32_patch_dpm_table(clk_mgr_base->bw_params);
1061
1061
1062
-
DC_FP_START();
1063
1062
/* Refresh bounding box */
1064
1063
clk_mgr_base->ctx->dc->res_pool->funcs->update_bw_bounding_box(
1065
1064
clk_mgr->base.ctx->dc, clk_mgr_base->bw_params);
1066
-
DC_FP_END();
1067
1065
}
1068
1066
1069
1067
static bool dcn32_are_clock_states_equal(struct dc_clocks *a,
+1
-4
drivers/gpu/drm/amd/display/dc/core/dc.c
+1
-4
drivers/gpu/drm/amd/display/dc/core/dc.c
···
1096
1096
#ifdef CONFIG_DRM_AMD_DC_FP
1097
1097
dc->clk_mgr->force_smu_not_present = init_params->force_smu_not_present;
1098
1098
1099
-
if (dc->res_pool->funcs->update_bw_bounding_box) {
1100
-
DC_FP_START();
1099
+
if (dc->res_pool->funcs->update_bw_bounding_box)
1101
1100
dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params);
1102
-
DC_FP_END();
1103
-
}
1104
1101
dc->soc_and_ip_translator = dc_create_soc_and_ip_translator(dc_ctx->dce_version);
1105
1102
if (!dc->soc_and_ip_translator)
1106
1103
goto fail;
+55
-20
drivers/gpu/drm/amd/display/dc/core/dc_state.c
+55
-20
drivers/gpu/drm/amd/display/dc/core/dc_state.c
···
205
205
state->power_source = params ? params->power_source : DC_POWER_SOURCE_AC;
206
206
207
207
#ifdef CONFIG_DRM_AMD_DC_FP
208
+
bool status;
209
+
208
210
if (dc->debug.using_dml2) {
209
-
if (!dml2_create(dc, &dc->dml2_options, &state->bw_ctx.dml2)) {
211
+
DC_FP_START();
212
+
status = dml2_create(dc, &dc->dml2_options, &state->bw_ctx.dml2);
213
+
DC_FP_END();
214
+
215
+
if (!status) {
210
216
dc_state_release(state);
211
217
return NULL;
212
218
}
213
219
214
-
if (dc->caps.dcmode_power_limits_present && !dml2_create(dc, &dc->dml2_dc_power_options, &state->bw_ctx.dml2_dc_power_source)) {
215
-
dc_state_release(state);
216
-
return NULL;
220
+
if (dc->caps.dcmode_power_limits_present) {
221
+
bool status;
222
+
223
+
DC_FP_START();
224
+
status = dml2_create(dc, &dc->dml2_dc_power_options, &state->bw_ctx.dml2_dc_power_source);
225
+
DC_FP_END();
226
+
227
+
if (!status) {
228
+
dc_state_release(state);
229
+
return NULL;
230
+
}
217
231
}
232
+
218
233
}
219
-
#endif
220
-
234
+
#endif // CONFIG_DRM_AMD_DC_FP
221
235
kref_init(&state->refcount);
222
236
223
237
return state;
···
249
235
250
236
#ifdef CONFIG_DRM_AMD_DC_FP
251
237
dst_state->bw_ctx.dml2 = dst_dml2;
252
-
if (src_state->bw_ctx.dml2)
238
+
if (src_state->bw_ctx.dml2) {
239
+
DC_FP_START();
253
240
dml2_copy(dst_state->bw_ctx.dml2, src_state->bw_ctx.dml2);
241
+
DC_FP_END();
242
+
}
254
243
255
244
dst_state->bw_ctx.dml2_dc_power_source = dst_dml2_dc_power_source;
256
-
if (src_state->bw_ctx.dml2_dc_power_source)
257
-
dml2_copy(dst_state->bw_ctx.dml2_dc_power_source, src_state->bw_ctx.dml2_dc_power_source);
258
-
#endif
259
245
246
+
if (src_state->bw_ctx.dml2_dc_power_source) {
247
+
DC_FP_START();
248
+
dml2_copy(dst_state->bw_ctx.dml2_dc_power_source, src_state->bw_ctx.dml2_dc_power_source);
249
+
DC_FP_END();
250
+
}
251
+
#endif // CONFIG_DRM_AMD_DC_FP
260
252
/* context refcount should not be overridden */
261
253
dst_state->refcount = refcount;
262
254
}
···
278
258
dc_state_copy_internal(new_state, src_state);
279
259
280
260
#ifdef CONFIG_DRM_AMD_DC_FP
261
+
bool status;
262
+
281
263
new_state->bw_ctx.dml2 = NULL;
282
264
new_state->bw_ctx.dml2_dc_power_source = NULL;
283
265
284
-
if (src_state->bw_ctx.dml2 &&
285
-
!dml2_create_copy(&new_state->bw_ctx.dml2, src_state->bw_ctx.dml2)) {
286
-
dc_state_release(new_state);
287
-
return NULL;
266
+
if (src_state->bw_ctx.dml2) {
267
+
DC_FP_START();
268
+
status = dml2_create_copy(&new_state->bw_ctx.dml2, src_state->bw_ctx.dml2);
269
+
DC_FP_END();
270
+
271
+
if (!status) {
272
+
dc_state_release(new_state);
273
+
return NULL;
274
+
}
288
275
}
289
276
290
-
if (src_state->bw_ctx.dml2_dc_power_source &&
291
-
!dml2_create_copy(&new_state->bw_ctx.dml2_dc_power_source, src_state->bw_ctx.dml2_dc_power_source)) {
292
-
dc_state_release(new_state);
293
-
return NULL;
294
-
}
295
-
#endif
296
277
278
+
if (src_state->bw_ctx.dml2_dc_power_source) {
279
+
DC_FP_START();
280
+
status = dml2_create_copy(&new_state->bw_ctx.dml2_dc_power_source,
281
+
src_state->bw_ctx.dml2_dc_power_source);
282
+
DC_FP_END();
283
+
284
+
if (!status) {
285
+
dc_state_release(new_state);
286
+
return NULL;
287
+
}
288
+
}
289
+
#endif // CONFIG_DRM_AMD_DC_FP
297
290
kref_init(&new_state->refcount);
298
291
299
292
return new_state;
···
384
351
dc_state_destruct(state);
385
352
386
353
#ifdef CONFIG_DRM_AMD_DC_FP
354
+
DC_FP_START();
387
355
dml2_destroy(state->bw_ctx.dml2);
388
356
state->bw_ctx.dml2 = 0;
389
357
390
358
dml2_destroy(state->bw_ctx.dml2_dc_power_source);
391
359
state->bw_ctx.dml2_dc_power_source = 0;
360
+
DC_FP_END();
392
361
#endif
393
362
394
363
kvfree(state);
+11
-2
drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+11
-2
drivers/gpu/drm/amd/display/dc/core/dc_stream.c
···
42
42
#define MAX(x, y) ((x > y) ? x : y)
43
43
#endif
44
44
45
+
#include "dc_fpu.h"
46
+
47
+
#if !defined(DC_RUN_WITH_PREEMPTION_ENABLED)
48
+
#define DC_RUN_WITH_PREEMPTION_ENABLED(code) code
49
+
#endif // !DC_RUN_WITH_PREEMPTION_ENABLED
50
+
51
+
45
52
/*******************************************************************************
46
53
* Private functions
47
54
******************************************************************************/
···
177
170
if (sink == NULL)
178
171
goto fail;
179
172
180
-
stream = kzalloc_obj(struct dc_stream_state, GFP_ATOMIC);
173
+
DC_RUN_WITH_PREEMPTION_ENABLED(stream = kzalloc_obj(struct dc_stream_state, GFP_ATOMIC));
181
174
182
175
if (stream == NULL)
183
176
goto fail;
184
177
185
-
stream->update_scratch = kzalloc((int32_t) dc_update_scratch_space_size(), GFP_ATOMIC);
178
+
DC_RUN_WITH_PREEMPTION_ENABLED(stream->update_scratch =
179
+
kzalloc((int32_t) dc_update_scratch_space_size(),
180
+
GFP_ATOMIC));
186
181
187
182
if (stream->update_scratch == NULL)
188
183
goto fail;
+2
-2
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
+2
-2
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
···
368
368
dc->res_pool->funcs->update_bw_bounding_box &&
369
369
dc->clk_mgr && dc->clk_mgr->bw_params) {
370
370
/* update bounding box if FAMS2 disabled, or if dchub clk has changed */
371
-
dc->res_pool->funcs->update_bw_bounding_box(dc,
372
-
dc->clk_mgr->bw_params);
371
+
if (dc->clk_mgr)
372
+
dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params);
373
373
}
374
374
}
375
375
}
+9
-1
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
+9
-1
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
···
1738
1738
{
1739
1739
bool out = false;
1740
1740
1741
+
DC_FP_START();
1741
1742
out = dml2_validate(dc, context,
1742
1743
context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2,
1743
1744
validate_mode);
1745
+
DC_FP_END();
1744
1746
1745
1747
if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING)
1746
1748
return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
···
1776
1774
return ret;
1777
1775
}
1778
1776
1777
+
void dcn35_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1778
+
{
1779
+
DC_FP_START();
1780
+
dcn35_update_bw_bounding_box_fpu(dc, bw_params);
1781
+
DC_FP_END();
1782
+
}
1779
1783
static struct resource_funcs dcn35_res_pool_funcs = {
1780
1784
.destroy = dcn35_destroy_resource_pool,
1781
1785
.link_enc_create = dcn35_link_encoder_create,
···
1803
1795
.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1804
1796
.acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1805
1797
.release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1806
-
.update_bw_bounding_box = dcn35_update_bw_bounding_box_fpu,
1798
+
.update_bw_bounding_box = dcn35_update_bw_bounding_box,
1807
1799
.patch_unknown_plane_state = dcn35_patch_unknown_plane_state,
1808
1800
.get_panel_config_defaults = dcn35_get_panel_config_defaults,
1809
1801
.get_preferred_eng_id_dpia = dcn35_get_preferred_eng_id_dpia,
+1
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
+1
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
+9
-1
drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
+9
-1
drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
···
1718
1718
{
1719
1719
bool out = false;
1720
1720
1721
+
DC_FP_START();
1721
1722
out = dml2_validate(dc, context,
1722
1723
context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2,
1723
1724
validate_mode);
1725
+
DC_FP_END();
1724
1726
1725
1727
if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING)
1726
1728
return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
···
1749
1747
1750
1748
}
1751
1749
1750
+
static void dcn351_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1751
+
{
1752
+
DC_FP_START();
1753
+
dcn351_update_bw_bounding_box_fpu(dc, bw_params);
1754
+
DC_FP_END();
1755
+
}
1752
1756
static struct resource_funcs dcn351_res_pool_funcs = {
1753
1757
.destroy = dcn351_destroy_resource_pool,
1754
1758
.link_enc_create = dcn35_link_encoder_create,
···
1776
1768
.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1777
1769
.acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1778
1770
.release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1779
-
.update_bw_bounding_box = dcn351_update_bw_bounding_box_fpu,
1771
+
.update_bw_bounding_box = dcn351_update_bw_bounding_box,
1780
1772
.patch_unknown_plane_state = dcn35_patch_unknown_plane_state,
1781
1773
.get_panel_config_defaults = dcn35_get_panel_config_defaults,
1782
1774
.get_preferred_eng_id_dpia = dcn351_get_preferred_eng_id_dpia,
+3
-1
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
+3
-1
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
···
1725
1725
{
1726
1726
bool out = false;
1727
1727
1728
+
DC_FP_START();
1728
1729
out = dml2_validate(dc, context,
1729
1730
context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2,
1730
1731
validate_mode);
1732
+
DC_FP_END();
1731
1733
1732
1734
if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING)
1733
1735
return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
···
1777
1775
.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1778
1776
.acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1779
1777
.release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1780
-
.update_bw_bounding_box = dcn35_update_bw_bounding_box_fpu,
1778
+
.update_bw_bounding_box = dcn35_update_bw_bounding_box,
1781
1779
.patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1782
1780
.get_panel_config_defaults = dcn35_get_panel_config_defaults,
1783
1781
.get_preferred_eng_id_dpia = dcn36_get_preferred_eng_id_dpia,
+23
-9
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
+23
-9
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
···
1643
1643
.get_subvp_en = dcn32_subvp_in_use,
1644
1644
};
1645
1645
1646
-
static void dcn401_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1646
+
static void dcn401_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params)
1647
1647
{
1648
+
dc_assert_fp_enabled();
1649
+
1648
1650
/* re-calculate the available MALL size if required */
1649
1651
if (bw_params->num_channels > 0) {
1650
1652
dc->caps.max_cab_allocation_bytes = dcn401_calc_num_avail_chans_for_mall(
···
1655
1653
dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes;
1656
1654
}
1657
1655
1658
-
DC_FP_START();
1659
-
1660
1656
if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2)
1661
1657
dml2_reinit(dc, &dc->dml2_options, &dc->current_state->bw_ctx.dml2);
1662
1658
1663
1659
if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2_dc_power_source)
1664
1660
dml2_reinit(dc, &dc->dml2_dc_power_options, &dc->current_state->bw_ctx.dml2_dc_power_source);
1665
-
1666
-
DC_FP_END();
1667
1661
}
1668
1662
1663
+
static void dcn401_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1664
+
{
1665
+
DC_FP_START();
1666
+
dcn401_update_bw_bounding_box_fpu(dc, bw_params);
1667
+
DC_FP_END();
1668
+
}
1669
1669
enum dc_status dcn401_patch_unknown_plane_state(struct dc_plane_state *plane_state)
1670
1670
{
1671
1671
plane_state->tiling_info.gfxversion = DcGfxAddr3;
···
1692
1688
}
1693
1689
}
1694
1690
1695
-
if (dc->debug.using_dml2)
1691
+
if (dc->debug.using_dml2) {
1692
+
DC_FP_START();
1696
1693
status = dml2_validate(dc, context,
1697
1694
context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2,
1698
1695
validate_mode) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1696
+
DC_FP_END();
1697
+
}
1699
1698
1700
1699
if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING && status == DC_OK && dc_state_is_subvp_in_use(context)) {
1701
1700
/* check new stream configuration still supports cursor if subvp used */
···
1717
1710
1718
1711
if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING && status == DC_FAIL_HW_CURSOR_SUPPORT) {
1719
1712
/* attempt to validate again with subvp disabled due to cursor */
1720
-
if (dc->debug.using_dml2)
1713
+
if (dc->debug.using_dml2) {
1714
+
DC_FP_START();
1721
1715
status = dml2_validate(dc, context,
1722
1716
context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2,
1723
1717
validate_mode) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1718
+
DC_FP_END();
1719
+
}
1724
1720
}
1725
1721
1726
1722
return status;
···
1732
1722
void dcn401_prepare_mcache_programming(struct dc *dc,
1733
1723
struct dc_state *context)
1734
1724
{
1735
-
if (dc->debug.using_dml21)
1725
+
if (dc->debug.using_dml21) {
1726
+
DC_FP_START();
1736
1727
dml2_prepare_mcache_programming(dc, context,
1737
-
context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2);
1728
+
context->power_source == DC_POWER_SOURCE_DC ?
1729
+
context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2);
1730
+
DC_FP_END();
1731
+
}
1738
1732
}
1739
1733
1740
1734
static void dcn401_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx)
+19
-6
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
+19
-6
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
···
1696
1696
static struct dc_cap_funcs cap_funcs = {
1697
1697
.get_dcc_compression_cap = dcn20_get_dcc_compression_cap};
1698
1698
1699
+
static void dcn42_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params)
1700
+
{
1701
+
dc_assert_fp_enabled();
1702
+
1703
+
if (dc->current_state && dc->current_state->bw_ctx.dml2)
1704
+
dml2_reinit(dc, &dc->dml2_options, &dc->current_state->bw_ctx.dml2);
1705
+
}
1706
+
1699
1707
static void dcn42_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1700
1708
{
1701
1709
DC_FP_START();
1702
-
if (dc->current_state && dc->current_state->bw_ctx.dml2)
1703
-
dml2_reinit(dc, &dc->dml2_options, &dc->current_state->bw_ctx.dml2);
1710
+
dcn42_update_bw_bounding_box_fpu(dc, bw_params);
1704
1711
DC_FP_END();
1705
1712
}
1706
-
1707
1713
enum dc_status dcn42_validate_bandwidth(struct dc *dc,
1708
1714
struct dc_state *context,
1709
1715
enum dc_validate_mode validate_mode)
1710
1716
{
1711
1717
bool out = false;
1712
1718
1719
+
DC_FP_START();
1720
+
1713
1721
out = dml2_validate(dc, context, context->bw_ctx.dml2,
1714
1722
validate_mode);
1715
-
DC_FP_START();
1723
+
1716
1724
if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING) {
1717
1725
/*not required for mode enumeration*/
1718
1726
dcn42_decide_zstate_support(dc, context);
1719
1727
}
1728
+
1720
1729
DC_FP_END();
1730
+
1721
1731
return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1722
1732
}
1723
1733
void dcn42_prepare_mcache_programming(struct dc *dc,
1724
1734
struct dc_state *context)
1725
1735
{
1726
-
if (dc->debug.using_dml21)
1736
+
if (dc->debug.using_dml21) {
1737
+
DC_FP_START();
1727
1738
dml2_prepare_mcache_programming(dc, context,
1728
1739
context->power_source == DC_POWER_SOURCE_DC ?
1729
-
context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2);
1740
+
context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2);
1741
+
DC_FP_END();
1742
+
}
1730
1743
}
1731
1744
/* Create a minimal link encoder object not associated with a particular
1732
1745
* physical connector.