Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
phy: qcom-qmp-ufs: Add Milos support
Add the init sequence tables and config for the UFS QMP phy found in the
Milos SoC.
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patch.msgid.link/20260112-milos-ufs-v2-4-d3ce4f61f030@fairphone.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
Luca Weiss
and committed by
Vinod Koul
3554ded4
ed0a26aa
+96
+96
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+96
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
···
84
84
[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_UFS_POWER_DOWN_CONTROL,
85
85
};
86
86
87
+
static const struct qmp_phy_init_tbl milos_ufsphy_serdes[] = {
88
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9),
89
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
90
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
91
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
92
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
93
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
94
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x0a),
95
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x17),
96
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
97
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0e),
98
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
99
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x82),
100
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x14),
101
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
102
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x18),
103
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0xff),
104
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0c),
105
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x98),
106
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x14),
107
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
108
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x18),
109
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x32),
110
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x0f),
111
+
};
112
+
113
+
static const struct qmp_phy_init_tbl milos_ufsphy_tx[] = {
114
+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x05),
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+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
116
+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
117
+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_FR_DCC_CTRL, 0xcc),
118
+
};
119
+
120
+
static const struct qmp_phy_init_tbl milos_ufsphy_rx[] = {
121
+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c),
122
+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x3e),
123
+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
124
+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xce),
125
+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xce),
126
+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B2, 0x18),
127
+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3, 0x1a),
128
+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B4, 0x0f),
129
+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6, 0x60),
130
+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B3, 0x9e),
131
+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B6, 0x60),
132
+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B3, 0x9e),
133
+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B4, 0x0e),
134
+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B5, 0x36),
135
+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02),
136
+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CTRL1, 0x94),
137
+
};
138
+
139
+
static const struct qmp_phy_init_tbl milos_ufsphy_pcs[] = {
140
+
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
141
+
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
142
+
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x0b),
143
+
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
144
+
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x68),
145
+
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),
146
+
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),
147
+
};
148
+
87
149
static const struct qmp_phy_init_tbl msm8996_ufsphy_serdes[] = {
88
150
QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
89
151
QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
···
1227
1165
}
1228
1166
1229
1167
/* Regulator bulk data with load values for specific configurations */
1168
+
static const struct regulator_bulk_data milos_ufsphy_vreg_l[] = {
1169
+
{ .supply = "vdda-phy", .init_load_uA = 140120 },
1170
+
{ .supply = "vdda-pll", .init_load_uA = 18340 },
1171
+
};
1172
+
1230
1173
static const struct regulator_bulk_data msm8996_ufsphy_vreg_l[] = {
1231
1174
{ .supply = "vdda-phy", .init_load_uA = 51400 },
1232
1175
{ .supply = "vdda-pll", .init_load_uA = 14600 },
···
1323
1256
.rx = 0x1200,
1324
1257
.tx2 = 0x1800,
1325
1258
.rx2 = 0x1a00,
1259
+
};
1260
+
1261
+
static const struct qmp_phy_cfg milos_ufsphy_cfg = {
1262
+
.lanes = 2,
1263
+
1264
+
.offsets = &qmp_ufs_offsets_v6,
1265
+
.max_supported_gear = UFS_HS_G4,
1266
+
1267
+
.tbls = {
1268
+
.serdes = milos_ufsphy_serdes,
1269
+
.serdes_num = ARRAY_SIZE(milos_ufsphy_serdes),
1270
+
.tx = milos_ufsphy_tx,
1271
+
.tx_num = ARRAY_SIZE(milos_ufsphy_tx),
1272
+
.rx = milos_ufsphy_rx,
1273
+
.rx_num = ARRAY_SIZE(milos_ufsphy_rx),
1274
+
.pcs = milos_ufsphy_pcs,
1275
+
.pcs_num = ARRAY_SIZE(milos_ufsphy_pcs),
1276
+
},
1277
+
.tbls_hs_b = {
1278
+
.serdes = sm8550_ufsphy_hs_b_serdes,
1279
+
.serdes_num = ARRAY_SIZE(sm8550_ufsphy_hs_b_serdes),
1280
+
},
1281
+
1282
+
.vreg_list = milos_ufsphy_vreg_l,
1283
+
.num_vregs = ARRAY_SIZE(milos_ufsphy_vreg_l),
1284
+
.regs = ufsphy_v6_regs_layout,
1326
1285
};
1327
1286
1328
1287
static const struct qmp_phy_cfg msm8996_ufsphy_cfg = {
···
2259
2166
2260
2167
static const struct of_device_id qmp_ufs_of_match_table[] = {
2261
2168
{
2169
+
.compatible = "qcom,milos-qmp-ufs-phy",
2170
+
.data = &milos_ufsphy_cfg,
2171
+
}, {
2262
2172
.compatible = "qcom,msm8996-qmp-ufs-phy",
2263
2173
.data = &msm8996_ufsphy_cfg,
2264
2174
}, {