tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

drm/panel: panel-jadard-jd9365da-h3: use wrapped MIPI DCS functions

Remove conditional code and always use mipi_dsi_dcs_*multi() wrappers to
simplify driver's init/enable/exit code.

Signed-off-by: Zhaoxiong Lv <lvzhaoxiong@huaqin.corp-partner.google.com>
Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240624141926.5250-4-lvzhaoxiong@huaqin.corp-partner.google.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20240624141926.5250-4-lvzhaoxiong@huaqin.corp-partner.google.com

authored by

Zhaoxiong Lv and committed by
Neil Armstrong 35583e12 e7f5112a

+390 -403
+390 -403
drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c
··· 19 19 #include <linux/of.h> 20 20 #include <linux/regulator/consumer.h> 21 21 22 - #define JD9365DA_INIT_CMD_LEN 2 23 - 24 - struct jadard_init_cmd { 25 - u8 data[JD9365DA_INIT_CMD_LEN]; 26 - }; 22 + struct jadard; 27 23 28 24 struct jadard_panel_desc { 29 25 const struct drm_display_mode mode; 30 26 unsigned int lanes; 31 27 enum mipi_dsi_pixel_format format; 32 - const struct jadard_init_cmd *init_cmds; 28 + int (*init)(struct jadard *jadard); 33 29 u32 num_init_cmds; 34 30 }; 35 31 ··· 46 50 47 51 static int jadard_enable(struct drm_panel *panel) 48 52 { 49 - struct device *dev = panel->dev; 50 53 struct jadard *jadard = panel_to_jadard(panel); 51 - struct mipi_dsi_device *dsi = jadard->dsi; 52 - int err; 54 + struct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi }; 53 55 54 56 msleep(120); 55 57 56 - err = mipi_dsi_dcs_exit_sleep_mode(dsi); 57 - if (err < 0) 58 - DRM_DEV_ERROR(dev, "failed to exit sleep mode ret = %d\n", err); 58 + mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); 59 59 60 - err = mipi_dsi_dcs_set_display_on(dsi); 61 - if (err < 0) 62 - DRM_DEV_ERROR(dev, "failed to set display on ret = %d\n", err); 60 + mipi_dsi_dcs_set_display_on_multi(&dsi_ctx); 63 61 64 - return 0; 62 + return dsi_ctx.accum_err; 65 63 } 66 64 67 65 static int jadard_disable(struct drm_panel *panel) 68 66 { 69 - struct device *dev = panel->dev; 70 67 struct jadard *jadard = panel_to_jadard(panel); 71 - int ret; 68 + struct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi }; 72 69 73 - ret = mipi_dsi_dcs_set_display_off(jadard->dsi); 74 - if (ret < 0) 75 - DRM_DEV_ERROR(dev, "failed to set display off: %d\n", ret); 70 + mipi_dsi_dcs_set_display_off_multi(&dsi_ctx); 76 71 77 - ret = mipi_dsi_dcs_enter_sleep_mode(jadard->dsi); 78 - if (ret < 0) 79 - DRM_DEV_ERROR(dev, "failed to enter sleep mode: %d\n", ret); 72 + mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx); 80 73 81 - return 0; 74 + return dsi_ctx.accum_err; 82 75 } 83 76 84 77 static int jadard_prepare(struct drm_panel *panel) 85 78 { 86 79 struct jadard *jadard = panel_to_jadard(panel); 87 - const struct jadard_panel_desc *desc = jadard->desc; 88 - unsigned int i; 89 80 int ret; 90 81 91 82 ret = regulator_enable(jadard->vccio); ··· 92 109 gpiod_set_value(jadard->reset, 1); 93 110 msleep(130); 94 111 95 - for (i = 0; i < desc->num_init_cmds; i++) { 96 - const struct jadard_init_cmd *cmd = &desc->init_cmds[i]; 97 - 98 - ret = mipi_dsi_dcs_write_buffer(dsi, cmd->data, JD9365DA_INIT_CMD_LEN); 99 - if (ret < 0) 100 - return ret; 101 - } 112 + ret = jadard->desc->init(jadard); 113 + if (ret) 114 + return ret; 102 115 103 116 return 0; 104 117 } ··· 144 165 .get_modes = jadard_get_modes, 145 166 }; 146 167 147 - static const struct jadard_init_cmd radxa_display_8hd_ad002_init_cmds[] = { 148 - { .data = { 0xE0, 0x00 } }, 149 - { .data = { 0xE1, 0x93 } }, 150 - { .data = { 0xE2, 0x65 } }, 151 - { .data = { 0xE3, 0xF8 } }, 152 - { .data = { 0x80, 0x03 } }, 153 - { .data = { 0xE0, 0x01 } }, 154 - { .data = { 0x00, 0x00 } }, 155 - { .data = { 0x01, 0x7E } }, 156 - { .data = { 0x03, 0x00 } }, 157 - { .data = { 0x04, 0x65 } }, 158 - { .data = { 0x0C, 0x74 } }, 159 - { .data = { 0x17, 0x00 } }, 160 - { .data = { 0x18, 0xB7 } }, 161 - { .data = { 0x19, 0x00 } }, 162 - { .data = { 0x1A, 0x00 } }, 163 - { .data = { 0x1B, 0xB7 } }, 164 - { .data = { 0x1C, 0x00 } }, 165 - { .data = { 0x24, 0xFE } }, 166 - { .data = { 0x37, 0x19 } }, 167 - { .data = { 0x38, 0x05 } }, 168 - { .data = { 0x39, 0x00 } }, 169 - { .data = { 0x3A, 0x01 } }, 170 - { .data = { 0x3B, 0x01 } }, 171 - { .data = { 0x3C, 0x70 } }, 172 - { .data = { 0x3D, 0xFF } }, 173 - { .data = { 0x3E, 0xFF } }, 174 - { .data = { 0x3F, 0xFF } }, 175 - { .data = { 0x40, 0x06 } }, 176 - { .data = { 0x41, 0xA0 } }, 177 - { .data = { 0x43, 0x1E } }, 178 - { .data = { 0x44, 0x0F } }, 179 - { .data = { 0x45, 0x28 } }, 180 - { .data = { 0x4B, 0x04 } }, 181 - { .data = { 0x55, 0x02 } }, 182 - { .data = { 0x56, 0x01 } }, 183 - { .data = { 0x57, 0xA9 } }, 184 - { .data = { 0x58, 0x0A } }, 185 - { .data = { 0x59, 0x0A } }, 186 - { .data = { 0x5A, 0x37 } }, 187 - { .data = { 0x5B, 0x19 } }, 188 - { .data = { 0x5D, 0x78 } }, 189 - { .data = { 0x5E, 0x63 } }, 190 - { .data = { 0x5F, 0x54 } }, 191 - { .data = { 0x60, 0x49 } }, 192 - { .data = { 0x61, 0x45 } }, 193 - { .data = { 0x62, 0x38 } }, 194 - { .data = { 0x63, 0x3D } }, 195 - { .data = { 0x64, 0x28 } }, 196 - { .data = { 0x65, 0x43 } }, 197 - { .data = { 0x66, 0x41 } }, 198 - { .data = { 0x67, 0x43 } }, 199 - { .data = { 0x68, 0x62 } }, 200 - { .data = { 0x69, 0x50 } }, 201 - { .data = { 0x6A, 0x57 } }, 202 - { .data = { 0x6B, 0x49 } }, 203 - { .data = { 0x6C, 0x44 } }, 204 - { .data = { 0x6D, 0x37 } }, 205 - { .data = { 0x6E, 0x23 } }, 206 - { .data = { 0x6F, 0x10 } }, 207 - { .data = { 0x70, 0x78 } }, 208 - { .data = { 0x71, 0x63 } }, 209 - { .data = { 0x72, 0x54 } }, 210 - { .data = { 0x73, 0x49 } }, 211 - { .data = { 0x74, 0x45 } }, 212 - { .data = { 0x75, 0x38 } }, 213 - { .data = { 0x76, 0x3D } }, 214 - { .data = { 0x77, 0x28 } }, 215 - { .data = { 0x78, 0x43 } }, 216 - { .data = { 0x79, 0x41 } }, 217 - { .data = { 0x7A, 0x43 } }, 218 - { .data = { 0x7B, 0x62 } }, 219 - { .data = { 0x7C, 0x50 } }, 220 - { .data = { 0x7D, 0x57 } }, 221 - { .data = { 0x7E, 0x49 } }, 222 - { .data = { 0x7F, 0x44 } }, 223 - { .data = { 0x80, 0x37 } }, 224 - { .data = { 0x81, 0x23 } }, 225 - { .data = { 0x82, 0x10 } }, 226 - { .data = { 0xE0, 0x02 } }, 227 - { .data = { 0x00, 0x47 } }, 228 - { .data = { 0x01, 0x47 } }, 229 - { .data = { 0x02, 0x45 } }, 230 - { .data = { 0x03, 0x45 } }, 231 - { .data = { 0x04, 0x4B } }, 232 - { .data = { 0x05, 0x4B } }, 233 - { .data = { 0x06, 0x49 } }, 234 - { .data = { 0x07, 0x49 } }, 235 - { .data = { 0x08, 0x41 } }, 236 - { .data = { 0x09, 0x1F } }, 237 - { .data = { 0x0A, 0x1F } }, 238 - { .data = { 0x0B, 0x1F } }, 239 - { .data = { 0x0C, 0x1F } }, 240 - { .data = { 0x0D, 0x1F } }, 241 - { .data = { 0x0E, 0x1F } }, 242 - { .data = { 0x0F, 0x5F } }, 243 - { .data = { 0x10, 0x5F } }, 244 - { .data = { 0x11, 0x57 } }, 245 - { .data = { 0x12, 0x77 } }, 246 - { .data = { 0x13, 0x35 } }, 247 - { .data = { 0x14, 0x1F } }, 248 - { .data = { 0x15, 0x1F } }, 249 - { .data = { 0x16, 0x46 } }, 250 - { .data = { 0x17, 0x46 } }, 251 - { .data = { 0x18, 0x44 } }, 252 - { .data = { 0x19, 0x44 } }, 253 - { .data = { 0x1A, 0x4A } }, 254 - { .data = { 0x1B, 0x4A } }, 255 - { .data = { 0x1C, 0x48 } }, 256 - { .data = { 0x1D, 0x48 } }, 257 - { .data = { 0x1E, 0x40 } }, 258 - { .data = { 0x1F, 0x1F } }, 259 - { .data = { 0x20, 0x1F } }, 260 - { .data = { 0x21, 0x1F } }, 261 - { .data = { 0x22, 0x1F } }, 262 - { .data = { 0x23, 0x1F } }, 263 - { .data = { 0x24, 0x1F } }, 264 - { .data = { 0x25, 0x5F } }, 265 - { .data = { 0x26, 0x5F } }, 266 - { .data = { 0x27, 0x57 } }, 267 - { .data = { 0x28, 0x77 } }, 268 - { .data = { 0x29, 0x35 } }, 269 - { .data = { 0x2A, 0x1F } }, 270 - { .data = { 0x2B, 0x1F } }, 271 - { .data = { 0x58, 0x40 } }, 272 - { .data = { 0x59, 0x00 } }, 273 - { .data = { 0x5A, 0x00 } }, 274 - { .data = { 0x5B, 0x10 } }, 275 - { .data = { 0x5C, 0x06 } }, 276 - { .data = { 0x5D, 0x40 } }, 277 - { .data = { 0x5E, 0x01 } }, 278 - { .data = { 0x5F, 0x02 } }, 279 - { .data = { 0x60, 0x30 } }, 280 - { .data = { 0x61, 0x01 } }, 281 - { .data = { 0x62, 0x02 } }, 282 - { .data = { 0x63, 0x03 } }, 283 - { .data = { 0x64, 0x6B } }, 284 - { .data = { 0x65, 0x05 } }, 285 - { .data = { 0x66, 0x0C } }, 286 - { .data = { 0x67, 0x73 } }, 287 - { .data = { 0x68, 0x09 } }, 288 - { .data = { 0x69, 0x03 } }, 289 - { .data = { 0x6A, 0x56 } }, 290 - { .data = { 0x6B, 0x08 } }, 291 - { .data = { 0x6C, 0x00 } }, 292 - { .data = { 0x6D, 0x04 } }, 293 - { .data = { 0x6E, 0x04 } }, 294 - { .data = { 0x6F, 0x88 } }, 295 - { .data = { 0x70, 0x00 } }, 296 - { .data = { 0x71, 0x00 } }, 297 - { .data = { 0x72, 0x06 } }, 298 - { .data = { 0x73, 0x7B } }, 299 - { .data = { 0x74, 0x00 } }, 300 - { .data = { 0x75, 0xF8 } }, 301 - { .data = { 0x76, 0x00 } }, 302 - { .data = { 0x77, 0xD5 } }, 303 - { .data = { 0x78, 0x2E } }, 304 - { .data = { 0x79, 0x12 } }, 305 - { .data = { 0x7A, 0x03 } }, 306 - { .data = { 0x7B, 0x00 } }, 307 - { .data = { 0x7C, 0x00 } }, 308 - { .data = { 0x7D, 0x03 } }, 309 - { .data = { 0x7E, 0x7B } }, 310 - { .data = { 0xE0, 0x04 } }, 311 - { .data = { 0x00, 0x0E } }, 312 - { .data = { 0x02, 0xB3 } }, 313 - { .data = { 0x09, 0x60 } }, 314 - { .data = { 0x0E, 0x2A } }, 315 - { .data = { 0x36, 0x59 } }, 316 - { .data = { 0xE0, 0x00 } }, 168 + static int radxa_display_8hd_ad002_init_cmds(struct jadard *jadard) 169 + { 170 + struct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi }; 171 + 172 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x00); 173 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE1, 0x93); 174 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE2, 0x65); 175 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE3, 0xF8); 176 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x03); 177 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x01); 178 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x00); 179 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x7E); 180 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x00); 181 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x65); 182 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0C, 0x74); 183 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x00); 184 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0xB7); 185 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x00); 186 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1A, 0x00); 187 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1B, 0xB7); 188 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1C, 0x00); 189 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0xFE); 190 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x19); 191 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x05); 192 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x00); 193 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3A, 0x01); 194 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3B, 0x01); 195 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3C, 0x70); 196 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3D, 0xFF); 197 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3E, 0xFF); 198 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3F, 0xFF); 199 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x06); 200 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0xA0); 201 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x1E); 202 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x0F); 203 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x28); 204 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4B, 0x04); 205 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x02); 206 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0x01); 207 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0xA9); 208 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x0A); 209 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x0A); 210 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5A, 0x37); 211 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5B, 0x19); 212 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5D, 0x78); 213 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5E, 0x63); 214 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5F, 0x54); 215 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x49); 216 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x45); 217 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x38); 218 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x3D); 219 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x28); 220 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x43); 221 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x41); 222 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x43); 223 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x62); 224 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x50); 225 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6A, 0x57); 226 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6B, 0x49); 227 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6C, 0x44); 228 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6D, 0x37); 229 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6E, 0x23); 230 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6F, 0x10); 231 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x78); 232 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x63); 233 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x54); 234 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x49); 235 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x45); 236 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x38); 237 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x3D); 238 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x28); 239 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x43); 240 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x41); 241 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7A, 0x43); 242 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7B, 0x62); 243 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7C, 0x50); 244 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7D, 0x57); 245 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7E, 0x49); 246 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7F, 0x44); 247 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x37); 248 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x23); 249 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x82, 0x10); 250 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x02); 251 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x47); 252 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x47); 253 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x45); 254 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x45); 255 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x4B); 256 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x4B); 257 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x49); 258 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x49); 259 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x41); 260 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x1F); 261 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0A, 0x1F); 262 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0B, 0x1F); 263 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0C, 0x1F); 264 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0D, 0x1F); 265 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0E, 0x1F); 266 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0F, 0x5F); 267 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x10, 0x5F); 268 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x11, 0x57); 269 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x12, 0x77); 270 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x13, 0x35); 271 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x14, 0x1F); 272 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x1F); 273 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x46); 274 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x46); 275 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x44); 276 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x44); 277 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1A, 0x4A); 278 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1B, 0x4A); 279 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1C, 0x48); 280 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1D, 0x48); 281 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1E, 0x40); 282 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1F, 0x1F); 283 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x1F); 284 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x1F); 285 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x1F); 286 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x23, 0x1F); 287 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0x1F); 288 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x25, 0x5F); 289 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x26, 0x5F); 290 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x27, 0x57); 291 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x28, 0x77); 292 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x29, 0x35); 293 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2A, 0x1F); 294 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2B, 0x1F); 295 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x40); 296 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x00); 297 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5A, 0x00); 298 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5B, 0x10); 299 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5C, 0x06); 300 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5D, 0x40); 301 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5E, 0x01); 302 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5F, 0x02); 303 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x30); 304 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x01); 305 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x02); 306 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x03); 307 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x6B); 308 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x05); 309 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x0C); 310 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x73); 311 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x09); 312 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x03); 313 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6A, 0x56); 314 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6B, 0x08); 315 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6C, 0x00); 316 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6D, 0x04); 317 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6E, 0x04); 318 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6F, 0x88); 319 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x00); 320 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x00); 321 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x06); 322 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x7B); 323 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x00); 324 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0xF8); 325 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x00); 326 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0xD5); 327 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x2E); 328 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x12); 329 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7A, 0x03); 330 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7B, 0x00); 331 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7C, 0x00); 332 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7D, 0x03); 333 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7E, 0x7B); 334 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x04); 335 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x0E); 336 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0xB3); 337 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x60); 338 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0E, 0x2A); 339 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x59); 340 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x00); 341 + 342 + return dsi_ctx.accum_err; 317 343 }; 318 344 319 345 static const struct jadard_panel_desc radxa_display_8hd_ad002_desc = { ··· 341 357 }, 342 358 .lanes = 4, 343 359 .format = MIPI_DSI_FMT_RGB888, 344 - .init_cmds = radxa_display_8hd_ad002_init_cmds, 345 - .num_init_cmds = ARRAY_SIZE(radxa_display_8hd_ad002_init_cmds), 360 + .init = radxa_display_8hd_ad002_init_cmds, 346 361 }; 347 362 348 - static const struct jadard_init_cmd cz101b4001_init_cmds[] = { 349 - { .data = { 0xE0, 0x00 } }, 350 - { .data = { 0xE1, 0x93 } }, 351 - { .data = { 0xE2, 0x65 } }, 352 - { .data = { 0xE3, 0xF8 } }, 353 - { .data = { 0x80, 0x03 } }, 354 - { .data = { 0xE0, 0x01 } }, 355 - { .data = { 0x00, 0x00 } }, 356 - { .data = { 0x01, 0x3B } }, 357 - { .data = { 0x0C, 0x74 } }, 358 - { .data = { 0x17, 0x00 } }, 359 - { .data = { 0x18, 0xAF } }, 360 - { .data = { 0x19, 0x00 } }, 361 - { .data = { 0x1A, 0x00 } }, 362 - { .data = { 0x1B, 0xAF } }, 363 - { .data = { 0x1C, 0x00 } }, 364 - { .data = { 0x35, 0x26 } }, 365 - { .data = { 0x37, 0x09 } }, 366 - { .data = { 0x38, 0x04 } }, 367 - { .data = { 0x39, 0x00 } }, 368 - { .data = { 0x3A, 0x01 } }, 369 - { .data = { 0x3C, 0x78 } }, 370 - { .data = { 0x3D, 0xFF } }, 371 - { .data = { 0x3E, 0xFF } }, 372 - { .data = { 0x3F, 0x7F } }, 373 - { .data = { 0x40, 0x06 } }, 374 - { .data = { 0x41, 0xA0 } }, 375 - { .data = { 0x42, 0x81 } }, 376 - { .data = { 0x43, 0x14 } }, 377 - { .data = { 0x44, 0x23 } }, 378 - { .data = { 0x45, 0x28 } }, 379 - { .data = { 0x55, 0x02 } }, 380 - { .data = { 0x57, 0x69 } }, 381 - { .data = { 0x59, 0x0A } }, 382 - { .data = { 0x5A, 0x2A } }, 383 - { .data = { 0x5B, 0x17 } }, 384 - { .data = { 0x5D, 0x7F } }, 385 - { .data = { 0x5E, 0x6B } }, 386 - { .data = { 0x5F, 0x5C } }, 387 - { .data = { 0x60, 0x4F } }, 388 - { .data = { 0x61, 0x4D } }, 389 - { .data = { 0x62, 0x3F } }, 390 - { .data = { 0x63, 0x42 } }, 391 - { .data = { 0x64, 0x2B } }, 392 - { .data = { 0x65, 0x44 } }, 393 - { .data = { 0x66, 0x43 } }, 394 - { .data = { 0x67, 0x43 } }, 395 - { .data = { 0x68, 0x63 } }, 396 - { .data = { 0x69, 0x52 } }, 397 - { .data = { 0x6A, 0x5A } }, 398 - { .data = { 0x6B, 0x4F } }, 399 - { .data = { 0x6C, 0x4E } }, 400 - { .data = { 0x6D, 0x20 } }, 401 - { .data = { 0x6E, 0x0F } }, 402 - { .data = { 0x6F, 0x00 } }, 403 - { .data = { 0x70, 0x7F } }, 404 - { .data = { 0x71, 0x6B } }, 405 - { .data = { 0x72, 0x5C } }, 406 - { .data = { 0x73, 0x4F } }, 407 - { .data = { 0x74, 0x4D } }, 408 - { .data = { 0x75, 0x3F } }, 409 - { .data = { 0x76, 0x42 } }, 410 - { .data = { 0x77, 0x2B } }, 411 - { .data = { 0x78, 0x44 } }, 412 - { .data = { 0x79, 0x43 } }, 413 - { .data = { 0x7A, 0x43 } }, 414 - { .data = { 0x7B, 0x63 } }, 415 - { .data = { 0x7C, 0x52 } }, 416 - { .data = { 0x7D, 0x5A } }, 417 - { .data = { 0x7E, 0x4F } }, 418 - { .data = { 0x7F, 0x4E } }, 419 - { .data = { 0x80, 0x20 } }, 420 - { .data = { 0x81, 0x0F } }, 421 - { .data = { 0x82, 0x00 } }, 422 - { .data = { 0xE0, 0x02 } }, 423 - { .data = { 0x00, 0x02 } }, 424 - { .data = { 0x01, 0x02 } }, 425 - { .data = { 0x02, 0x00 } }, 426 - { .data = { 0x03, 0x00 } }, 427 - { .data = { 0x04, 0x1E } }, 428 - { .data = { 0x05, 0x1E } }, 429 - { .data = { 0x06, 0x1F } }, 430 - { .data = { 0x07, 0x1F } }, 431 - { .data = { 0x08, 0x1F } }, 432 - { .data = { 0x09, 0x17 } }, 433 - { .data = { 0x0A, 0x17 } }, 434 - { .data = { 0x0B, 0x37 } }, 435 - { .data = { 0x0C, 0x37 } }, 436 - { .data = { 0x0D, 0x47 } }, 437 - { .data = { 0x0E, 0x47 } }, 438 - { .data = { 0x0F, 0x45 } }, 439 - { .data = { 0x10, 0x45 } }, 440 - { .data = { 0x11, 0x4B } }, 441 - { .data = { 0x12, 0x4B } }, 442 - { .data = { 0x13, 0x49 } }, 443 - { .data = { 0x14, 0x49 } }, 444 - { .data = { 0x15, 0x1F } }, 445 - { .data = { 0x16, 0x01 } }, 446 - { .data = { 0x17, 0x01 } }, 447 - { .data = { 0x18, 0x00 } }, 448 - { .data = { 0x19, 0x00 } }, 449 - { .data = { 0x1A, 0x1E } }, 450 - { .data = { 0x1B, 0x1E } }, 451 - { .data = { 0x1C, 0x1F } }, 452 - { .data = { 0x1D, 0x1F } }, 453 - { .data = { 0x1E, 0x1F } }, 454 - { .data = { 0x1F, 0x17 } }, 455 - { .data = { 0x20, 0x17 } }, 456 - { .data = { 0x21, 0x37 } }, 457 - { .data = { 0x22, 0x37 } }, 458 - { .data = { 0x23, 0x46 } }, 459 - { .data = { 0x24, 0x46 } }, 460 - { .data = { 0x25, 0x44 } }, 461 - { .data = { 0x26, 0x44 } }, 462 - { .data = { 0x27, 0x4A } }, 463 - { .data = { 0x28, 0x4A } }, 464 - { .data = { 0x29, 0x48 } }, 465 - { .data = { 0x2A, 0x48 } }, 466 - { .data = { 0x2B, 0x1F } }, 467 - { .data = { 0x2C, 0x01 } }, 468 - { .data = { 0x2D, 0x01 } }, 469 - { .data = { 0x2E, 0x00 } }, 470 - { .data = { 0x2F, 0x00 } }, 471 - { .data = { 0x30, 0x1F } }, 472 - { .data = { 0x31, 0x1F } }, 473 - { .data = { 0x32, 0x1E } }, 474 - { .data = { 0x33, 0x1E } }, 475 - { .data = { 0x34, 0x1F } }, 476 - { .data = { 0x35, 0x17 } }, 477 - { .data = { 0x36, 0x17 } }, 478 - { .data = { 0x37, 0x37 } }, 479 - { .data = { 0x38, 0x37 } }, 480 - { .data = { 0x39, 0x08 } }, 481 - { .data = { 0x3A, 0x08 } }, 482 - { .data = { 0x3B, 0x0A } }, 483 - { .data = { 0x3C, 0x0A } }, 484 - { .data = { 0x3D, 0x04 } }, 485 - { .data = { 0x3E, 0x04 } }, 486 - { .data = { 0x3F, 0x06 } }, 487 - { .data = { 0x40, 0x06 } }, 488 - { .data = { 0x41, 0x1F } }, 489 - { .data = { 0x42, 0x02 } }, 490 - { .data = { 0x43, 0x02 } }, 491 - { .data = { 0x44, 0x00 } }, 492 - { .data = { 0x45, 0x00 } }, 493 - { .data = { 0x46, 0x1F } }, 494 - { .data = { 0x47, 0x1F } }, 495 - { .data = { 0x48, 0x1E } }, 496 - { .data = { 0x49, 0x1E } }, 497 - { .data = { 0x4A, 0x1F } }, 498 - { .data = { 0x4B, 0x17 } }, 499 - { .data = { 0x4C, 0x17 } }, 500 - { .data = { 0x4D, 0x37 } }, 501 - { .data = { 0x4E, 0x37 } }, 502 - { .data = { 0x4F, 0x09 } }, 503 - { .data = { 0x50, 0x09 } }, 504 - { .data = { 0x51, 0x0B } }, 505 - { .data = { 0x52, 0x0B } }, 506 - { .data = { 0x53, 0x05 } }, 507 - { .data = { 0x54, 0x05 } }, 508 - { .data = { 0x55, 0x07 } }, 509 - { .data = { 0x56, 0x07 } }, 510 - { .data = { 0x57, 0x1F } }, 511 - { .data = { 0x58, 0x40 } }, 512 - { .data = { 0x5B, 0x30 } }, 513 - { .data = { 0x5C, 0x16 } }, 514 - { .data = { 0x5D, 0x34 } }, 515 - { .data = { 0x5E, 0x05 } }, 516 - { .data = { 0x5F, 0x02 } }, 517 - { .data = { 0x63, 0x00 } }, 518 - { .data = { 0x64, 0x6A } }, 519 - { .data = { 0x67, 0x73 } }, 520 - { .data = { 0x68, 0x1D } }, 521 - { .data = { 0x69, 0x08 } }, 522 - { .data = { 0x6A, 0x6A } }, 523 - { .data = { 0x6B, 0x08 } }, 524 - { .data = { 0x6C, 0x00 } }, 525 - { .data = { 0x6D, 0x00 } }, 526 - { .data = { 0x6E, 0x00 } }, 527 - { .data = { 0x6F, 0x88 } }, 528 - { .data = { 0x75, 0xFF } }, 529 - { .data = { 0x77, 0xDD } }, 530 - { .data = { 0x78, 0x3F } }, 531 - { .data = { 0x79, 0x15 } }, 532 - { .data = { 0x7A, 0x17 } }, 533 - { .data = { 0x7D, 0x14 } }, 534 - { .data = { 0x7E, 0x82 } }, 535 - { .data = { 0xE0, 0x04 } }, 536 - { .data = { 0x00, 0x0E } }, 537 - { .data = { 0x02, 0xB3 } }, 538 - { .data = { 0x09, 0x61 } }, 539 - { .data = { 0x0E, 0x48 } }, 540 - { .data = { 0xE0, 0x00 } }, 541 - { .data = { 0xE6, 0x02 } }, 542 - { .data = { 0xE7, 0x0C } }, 363 + static int cz101b4001_init_cmds(struct jadard *jadard) 364 + { 365 + struct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi }; 366 + 367 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x00); 368 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE1, 0x93); 369 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE2, 0x65); 370 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE3, 0xF8); 371 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x03); 372 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x01); 373 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x00); 374 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x3B); 375 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0C, 0x74); 376 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x00); 377 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0xAF); 378 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x00); 379 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1A, 0x00); 380 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1B, 0xAF); 381 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1C, 0x00); 382 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x26); 383 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x09); 384 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x04); 385 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x00); 386 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3A, 0x01); 387 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3C, 0x78); 388 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3D, 0xFF); 389 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3E, 0xFF); 390 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3F, 0x7F); 391 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x06); 392 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0xA0); 393 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0x81); 394 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x14); 395 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x23); 396 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x28); 397 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x02); 398 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x69); 399 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x0A); 400 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5A, 0x2A); 401 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5B, 0x17); 402 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5D, 0x7F); 403 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5E, 0x6B); 404 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5F, 0x5C); 405 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x4F); 406 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x4D); 407 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x3F); 408 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x42); 409 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x2B); 410 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x44); 411 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x43); 412 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x43); 413 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x63); 414 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x52); 415 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6A, 0x5A); 416 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6B, 0x4F); 417 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6C, 0x4E); 418 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6D, 0x20); 419 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6E, 0x0F); 420 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6F, 0x00); 421 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x7F); 422 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x6B); 423 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x5C); 424 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x4F); 425 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x4D); 426 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x3F); 427 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x42); 428 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x2B); 429 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x44); 430 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x43); 431 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7A, 0x43); 432 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7B, 0x63); 433 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7C, 0x52); 434 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7D, 0x5A); 435 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7E, 0x4F); 436 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7F, 0x4E); 437 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x20); 438 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x0F); 439 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x82, 0x00); 440 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x02); 441 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x02); 442 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x02); 443 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x00); 444 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x00); 445 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x1E); 446 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x1E); 447 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x1F); 448 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x1F); 449 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x1F); 450 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x17); 451 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0A, 0x17); 452 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0B, 0x37); 453 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0C, 0x37); 454 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0D, 0x47); 455 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0E, 0x47); 456 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0F, 0x45); 457 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x10, 0x45); 458 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x11, 0x4B); 459 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x12, 0x4B); 460 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x13, 0x49); 461 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x14, 0x49); 462 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x1F); 463 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x01); 464 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x01); 465 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x00); 466 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x00); 467 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1A, 0x1E); 468 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1B, 0x1E); 469 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1C, 0x1F); 470 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1D, 0x1F); 471 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1E, 0x1F); 472 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1F, 0x17); 473 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x17); 474 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x37); 475 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x37); 476 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x23, 0x46); 477 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0x46); 478 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x25, 0x44); 479 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x26, 0x44); 480 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x27, 0x4A); 481 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x28, 0x4A); 482 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x29, 0x48); 483 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2A, 0x48); 484 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2B, 0x1F); 485 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2C, 0x01); 486 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2D, 0x01); 487 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2E, 0x00); 488 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2F, 0x00); 489 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x30, 0x1F); 490 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x31, 0x1F); 491 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x32, 0x1E); 492 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x33, 0x1E); 493 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x34, 0x1F); 494 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x17); 495 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x17); 496 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x37); 497 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x37); 498 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x08); 499 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3A, 0x08); 500 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3B, 0x0A); 501 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3C, 0x0A); 502 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3D, 0x04); 503 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3E, 0x04); 504 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3F, 0x06); 505 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x06); 506 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0x1F); 507 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0x02); 508 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x02); 509 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x00); 510 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x00); 511 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x46, 0x1F); 512 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x47, 0x1F); 513 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x48, 0x1E); 514 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x49, 0x1E); 515 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4A, 0x1F); 516 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4B, 0x17); 517 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4C, 0x17); 518 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4D, 0x37); 519 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4E, 0x37); 520 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4F, 0x09); 521 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x09); 522 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x51, 0x0B); 523 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x52, 0x0B); 524 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x53, 0x05); 525 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x54, 0x05); 526 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x07); 527 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0x07); 528 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x1F); 529 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x40); 530 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5B, 0x30); 531 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5C, 0x16); 532 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5D, 0x34); 533 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5E, 0x05); 534 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5F, 0x02); 535 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x00); 536 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x6A); 537 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x73); 538 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x1D); 539 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x08); 540 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6A, 0x6A); 541 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6B, 0x08); 542 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6C, 0x00); 543 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6D, 0x00); 544 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6E, 0x00); 545 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6F, 0x88); 546 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0xFF); 547 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0xDD); 548 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x3F); 549 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x15); 550 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7A, 0x17); 551 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7D, 0x14); 552 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7E, 0x82); 553 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x04); 554 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x0E); 555 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0xB3); 556 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x61); 557 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0E, 0x48); 558 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x00); 559 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE6, 0x02); 560 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE7, 0x0C); 561 + 562 + return dsi_ctx.accum_err; 543 563 }; 544 564 545 565 static const struct jadard_panel_desc cz101b4001_desc = { ··· 566 578 }, 567 579 .lanes = 4, 568 580 .format = MIPI_DSI_FMT_RGB888, 569 - .init_cmds = cz101b4001_init_cmds, 570 - .num_init_cmds = ARRAY_SIZE(cz101b4001_init_cmds), 581 + .init = cz101b4001_init_cmds, 571 582 }; 572 583 573 584 static int jadard_dsi_probe(struct mipi_dsi_device *dsi)