Merge tag 'tty-6.12-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty

+1

Documentation/devicetree/bindings/serial/8250_omap.yaml

··· 76 76 clock-frequency: true 77 77 current-speed: true 78 78 overrun-throttle-ms: true 79 + wakeup-source: true 79 80 80 81 required: 81 82 - compatible

+8 -1

Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml

··· 23 23 - const: atmel,at91sam9260-dbgu 24 24 - const: atmel,at91sam9260-usart 25 25 - items: 26 - - const: microchip,sam9x60-usart 26 + - enum: 27 + - microchip,sam9x60-usart 28 + - microchip,sam9x7-usart 27 29 - const: atmel,at91sam9260-usart 28 30 - items: 29 31 - const: microchip,sam9x60-dbgu 30 32 - const: microchip,sam9x60-usart 31 33 - const: atmel,at91sam9260-dbgu 34 + - const: atmel,at91sam9260-usart 35 + - items: 36 + - const: microchip,sam9x7-dbgu 37 + - const: atmel,at91sam9260-dbgu 38 + - const: microchip,sam9x7-usart 32 39 - const: atmel,at91sam9260-usart 33 40 34 41 reg:

+1

Documentation/devicetree/bindings/serial/mediatek,uart.yaml

··· 36 36 - mediatek,mt7622-uart 37 37 - mediatek,mt7623-uart 38 38 - mediatek,mt7629-uart 39 + - mediatek,mt7981-uart 39 40 - mediatek,mt7986-uart 40 41 - mediatek,mt7988-uart 41 42 - mediatek,mt8127-uart

+1

Documentation/devicetree/bindings/serial/renesas,scif.yaml

··· 46 46 - items: 47 47 - enum: 48 48 - renesas,scif-r8a774a1 # RZ/G2M 49 + - renesas,scif-r8a774a3 # RZ/G2M v3.0 49 50 - renesas,scif-r8a774b1 # RZ/G2N 50 51 - renesas,scif-r8a774c0 # RZ/G2E 51 52 - renesas,scif-r8a774e1 # RZ/G2H

+56 -14

Documentation/devicetree/bindings/serial/samsung_uart.yaml

··· 56 56 maxItems: 5 57 57 58 58 clock-names: 59 - description: N = 0 is allowed for SoCs without internal baud clock mux. 60 59 minItems: 2 61 - items: 62 - - const: uart 63 - - pattern: '^clk_uart_baud[0-3]$' 64 - - pattern: '^clk_uart_baud[0-3]$' 65 - - pattern: '^clk_uart_baud[0-3]$' 66 - - pattern: '^clk_uart_baud[0-3]$' 60 + maxItems: 5 67 61 68 62 dmas: 69 63 items: ··· 97 103 compatible: 98 104 contains: 99 105 enum: 100 - - samsung,s5pv210-uart 106 + - samsung,s3c6400-uart 101 107 then: 102 108 properties: 103 109 clocks: 104 - minItems: 2 110 + minItems: 3 105 111 maxItems: 3 112 + 113 + clock-names: 114 + items: 115 + - const: uart 116 + - const: clk_uart_baud2 117 + - const: clk_uart_baud3 118 + 119 + else: 120 + properties: 106 121 clock-names: 107 122 minItems: 2 108 123 items: 109 124 - const: uart 110 - - pattern: '^clk_uart_baud[0-1]$' 111 - - pattern: '^clk_uart_baud[0-1]$' 125 + - const: clk_uart_baud0 126 + - const: clk_uart_baud1 127 + - const: clk_uart_baud2 128 + - const: clk_uart_baud3 129 + 130 + - if: 131 + properties: 132 + compatible: 133 + contains: 134 + enum: 135 + - samsung,s5pv210-uart 136 + then: 137 + properties: 138 + clocks: 139 + minItems: 3 140 + maxItems: 3 141 + 142 + clock-names: 143 + minItems: 3 144 + maxItems: 3 112 145 113 146 - if: 114 147 properties: ··· 150 129 properties: 151 130 clocks: 152 131 maxItems: 2 132 + 153 133 clock-names: 154 - items: 155 - - const: uart 156 - - const: clk_uart_baud0 134 + maxItems: 2 157 135 158 136 - if: 159 137 properties: ··· 165 145 - samsung,uart-fifosize 166 146 properties: 167 147 reg-io-width: false 148 + 149 + clocks: 150 + maxItems: 2 151 + 152 + clock-names: 153 + maxItems: 2 168 154 169 155 unevaluatedProperties: false 170 156 ··· 188 162 clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>, 189 163 <&clocks SCLK_UART>; 190 164 samsung,uart-fifosize = <16>; 165 + }; 166 + - | 167 + #include <dt-bindings/clock/google,gs101.h> 168 + #include <dt-bindings/interrupt-controller/arm-gic.h> 169 + #include <dt-bindings/interrupt-controller/irq.h> 170 + 171 + serial_0: serial@10a00000 { 172 + compatible = "google,gs101-uart"; 173 + reg = <0x10a00000 0xc0>; 174 + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0>, 175 + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>; 176 + clock-names = "uart", "clk_uart_baud0"; 177 + interrupts = <GIC_SPI 634 IRQ_TYPE_LEVEL_HIGH 0>; 178 + pinctrl-0 = <&uart0_bus>; 179 + pinctrl-names = "default"; 180 + samsung,uart-fifosize = <256>; 191 181 };

+33

arch/arm64/boot/dts/mediatek/mt7981b.dtsi

··· 94 94 #pwm-cells = <2>; 95 95 }; 96 96 97 + serial@11002000 { 98 + compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart"; 99 + reg = <0 0x11002000 0 0x100>; 100 + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 101 + interrupt-names = "uart", "wakeup"; 102 + clocks = <&infracfg CLK_INFRA_UART0_SEL>, 103 + <&infracfg CLK_INFRA_UART0_CK>; 104 + clock-names = "baud", "bus"; 105 + status = "disabled"; 106 + }; 107 + 108 + serial@11003000 { 109 + compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart"; 110 + reg = <0 0x11003000 0 0x100>; 111 + interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 112 + interrupt-names = "uart", "wakeup"; 113 + clocks = <&infracfg CLK_INFRA_UART1_SEL>, 114 + <&infracfg CLK_INFRA_UART1_CK>; 115 + clock-names = "baud", "bus"; 116 + status = "disabled"; 117 + }; 118 + 119 + serial@11004000 { 120 + compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart"; 121 + reg = <0 0x11004000 0 0x100>; 122 + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 123 + interrupt-names = "uart", "wakeup"; 124 + clocks = <&infracfg CLK_INFRA_UART2_SEL>, 125 + <&infracfg CLK_INFRA_UART2_CK>; 126 + clock-names = "baud", "bus"; 127 + status = "disabled"; 128 + }; 129 + 97 130 i2c@11007000 { 98 131 compatible = "mediatek,mt7981-i2c"; 99 132 reg = <0 0x11007000 0 0x1000>,

+20 -40

drivers/net/hamradio/6pack.c

··· 37 37 #include <linux/semaphore.h> 38 38 #include <linux/refcount.h> 39 39 40 - #define SIXPACK_VERSION "Revision: 0.3.0" 41 - 42 40 /* sixpack priority commands */ 43 41 #define SIXP_SEOF 0x40 /* start and end of a 6pack frame */ 44 42 #define SIXP_TX_URUN 0x48 /* transmit overrun */ ··· 86 88 struct net_device *dev; /* easy for intr handling */ 87 89 88 90 /* These are pointers to the malloc()ed frame buffers. */ 89 - unsigned char *rbuff; /* receiver buffer */ 90 91 int rcount; /* received chars counter */ 91 92 unsigned char *xbuff; /* transmitter buffer */ 92 93 unsigned char *xhead; /* next byte to XMIT */ 93 94 int xleft; /* bytes left in XMIT queue */ 94 95 95 - unsigned char raw_buf[4]; 96 - unsigned char cooked_buf[400]; 96 + u8 raw_buf[4]; 97 + u8 cooked_buf[400]; 97 98 98 99 unsigned int rx_count; 99 100 unsigned int rx_count_cooked; 100 101 spinlock_t rxlock; 101 - 102 - int mtu; /* Our mtu (to spot changes!) */ 103 - int buffsize; /* Max buffers sizes */ 104 102 105 103 unsigned long flags; /* Flag values/ mode etc */ 106 104 unsigned char mode; /* 6pack mode */ ··· 107 113 unsigned char slottime; 108 114 unsigned char duplex; 109 115 unsigned char led_state; 110 - unsigned char status; 111 - unsigned char status1; 116 + u8 status; 117 + u8 status1; 112 118 unsigned char status2; 113 119 unsigned char tx_enable; 114 120 unsigned char tnc_state; ··· 122 128 123 129 #define AX25_6PACK_HEADER_LEN 0 124 130 125 - static void sixpack_decode(struct sixpack *, const unsigned char[], int); 131 + static void sixpack_decode(struct sixpack *, const u8 *, size_t); 126 132 static int encode_sixpack(unsigned char *, unsigned char *, int, unsigned char); 127 133 128 134 /* ··· 161 167 unsigned char *msg, *p = icp; 162 168 int actual, count; 163 169 164 - if (len > sp->mtu) { /* sp->mtu = AX25_MTU = max. PACLEN = 256 */ 170 + if (len > AX25_MTU + 73) { 165 171 msg = "oversized transmit packet!"; 166 172 goto out_drop; 167 173 } ··· 327 333 { 328 334 struct sk_buff *skb; 329 335 int count; 330 - unsigned char *ptr; 336 + u8 *ptr; 331 337 332 338 count = sp->rcount + 1; 333 339 ··· 425 431 const u8 *fp, size_t count) 426 432 { 427 433 struct sixpack *sp; 428 - int count1; 434 + size_t count1; 429 435 430 436 if (!count) 431 437 return; ··· 538 544 */ 539 545 static int sixpack_open(struct tty_struct *tty) 540 546 { 541 - char *rbuff = NULL, *xbuff = NULL; 547 + char *xbuff = NULL; 542 548 struct net_device *dev; 543 549 struct sixpack *sp; 544 550 unsigned long len; ··· 568 574 569 575 len = dev->mtu * 2; 570 576 571 - rbuff = kmalloc(len + 4, GFP_KERNEL); 572 577 xbuff = kmalloc(len + 4, GFP_KERNEL); 573 - 574 - if (rbuff == NULL || xbuff == NULL) { 578 + if (xbuff == NULL) { 575 579 err = -ENOBUFS; 576 580 goto out_free; 577 581 } ··· 578 586 579 587 sp->tty = tty; 580 588 581 - sp->rbuff = rbuff; 582 589 sp->xbuff = xbuff; 583 590 584 - sp->mtu = AX25_MTU + 73; 585 - sp->buffsize = len; 586 591 sp->rcount = 0; 587 592 sp->rx_count = 0; 588 593 sp->rx_count_cooked = 0; ··· 620 631 621 632 out_free: 622 633 kfree(xbuff); 623 - kfree(rbuff); 624 634 625 635 free_netdev(dev); 626 636 ··· 664 676 del_timer_sync(&sp->resync_t); 665 677 666 678 /* Free all 6pack frame buffers after unreg. */ 667 - kfree(sp->rbuff); 668 679 kfree(sp->xbuff); 669 680 670 681 free_netdev(sp->dev); ··· 743 756 744 757 /* Initialize 6pack control device -- register 6pack line discipline */ 745 758 746 - static const char msg_banner[] __initconst = KERN_INFO \ 747 - "AX.25: 6pack driver, " SIXPACK_VERSION "\n"; 748 - static const char msg_regfail[] __initconst = KERN_ERR \ 749 - "6pack: can't register line discipline (err = %d)\n"; 750 - 751 759 static int __init sixpack_init_driver(void) 752 760 { 753 761 int status; 754 762 755 - printk(msg_banner); 756 - 757 763 /* Register the provided line protocol discipline */ 758 764 status = tty_register_ldisc(&sp_ldisc); 759 765 if (status) 760 - printk(msg_regfail, status); 766 + pr_err("6pack: can't register line discipline (err = %d)\n", status); 761 767 762 768 return status; 763 769 } ··· 800 820 801 821 /* decode 4 sixpack-encoded bytes into 3 data bytes */ 802 822 803 - static void decode_data(struct sixpack *sp, unsigned char inbyte) 823 + static void decode_data(struct sixpack *sp, u8 inbyte) 804 824 { 805 - unsigned char *buf; 825 + u8 *buf; 806 826 807 827 if (sp->rx_count != 3) { 808 828 sp->raw_buf[sp->rx_count++] = inbyte; ··· 828 848 829 849 /* identify and execute a 6pack priority command byte */ 830 850 831 - static void decode_prio_command(struct sixpack *sp, unsigned char cmd) 851 + static void decode_prio_command(struct sixpack *sp, u8 cmd) 832 852 { 833 - int actual; 853 + ssize_t actual; 834 854 835 855 if ((cmd & SIXP_PRIO_DATA_MASK) != 0) { /* idle ? */ 836 856 ··· 878 898 879 899 /* identify and execute a standard 6pack command byte */ 880 900 881 - static void decode_std_command(struct sixpack *sp, unsigned char cmd) 901 + static void decode_std_command(struct sixpack *sp, u8 cmd) 882 902 { 883 - unsigned char checksum = 0, rest = 0; 903 + u8 checksum = 0, rest = 0; 884 904 short i; 885 905 886 906 switch (cmd & SIXP_CMD_MASK) { /* normal command */ ··· 928 948 /* decode a 6pack packet */ 929 949 930 950 static void 931 - sixpack_decode(struct sixpack *sp, const unsigned char *pre_rbuff, int count) 951 + sixpack_decode(struct sixpack *sp, const u8 *pre_rbuff, size_t count) 932 952 { 933 - unsigned char inbyte; 934 - int count1; 953 + size_t count1; 954 + u8 inbyte; 935 955 936 956 for (count1 = 0; count1 < count; count1++) { 937 957 inbyte = pre_rbuff[count1];

+12 -11

drivers/net/mctp/mctp-serial.c

··· 64 64 u16 txfcs, rxfcs, rxfcs_rcvd; 65 65 unsigned int txlen, rxlen; 66 66 unsigned int txpos, rxpos; 67 - unsigned char txbuf[BUFSIZE], 67 + u8 txbuf[BUFSIZE], 68 68 rxbuf[BUFSIZE]; 69 69 }; 70 70 71 - static bool needs_escape(unsigned char c) 71 + static bool needs_escape(u8 c) 72 72 { 73 73 return c == BYTE_ESC || c == BYTE_FRAME; 74 74 } 75 75 76 - static int next_chunk_len(struct mctp_serial *dev) 76 + static unsigned int next_chunk_len(struct mctp_serial *dev) 77 77 { 78 - int i; 78 + unsigned int i; 79 79 80 80 /* either we have no bytes to send ... */ 81 81 if (dev->txpos == dev->txlen) ··· 99 99 return i; 100 100 } 101 101 102 - static int write_chunk(struct mctp_serial *dev, unsigned char *buf, int len) 102 + static ssize_t write_chunk(struct mctp_serial *dev, u8 *buf, size_t len) 103 103 { 104 104 return dev->tty->ops->write(dev->tty, buf, len); 105 105 } ··· 108 108 { 109 109 struct mctp_serial *dev = container_of(work, struct mctp_serial, 110 110 tx_work); 111 - unsigned char c, buf[3]; 112 111 unsigned long flags; 113 - int len, txlen; 112 + ssize_t txlen; 113 + unsigned int len; 114 + u8 c, buf[3]; 114 115 115 116 spin_lock_irqsave(&dev->lock, flags); 116 117 ··· 294 293 dev->netdev->stats.rx_bytes += dev->rxlen; 295 294 } 296 295 297 - static void mctp_serial_push_header(struct mctp_serial *dev, unsigned char c) 296 + static void mctp_serial_push_header(struct mctp_serial *dev, u8 c) 298 297 { 299 298 switch (dev->rxpos) { 300 299 case 0: ··· 324 323 } 325 324 } 326 325 327 - static void mctp_serial_push_trailer(struct mctp_serial *dev, unsigned char c) 326 + static void mctp_serial_push_trailer(struct mctp_serial *dev, u8 c) 328 327 { 329 328 switch (dev->rxpos) { 330 329 case 0: ··· 348 347 } 349 348 } 350 349 351 - static void mctp_serial_push(struct mctp_serial *dev, unsigned char c) 350 + static void mctp_serial_push(struct mctp_serial *dev, u8 c) 352 351 { 353 352 switch (dev->rxstate) { 354 353 case STATE_IDLE: ··· 395 394 const u8 *f, size_t len) 396 395 { 397 396 struct mctp_serial *dev = tty->disc_data; 398 - int i; 397 + size_t i; 399 398 400 399 if (!netif_running(dev->netdev)) 401 400 return;

+1 -1

drivers/tty/hvc/hvsi_lib.c

··· 303 303 pr_devel("HVSI@%x: %s DTR...\n", pv->termno, 304 304 dtr ? "Setting" : "Clearing"); 305 305 306 - ctrl.hdr.type = VS_CONTROL_PACKET_HEADER, 306 + ctrl.hdr.type = VS_CONTROL_PACKET_HEADER; 307 307 ctrl.hdr.len = sizeof(struct hvsi_control); 308 308 ctrl.verb = cpu_to_be16(VSV_SET_MODEM_CTL); 309 309 ctrl.mask = cpu_to_be32(HVSI_TSDTR);

+1 -6

drivers/tty/mxser.c

··· 208 208 }; 209 209 #define UART_INFO_NUM ARRAY_SIZE(Gpci_uart_info) 210 210 211 - 212 - /* driver_data correspond to the lines in the structure above 213 - see also ISA probe function before you change something */ 214 211 static const struct pci_device_id mxser_pcibrds[] = { 215 212 { PCI_DEVICE_DATA(MOXA, C168, 8) }, 216 213 { PCI_DEVICE_DATA(MOXA, C104, 4) }, ··· 983 986 ss->baud_base = MXSER_BAUD_BASE; 984 987 ss->close_delay = close_delay; 985 988 ss->closing_wait = closing_wait; 986 - ss->custom_divisor = MXSER_CUSTOM_DIVISOR, 989 + ss->custom_divisor = MXSER_CUSTOM_DIVISOR; 987 990 mutex_unlock(&port->mutex); 988 991 return 0; 989 992 } ··· 1770 1773 1771 1774 mxser_process_txrx_fifo(info); 1772 1775 1773 - info->port.close_delay = 5 * HZ / 10; 1774 - info->port.closing_wait = 30 * HZ; 1775 1776 spin_lock_init(&info->slock); 1776 1777 1777 1778 /* before set INT ISR, disable all int */

+1 -1

drivers/tty/serdev/core.c

··· 529 529 bool found = false; 530 530 531 531 for_each_available_child_of_node(ctrl->dev.of_node, node) { 532 - if (!of_get_property(node, "compatible", NULL)) 532 + if (!of_property_present(node, "compatible")) 533 533 continue; 534 534 535 535 dev_dbg(&ctrl->dev, "adding child %pOF\n", node);

+1

drivers/tty/serial/8250/8250_aspeed_vuart.c

··· 561 561 { .compatible = "aspeed,ast2500-vuart" }, 562 562 { }, 563 563 }; 564 + MODULE_DEVICE_TABLE(of, aspeed_vuart_table); 564 565 565 566 static struct platform_driver aspeed_vuart_driver = { 566 567 .driver = {

+47

drivers/tty/serial/8250/8250_bcm2835aux.c

··· 13 13 */ 14 14 15 15 #include <linux/clk.h> 16 + #include <linux/console.h> 16 17 #include <linux/io.h> 17 18 #include <linux/module.h> 18 19 #include <linux/of.h> ··· 214 213 }; 215 214 MODULE_DEVICE_TABLE(acpi, bcm2835aux_serial_acpi_match); 216 215 216 + static bool bcm2835aux_can_disable_clock(struct device *dev) 217 + { 218 + struct bcm2835aux_data *data = dev_get_drvdata(dev); 219 + struct uart_8250_port *up = serial8250_get_port(data->line); 220 + 221 + if (device_may_wakeup(dev)) 222 + return false; 223 + 224 + if (uart_console(&up->port) && !console_suspend_enabled) 225 + return false; 226 + 227 + return true; 228 + } 229 + 230 + static int bcm2835aux_suspend(struct device *dev) 231 + { 232 + struct bcm2835aux_data *data = dev_get_drvdata(dev); 233 + 234 + serial8250_suspend_port(data->line); 235 + 236 + if (!bcm2835aux_can_disable_clock(dev)) 237 + return 0; 238 + 239 + clk_disable_unprepare(data->clk); 240 + return 0; 241 + } 242 + 243 + static int bcm2835aux_resume(struct device *dev) 244 + { 245 + struct bcm2835aux_data *data = dev_get_drvdata(dev); 246 + int ret; 247 + 248 + if (bcm2835aux_can_disable_clock(dev)) { 249 + ret = clk_prepare_enable(data->clk); 250 + if (ret) 251 + return ret; 252 + } 253 + 254 + serial8250_resume_port(data->line); 255 + 256 + return 0; 257 + } 258 + 259 + static DEFINE_SIMPLE_DEV_PM_OPS(bcm2835aux_dev_pm_ops, bcm2835aux_suspend, bcm2835aux_resume); 260 + 217 261 static struct platform_driver bcm2835aux_serial_driver = { 218 262 .driver = { 219 263 .name = "bcm2835-aux-uart", 220 264 .of_match_table = bcm2835aux_serial_match, 221 265 .acpi_match_table = bcm2835aux_serial_acpi_match, 266 + .pm = pm_ptr(&bcm2835aux_dev_pm_ops), 222 267 }, 223 268 .probe = bcm2835aux_serial_probe, 224 269 .remove_new = bcm2835aux_serial_remove,

+10 -9

drivers/tty/serial/8250/8250_dma.c

··· 89 89 struct tty_port *tport = &p->port.state->port; 90 90 struct dma_async_tx_descriptor *desc; 91 91 struct uart_port *up = &p->port; 92 - struct scatterlist sg; 92 + struct scatterlist *sg; 93 + struct scatterlist sgl[2]; 94 + int i; 93 95 int ret; 94 96 95 97 if (dma->tx_running) { ··· 112 110 113 111 serial8250_do_prepare_tx_dma(p); 114 112 115 - sg_init_table(&sg, 1); 116 - /* kfifo can do more than one sg, we don't (quite yet) */ 117 - ret = kfifo_dma_out_prepare_mapped(&tport->xmit_fifo, &sg, 1, 113 + sg_init_table(sgl, ARRAY_SIZE(sgl)); 114 + 115 + ret = kfifo_dma_out_prepare_mapped(&tport->xmit_fifo, sgl, ARRAY_SIZE(sgl), 118 116 UART_XMIT_SIZE, dma->tx_addr); 119 117 120 - /* we already checked empty fifo above, so there should be something */ 121 - if (WARN_ON_ONCE(ret != 1)) 122 - return 0; 118 + dma->tx_size = 0; 123 119 124 - dma->tx_size = sg_dma_len(&sg); 120 + for_each_sg(sgl, sg, ret, i) 121 + dma->tx_size += sg_dma_len(sg); 125 122 126 - desc = dmaengine_prep_slave_sg(dma->txchan, &sg, 1, 123 + desc = dmaengine_prep_slave_sg(dma->txchan, sgl, ret, 127 124 DMA_MEM_TO_DEV, 128 125 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 129 126 if (!desc) {

+1 -1

drivers/tty/serial/8250/8250_dwlib.c

··· 89 89 unsigned int quot, unsigned int quot_frac) 90 90 { 91 91 dw8250_writel_ext(p, DW_UART_DLF, quot_frac); 92 - serial8250_do_set_divisor(p, baud, quot, quot_frac); 92 + serial8250_do_set_divisor(p, baud, quot); 93 93 } 94 94 95 95 void dw8250_do_set_termios(struct uart_port *p, struct ktermios *termios,

+11

drivers/tty/serial/8250/8250_early.c

··· 171 171 OF_EARLYCON_DECLARE(uart, "nvidia,tegra20-uart", early_serial8250_setup); 172 172 OF_EARLYCON_DECLARE(uart, "snps,dw-apb-uart", early_serial8250_setup); 173 173 174 + static int __init early_serial8250_rs2_setup(struct earlycon_device *device, 175 + const char *options) 176 + { 177 + device->port.regshift = 2; 178 + 179 + return early_serial8250_setup(device, options); 180 + } 181 + OF_EARLYCON_DECLARE(uart, "intel,xscale-uart", early_serial8250_rs2_setup); 182 + OF_EARLYCON_DECLARE(uart, "mrvl,mmp-uart", early_serial8250_rs2_setup); 183 + OF_EARLYCON_DECLARE(uart, "mrvl,pxa-uart", early_serial8250_rs2_setup); 184 + 174 185 #ifdef CONFIG_SERIAL_8250_OMAP 175 186 176 187 static int __init early_omap8250_setup(struct earlycon_device *device,

+1 -1

drivers/tty/serial/8250/8250_exar.c

··· 500 500 static void xr17v35x_set_divisor(struct uart_port *p, unsigned int baud, 501 501 unsigned int quot, unsigned int quot_frac) 502 502 { 503 - serial8250_do_set_divisor(p, baud, quot, quot_frac); 503 + serial8250_do_set_divisor(p, baud, quot); 504 504 505 505 /* Preserve bits not related to baudrate; DLD[7:4]. */ 506 506 quot_frac |= serial_port_in(p, 0x2) & 0xf0;

+6 -4

drivers/tty/serial/8250/8250_omap.c

··· 137 137 atomic_t active; 138 138 bool is_suspending; 139 139 int wakeirq; 140 - int wakeups_enabled; 141 140 u32 latency; 142 141 u32 calc_latency; 143 142 struct pm_qos_request pm_qos_request; ··· 1522 1523 1523 1524 platform_set_drvdata(pdev, priv); 1524 1525 1525 - device_init_wakeup(&pdev->dev, true); 1526 + device_set_wakeup_capable(&pdev->dev, true); 1527 + if (of_property_read_bool(np, "wakeup-source")) 1528 + device_set_wakeup_enable(&pdev->dev, true); 1529 + 1526 1530 pm_runtime_enable(&pdev->dev); 1527 1531 pm_runtime_use_autosuspend(&pdev->dev); 1528 1532 ··· 1583 1581 ret = devm_request_irq(&pdev->dev, up.port.irq, omap8250_irq, 0, 1584 1582 dev_name(&pdev->dev), priv); 1585 1583 if (ret < 0) 1586 - return ret; 1584 + goto err; 1587 1585 1588 1586 priv->wakeirq = irq_of_parse_and_map(np, 1); 1589 1587 ··· 1624 1622 flush_work(&priv->qos_work); 1625 1623 pm_runtime_disable(&pdev->dev); 1626 1624 cpu_latency_qos_remove_request(&priv->pm_qos_request); 1627 - device_init_wakeup(&pdev->dev, false); 1625 + device_set_wakeup_capable(&pdev->dev, false); 1628 1626 } 1629 1627 1630 1628 static int omap8250_prepare(struct device *dev)

+1 -1

drivers/tty/serial/8250/8250_pci.c

··· 1277 1277 serial_icr_write(up, UART_TCR, tcr); 1278 1278 serial_icr_write(up, UART_CPR, cpr); 1279 1279 serial_icr_write(up, UART_CKS, cpr2); 1280 - serial8250_do_set_divisor(port, baud, quot, 0); 1280 + serial8250_do_set_divisor(port, baud, quot); 1281 1281 } 1282 1282 1283 1283 /*

+104 -18

drivers/tty/serial/8250/8250_platform.c

··· 2 2 /* 3 3 * Universal/legacy platform driver for 8250/16550-type serial ports 4 4 * 5 - * Supports: ISA-compatible 8250/16550 ports 5 + * Supports: 6 + * ISA-compatible 8250/16550 ports 7 + * ACPI 8250/16550 ports 6 8 * PNP 8250/16550 ports 7 9 * "serial8250" platform devices 8 10 */ 11 + #include <linux/acpi.h> 9 12 #include <linux/array_size.h> 13 + #include <linux/io.h> 10 14 #include <linux/module.h> 11 15 #include <linux/moduleparam.h> 12 16 #include <linux/once.h> ··· 26 22 27 23 /* 28 24 * Configuration: 29 - * share_irqs Whether we pass IRQF_SHARED to request_irq(). 25 + * share_irqs: Whether we pass IRQF_SHARED to request_irq(). 30 26 * This option is unsafe when used on edge-triggered interrupts. 31 - * skip_txen_test Force skip of txen test at init time. 27 + * skip_txen_test: Force skip of txen test at init time. 32 28 */ 33 29 unsigned int share_irqs = SERIAL8250_SHARE_IRQS; 34 30 unsigned int skip_txen_test; ··· 65 61 nr_uarts = UART_NR; 66 62 67 63 /* 68 - * Set up initial isa ports based on nr_uart module param, or else 64 + * Set up initial ISA ports based on nr_uart module param, or else 69 65 * default to CONFIG_SERIAL_8250_RUNTIME_UARTS. Note that we do not 70 - * need to increase nr_uarts when setting up the initial isa ports. 66 + * need to increase nr_uarts when setting up the initial ISA ports. 71 67 */ 72 68 for (i = 0; i < nr_uarts; i++) 73 69 serial8250_setup_port(i); ··· 105 101 } 106 102 107 103 /* 108 - * Register a set of serial devices attached to a platform device. The 109 - * list is terminated with a zero flags entry, which means we expect 110 - * all entries to have at least UPF_BOOT_AUTOCONF set. 104 + * Generic 16550A platform devices 111 105 */ 112 - static int serial8250_probe(struct platform_device *dev) 106 + static int serial8250_probe_acpi(struct platform_device *pdev) 113 107 { 114 - struct plat_serial8250_port *p = dev_get_platdata(&dev->dev); 108 + struct device *dev = &pdev->dev; 109 + struct uart_8250_port uart = { }; 110 + struct resource *regs; 111 + unsigned char iotype; 112 + int ret, line; 113 + 114 + regs = platform_get_mem_or_io(pdev, 0); 115 + if (!regs) 116 + return dev_err_probe(dev, -EINVAL, "no registers defined\n"); 117 + 118 + switch (resource_type(regs)) { 119 + case IORESOURCE_IO: 120 + uart.port.iobase = regs->start; 121 + iotype = UPIO_PORT; 122 + break; 123 + case IORESOURCE_MEM: 124 + uart.port.mapbase = regs->start; 125 + uart.port.mapsize = resource_size(regs); 126 + uart.port.flags = UPF_IOREMAP; 127 + iotype = UPIO_MEM; 128 + break; 129 + default: 130 + return -EINVAL; 131 + } 132 + 133 + /* default clock frequency */ 134 + uart.port.uartclk = 1843200; 135 + uart.port.type = PORT_16550A; 136 + uart.port.dev = &pdev->dev; 137 + uart.port.flags |= UPF_SKIP_TEST | UPF_BOOT_AUTOCONF; 138 + 139 + ret = uart_read_and_validate_port_properties(&uart.port); 140 + /* no interrupt -> fall back to polling */ 141 + if (ret == -ENXIO) 142 + ret = 0; 143 + if (ret) 144 + return ret; 145 + 146 + /* 147 + * The previous call may not set iotype correctly when reg-io-width 148 + * property is absent and it doesn't support IO port resource. 149 + */ 150 + uart.port.iotype = iotype; 151 + 152 + line = serial8250_register_8250_port(&uart); 153 + if (line < 0) 154 + return line; 155 + 156 + return 0; 157 + } 158 + 159 + static int serial8250_probe_platform(struct platform_device *dev, struct plat_serial8250_port *p) 160 + { 115 161 struct uart_8250_port uart; 116 162 int ret, i, irqflag = 0; 117 163 ··· 210 156 } 211 157 212 158 /* 159 + * Register a set of serial devices attached to a platform device. 160 + * The list is terminated with a zero flags entry, which means we expect 161 + * all entries to have at least UPF_BOOT_AUTOCONF set. 162 + */ 163 + static int serial8250_probe(struct platform_device *pdev) 164 + { 165 + struct device *dev = &pdev->dev; 166 + struct plat_serial8250_port *p; 167 + 168 + p = dev_get_platdata(dev); 169 + if (p) 170 + return serial8250_probe_platform(pdev, p); 171 + 172 + /* 173 + * Probe platform UART devices defined using standard hardware 174 + * discovery mechanism like ACPI or DT. Support only ACPI based 175 + * serial device for now. 176 + */ 177 + if (has_acpi_companion(dev)) 178 + return serial8250_probe_acpi(pdev); 179 + 180 + return 0; 181 + } 182 + 183 + /* 213 184 * Remove serial ports registered against a platform device. 214 185 */ 215 186 static void serial8250_remove(struct platform_device *dev) ··· 277 198 return 0; 278 199 } 279 200 201 + static const struct acpi_device_id acpi_platform_serial_table[] = { 202 + { "RSCV0003" }, /* RISC-V Generic 16550A UART */ 203 + { } 204 + }; 205 + MODULE_DEVICE_TABLE(acpi, acpi_platform_serial_table); 206 + 280 207 static struct platform_driver serial8250_isa_driver = { 281 208 .probe = serial8250_probe, 282 209 .remove_new = serial8250_remove, ··· 290 205 .resume = serial8250_resume, 291 206 .driver = { 292 207 .name = "serial8250", 208 + .acpi_match_table = acpi_platform_serial_table, 293 209 }, 294 210 }; 295 211 296 212 /* 297 213 * This "device" covers _all_ ISA 8250-compatible serial devices listed 298 - * in the table in include/asm/serial.h 214 + * in the table in include/asm/serial.h. 299 215 */ 300 216 struct platform_device *serial8250_isa_devs; 301 217 ··· 325 239 if (ret) 326 240 goto unreg_uart_drv; 327 241 328 - serial8250_isa_devs = platform_device_alloc("serial8250", 329 - PLAT8250_DEV_LEGACY); 242 + serial8250_isa_devs = platform_device_alloc("serial8250", PLAT8250_DEV_LEGACY); 330 243 if (!serial8250_isa_devs) { 331 244 ret = -ENOMEM; 332 245 goto unreg_pnp; ··· 364 279 /* 365 280 * This tells serial8250_unregister_port() not to re-register 366 281 * the ports (thereby making serial8250_isa_driver permanently 367 - * in use.) 282 + * in use). 368 283 */ 369 284 serial8250_isa_devs = NULL; 370 285 ··· 397 312 398 313 #ifdef CONFIG_SERIAL_8250_DEPRECATED_OPTIONS 399 314 #ifndef MODULE 400 - /* This module was renamed to 8250_core in 3.7. Keep the old "8250" name 401 - * working as well for the module options so we don't break people. We 315 + /* 316 + * This module was renamed to 8250_core in 3.7. Keep the old "8250" name 317 + * working as well for the module options so we don't break people. We 402 318 * need to keep the names identical and the convenient macros will happily 403 319 * refuse to let us do that by failing the build with redefinition errors 404 - * of global variables. So we stick them inside a dummy function to avoid 405 - * those conflicts. The options still get parsed, and the redefined 320 + * of global variables. So we stick them inside a dummy function to avoid 321 + * those conflicts. The options still get parsed, and the redefined 406 322 * MODULE_PARAM_PREFIX lets us keep the "8250." syntax alive. 407 323 * 408 324 * This is hacky. I'm sorry.

+2 -2

drivers/tty/serial/8250/8250_port.c

··· 2609 2609 } 2610 2610 2611 2611 void serial8250_do_set_divisor(struct uart_port *port, unsigned int baud, 2612 - unsigned int quot, unsigned int quot_frac) 2612 + unsigned int quot) 2613 2613 { 2614 2614 struct uart_8250_port *up = up_to_u8250p(port); 2615 2615 ··· 2641 2641 if (port->set_divisor) 2642 2642 port->set_divisor(port, baud, quot, quot_frac); 2643 2643 else 2644 - serial8250_do_set_divisor(port, baud, quot, quot_frac); 2644 + serial8250_do_set_divisor(port, baud, quot); 2645 2645 } 2646 2646 2647 2647 static unsigned int serial8250_get_baud_rate(struct uart_port *port,

-16

drivers/tty/serial/8250/8250_pxa.c

··· 165 165 166 166 module_platform_driver(serial_pxa_driver); 167 167 168 - #ifdef CONFIG_SERIAL_8250_CONSOLE 169 - static int __init early_serial_pxa_setup(struct earlycon_device *device, 170 - const char *options) 171 - { 172 - struct uart_port *port = &device->port; 173 - 174 - if (!(device->port.membase || device->port.iobase)) 175 - return -ENODEV; 176 - 177 - port->regshift = 2; 178 - return early_serial8250_setup(device, NULL); 179 - } 180 - OF_EARLYCON_DECLARE(early_pxa, "mrvl,pxa-uart", early_serial_pxa_setup); 181 - OF_EARLYCON_DECLARE(mmp, "mrvl,mmp-uart", early_serial_pxa_setup); 182 - #endif 183 - 184 168 MODULE_AUTHOR("Sergei Ianovich"); 185 169 MODULE_DESCRIPTION("driver for PXA on-board UARTS"); 186 170 MODULE_LICENSE("GPL");

+76 -57

drivers/tty/serial/qcom_geni_serial.c

··· 124 124 dma_addr_t tx_dma_addr; 125 125 dma_addr_t rx_dma_addr; 126 126 bool setup; 127 - unsigned int baud; 127 + unsigned long poll_timeout_us; 128 128 unsigned long clk_rate; 129 129 void *rx_buf; 130 130 u32 loopback; 131 131 bool brk; 132 132 133 133 unsigned int tx_remaining; 134 + unsigned int tx_queued; 134 135 int wakeup_irq; 135 136 bool rx_tx_swap; 136 137 bool cts_rts_swap; ··· 144 143 static const struct uart_ops qcom_geni_uart_pops; 145 144 static struct uart_driver qcom_geni_console_driver; 146 145 static struct uart_driver qcom_geni_uart_driver; 146 + 147 + static void __qcom_geni_serial_cancel_tx_cmd(struct uart_port *uport); 148 + static void qcom_geni_serial_cancel_tx_cmd(struct uart_port *uport); 147 149 148 150 static inline struct qcom_geni_serial_port *to_dev_port(struct uart_port *uport) 149 151 { ··· 269 265 return readl(uport->membase + SE_GENI_STATUS) & S_GENI_CMD_ACTIVE; 270 266 } 271 267 272 - static bool qcom_geni_serial_poll_bit(struct uart_port *uport, 273 - int offset, int field, bool set) 268 + static bool qcom_geni_serial_poll_bitfield(struct uart_port *uport, 269 + unsigned int offset, u32 field, u32 val) 274 270 { 275 271 u32 reg; 276 272 struct qcom_geni_serial_port *port; 277 - unsigned int baud; 278 - unsigned int fifo_bits; 279 273 unsigned long timeout_us = 20000; 280 274 struct qcom_geni_private_data *private_data = uport->private_data; 281 275 282 276 if (private_data->drv) { 283 277 port = to_dev_port(uport); 284 - baud = port->baud; 285 - if (!baud) 286 - baud = 115200; 287 - fifo_bits = port->tx_fifo_depth * port->tx_fifo_width; 288 - /* 289 - * Total polling iterations based on FIFO worth of bytes to be 290 - * sent at current baud. Add a little fluff to the wait. 291 - */ 292 - timeout_us = ((fifo_bits * USEC_PER_SEC) / baud) + 500; 278 + if (port->poll_timeout_us) 279 + timeout_us = port->poll_timeout_us; 293 280 } 294 281 295 282 /* ··· 290 295 timeout_us = DIV_ROUND_UP(timeout_us, 10) * 10; 291 296 while (timeout_us) { 292 297 reg = readl(uport->membase + offset); 293 - if ((bool)(reg & field) == set) 298 + if ((reg & field) == val) 294 299 return true; 295 300 udelay(10); 296 301 timeout_us -= 10; 297 302 } 298 303 return false; 304 + } 305 + 306 + static bool qcom_geni_serial_poll_bit(struct uart_port *uport, 307 + unsigned int offset, u32 field, bool set) 308 + { 309 + return qcom_geni_serial_poll_bitfield(uport, offset, field, set ? field : 0); 299 310 } 300 311 301 312 static void qcom_geni_serial_setup_tx(struct uart_port *uport, u32 xmit_size) ··· 316 315 static void qcom_geni_serial_poll_tx_done(struct uart_port *uport) 317 316 { 318 317 int done; 319 - u32 irq_clear = M_CMD_DONE_EN; 320 318 321 319 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 322 320 M_CMD_DONE_EN, true); 323 321 if (!done) { 324 322 writel(M_GENI_CMD_ABORT, uport->membase + 325 323 SE_GENI_M_CMD_CTRL_REG); 326 - irq_clear |= M_CMD_ABORT_EN; 327 324 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 328 325 M_CMD_ABORT_EN, true); 326 + writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 329 327 } 330 - writel(irq_clear, uport->membase + SE_GENI_M_IRQ_CLEAR); 331 328 } 332 329 333 330 static void qcom_geni_serial_abort_rx(struct uart_port *uport) ··· 385 386 static void qcom_geni_serial_poll_put_char(struct uart_port *uport, 386 387 unsigned char c) 387 388 { 388 - writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); 389 + if (qcom_geni_serial_main_active(uport)) { 390 + qcom_geni_serial_poll_tx_done(uport); 391 + __qcom_geni_serial_cancel_tx_cmd(uport); 392 + } 393 + 394 + writel(M_CMD_DONE_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 389 395 qcom_geni_serial_setup_tx(uport, 1); 390 - WARN_ON(!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 391 - M_TX_FIFO_WATERMARK_EN, true)); 392 396 writel(c, uport->membase + SE_GENI_TX_FIFOn); 393 - writel(M_TX_FIFO_WATERMARK_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 394 397 qcom_geni_serial_poll_tx_done(uport); 395 398 } 396 399 #endif 397 400 398 401 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE 402 + static void qcom_geni_serial_drain_fifo(struct uart_port *uport) 403 + { 404 + struct qcom_geni_serial_port *port = to_dev_port(uport); 405 + 406 + qcom_geni_serial_poll_bitfield(uport, SE_GENI_M_GP_LENGTH, GP_LENGTH, 407 + port->tx_queued); 408 + } 409 + 399 410 static void qcom_geni_serial_wr_char(struct uart_port *uport, unsigned char ch) 400 411 { 401 412 struct qcom_geni_private_data *private_data = uport->private_data; ··· 440 431 } 441 432 442 433 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); 434 + writel(M_CMD_DONE_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 443 435 qcom_geni_serial_setup_tx(uport, bytes_to_send); 444 436 for (i = 0; i < count; ) { 445 437 size_t chars_to_write = 0; ··· 479 469 { 480 470 struct uart_port *uport; 481 471 struct qcom_geni_serial_port *port; 472 + u32 m_irq_en, s_irq_en; 482 473 bool locked = true; 483 474 unsigned long flags; 484 - u32 geni_status; 485 - u32 irq_en; 486 475 487 476 WARN_ON(co->index < 0 || co->index >= GENI_UART_CONS_PORTS); 488 477 ··· 495 486 else 496 487 uart_port_lock_irqsave(uport, &flags); 497 488 498 - geni_status = readl(uport->membase + SE_GENI_STATUS); 489 + m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 490 + s_irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN); 491 + writel(0, uport->membase + SE_GENI_M_IRQ_EN); 492 + writel(0, uport->membase + SE_GENI_S_IRQ_EN); 499 493 500 - if (!locked) { 501 - /* 502 - * We can only get here if an oops is in progress then we were 503 - * unable to get the lock. This means we can't safely access 504 - * our state variables like tx_remaining. About the best we 505 - * can do is wait for the FIFO to be empty before we start our 506 - * transfer, so we'll do that. 507 - */ 508 - qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 509 - M_TX_FIFO_NOT_EMPTY_EN, false); 510 - } else if ((geni_status & M_GENI_CMD_ACTIVE) && !port->tx_remaining) { 511 - /* 512 - * It seems we can't interrupt existing transfers if all data 513 - * has been sent, in which case we need to look for done first. 514 - */ 515 - qcom_geni_serial_poll_tx_done(uport); 494 + if (qcom_geni_serial_main_active(uport)) { 495 + /* Wait for completion or drain FIFO */ 496 + if (!locked || port->tx_remaining == 0) 497 + qcom_geni_serial_poll_tx_done(uport); 498 + else 499 + qcom_geni_serial_drain_fifo(uport); 516 500 517 - if (!kfifo_is_empty(&uport->state->port.xmit_fifo)) { 518 - irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 519 - writel(irq_en | M_TX_FIFO_WATERMARK_EN, 520 - uport->membase + SE_GENI_M_IRQ_EN); 521 - } 501 + qcom_geni_serial_cancel_tx_cmd(uport); 522 502 } 523 503 524 504 __qcom_geni_serial_console_write(uport, s, count); 525 505 506 + writel(m_irq_en, uport->membase + SE_GENI_M_IRQ_EN); 507 + writel(s_irq_en, uport->membase + SE_GENI_S_IRQ_EN); 526 508 527 - if (locked) { 528 - if (port->tx_remaining) 529 - qcom_geni_serial_setup_tx(uport, port->tx_remaining); 509 + if (locked) 530 510 uart_port_unlock_irqrestore(uport, flags); 531 - } 532 511 } 533 512 534 513 static void handle_rx_console(struct uart_port *uport, u32 bytes, bool drop) ··· 679 682 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 680 683 } 681 684 682 - static void qcom_geni_serial_cancel_tx_cmd(struct uart_port *uport) 685 + static void __qcom_geni_serial_cancel_tx_cmd(struct uart_port *uport) 683 686 { 684 687 struct qcom_geni_serial_port *port = to_dev_port(uport); 685 - 686 - if (!qcom_geni_serial_main_active(uport)) 687 - return; 688 688 689 689 geni_se_cancel_m_cmd(&port->se); 690 690 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, ··· 692 698 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 693 699 } 694 700 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 701 + } 702 + 703 + static void qcom_geni_serial_cancel_tx_cmd(struct uart_port *uport) 704 + { 705 + struct qcom_geni_serial_port *port = to_dev_port(uport); 706 + 707 + if (!qcom_geni_serial_main_active(uport)) 708 + return; 709 + 710 + __qcom_geni_serial_cancel_tx_cmd(uport); 695 711 696 712 port->tx_remaining = 0; 713 + port->tx_queued = 0; 697 714 } 698 715 699 716 static void qcom_geni_serial_handle_rx_fifo(struct uart_port *uport, bool drop) ··· 928 923 if (!chunk) 929 924 goto out_write_wakeup; 930 925 931 - if (!port->tx_remaining) { 926 + if (!active) { 932 927 qcom_geni_serial_setup_tx(uport, pending); 933 928 port->tx_remaining = pending; 929 + port->tx_queued = 0; 934 930 935 931 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 936 932 if (!(irq_en & M_TX_FIFO_WATERMARK_EN)) ··· 940 934 } 941 935 942 936 qcom_geni_serial_send_chunk_fifo(uport, chunk); 937 + port->tx_queued += chunk; 943 938 944 939 /* 945 940 * The tx fifo watermark is level triggered and latched. Though we had ··· 1251 1244 unsigned long clk_rate; 1252 1245 u32 ver, sampling_rate; 1253 1246 unsigned int avg_bw_core; 1247 + unsigned long timeout; 1254 1248 1255 1249 qcom_geni_serial_stop_rx(uport); 1256 1250 /* baud rate */ 1257 1251 baud = uart_get_baud_rate(uport, termios, old, 300, 4000000); 1258 - port->baud = baud; 1259 1252 1260 1253 sampling_rate = UART_OVERSAMPLING; 1261 1254 /* Sampling rate is halved for IP versions >= 2.5 */ ··· 1333 1326 else 1334 1327 tx_trans_cfg |= UART_CTS_MASK; 1335 1328 1336 - if (baud) 1329 + if (baud) { 1337 1330 uart_update_timeout(uport, termios->c_cflag, baud); 1331 + 1332 + /* 1333 + * Make sure that qcom_geni_serial_poll_bitfield() waits for 1334 + * the FIFO, two-word intermediate transfer register and shift 1335 + * register to clear. 1336 + * 1337 + * Note that uart_fifo_timeout() also adds a 20 ms margin. 1338 + */ 1339 + timeout = jiffies_to_usecs(uart_fifo_timeout(uport)); 1340 + timeout += 3 * timeout / port->tx_fifo_depth; 1341 + WRITE_ONCE(port->poll_timeout_us, timeout); 1342 + } 1338 1343 1339 1344 if (!uart_console(uport)) 1340 1345 writel(port->loopback,

+1 -1

drivers/tty/serial/rp2.c

··· 577 577 u32 clk_cfg; 578 578 579 579 writew(1, base + RP2_GLOBAL_CMD); 580 - readw(base + RP2_GLOBAL_CMD); 581 580 msleep(100); 581 + readw(base + RP2_GLOBAL_CMD); 582 582 writel(0, base + RP2_CLK_PRESCALER); 583 583 584 584 /* TDM clock configuration */

+28 -23

drivers/tty/serial/samsung_tty.c

··· 550 550 case TYPE_APPLE_S5L: 551 551 s3c24xx_clear_bit(port, APPLE_S5L_UCON_RXTHRESH_ENA, S3C2410_UCON); 552 552 s3c24xx_clear_bit(port, APPLE_S5L_UCON_RXTO_ENA, S3C2410_UCON); 553 + s3c24xx_clear_bit(port, APPLE_S5L_UCON_RXTO_LEGACY_ENA, S3C2410_UCON); 553 554 break; 554 555 default: 555 556 disable_irq_nosync(ourport->rx_irq); ··· 708 707 709 708 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport); 710 709 711 - static irqreturn_t s3c24xx_serial_rx_chars_dma(void *dev_id) 710 + static irqreturn_t s3c24xx_serial_rx_chars_dma(struct s3c24xx_uart_port *ourport) 712 711 { 713 - struct s3c24xx_uart_port *ourport = dev_id; 714 712 struct uart_port *port = &ourport->port; 715 713 struct s3c24xx_uart_dma *dma = ourport->dma; 716 714 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port); ··· 843 843 tty_flip_buffer_push(&port->state->port); 844 844 } 845 845 846 - static irqreturn_t s3c24xx_serial_rx_chars_pio(void *dev_id) 846 + static irqreturn_t s3c24xx_serial_rx_chars_pio(struct s3c24xx_uart_port *ourport) 847 847 { 848 - struct s3c24xx_uart_port *ourport = dev_id; 849 848 struct uart_port *port = &ourport->port; 850 849 851 850 uart_port_lock(port); ··· 854 855 return IRQ_HANDLED; 855 856 } 856 857 857 - static irqreturn_t s3c24xx_serial_rx_irq(int irq, void *dev_id) 858 + static irqreturn_t s3c24xx_serial_rx_irq(struct s3c24xx_uart_port *ourport) 858 859 { 859 - struct s3c24xx_uart_port *ourport = dev_id; 860 - 861 860 if (ourport->dma && ourport->dma->rx_chan) 862 - return s3c24xx_serial_rx_chars_dma(dev_id); 863 - return s3c24xx_serial_rx_chars_pio(dev_id); 861 + return s3c24xx_serial_rx_chars_dma(ourport); 862 + return s3c24xx_serial_rx_chars_pio(ourport); 864 863 } 865 864 866 865 static void s3c24xx_serial_tx_chars(struct s3c24xx_uart_port *ourport) ··· 925 928 s3c24xx_serial_stop_tx(port); 926 929 } 927 930 928 - static irqreturn_t s3c24xx_serial_tx_irq(int irq, void *id) 931 + static irqreturn_t s3c24xx_serial_tx_irq(struct s3c24xx_uart_port *ourport) 929 932 { 930 - struct s3c24xx_uart_port *ourport = id; 931 933 struct uart_port *port = &ourport->port; 932 934 933 935 uart_port_lock(port); ··· 940 944 /* interrupt handler for s3c64xx and later SoC's.*/ 941 945 static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id) 942 946 { 943 - const struct s3c24xx_uart_port *ourport = id; 947 + struct s3c24xx_uart_port *ourport = id; 944 948 const struct uart_port *port = &ourport->port; 945 949 u32 pend = rd_regl(port, S3C64XX_UINTP); 946 950 irqreturn_t ret = IRQ_HANDLED; 947 951 948 952 if (pend & S3C64XX_UINTM_RXD_MSK) { 949 - ret = s3c24xx_serial_rx_irq(irq, id); 953 + ret = s3c24xx_serial_rx_irq(ourport); 950 954 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK); 951 955 } 952 956 if (pend & S3C64XX_UINTM_TXD_MSK) { 953 - ret = s3c24xx_serial_tx_irq(irq, id); 957 + ret = s3c24xx_serial_tx_irq(ourport); 954 958 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK); 955 959 } 956 960 return ret; ··· 959 963 /* interrupt handler for Apple SoC's.*/ 960 964 static irqreturn_t apple_serial_handle_irq(int irq, void *id) 961 965 { 962 - const struct s3c24xx_uart_port *ourport = id; 966 + struct s3c24xx_uart_port *ourport = id; 963 967 const struct uart_port *port = &ourport->port; 964 968 u32 pend = rd_regl(port, S3C2410_UTRSTAT); 965 969 irqreturn_t ret = IRQ_NONE; 966 970 967 - if (pend & (APPLE_S5L_UTRSTAT_RXTHRESH | APPLE_S5L_UTRSTAT_RXTO)) { 971 + if (pend & (APPLE_S5L_UTRSTAT_RXTHRESH | APPLE_S5L_UTRSTAT_RXTO | 972 + APPLE_S5L_UTRSTAT_RXTO_LEGACY)) { 968 973 wr_regl(port, S3C2410_UTRSTAT, 969 - APPLE_S5L_UTRSTAT_RXTHRESH | APPLE_S5L_UTRSTAT_RXTO); 970 - ret = s3c24xx_serial_rx_irq(irq, id); 974 + APPLE_S5L_UTRSTAT_RXTHRESH | APPLE_S5L_UTRSTAT_RXTO | 975 + APPLE_S5L_UTRSTAT_RXTO_LEGACY); 976 + ret = s3c24xx_serial_rx_irq(ourport); 971 977 } 972 978 if (pend & APPLE_S5L_UTRSTAT_TXTHRESH) { 973 979 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_TXTHRESH); 974 - ret = s3c24xx_serial_tx_irq(irq, id); 980 + ret = s3c24xx_serial_tx_irq(ourport); 975 981 } 976 982 977 983 return ret; ··· 1193 1195 ucon = rd_regl(port, S3C2410_UCON); 1194 1196 ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK | 1195 1197 APPLE_S5L_UCON_RXTHRESH_ENA_MSK | 1196 - APPLE_S5L_UCON_RXTO_ENA_MSK); 1198 + APPLE_S5L_UCON_RXTO_ENA_MSK | 1199 + APPLE_S5L_UCON_RXTO_LEGACY_ENA_MSK); 1197 1200 wr_regl(port, S3C2410_UCON, ucon); 1198 1201 1199 1202 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS); ··· 1291 1292 /* Enable Rx Interrupt */ 1292 1293 s3c24xx_set_bit(port, APPLE_S5L_UCON_RXTHRESH_ENA, S3C2410_UCON); 1293 1294 s3c24xx_set_bit(port, APPLE_S5L_UCON_RXTO_ENA, S3C2410_UCON); 1295 + s3c24xx_set_bit(port, APPLE_S5L_UCON_RXTO_LEGACY_ENA, S3C2410_UCON); 1294 1296 1295 1297 return ret; 1296 1298 } ··· 2148 2148 2149 2149 ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK | 2150 2150 APPLE_S5L_UCON_RXTHRESH_ENA_MSK | 2151 - APPLE_S5L_UCON_RXTO_ENA_MSK); 2151 + APPLE_S5L_UCON_RXTO_ENA_MSK | 2152 + APPLE_S5L_UCON_RXTO_LEGACY_ENA_MSK); 2152 2153 2153 2154 if (ourport->tx_enabled) 2154 2155 ucon |= APPLE_S5L_UCON_TXTHRESH_ENA_MSK; 2155 2156 if (ourport->rx_enabled) 2156 2157 ucon |= APPLE_S5L_UCON_RXTHRESH_ENA_MSK | 2157 - APPLE_S5L_UCON_RXTO_ENA_MSK; 2158 + APPLE_S5L_UCON_RXTO_ENA_MSK | 2159 + APPLE_S5L_UCON_RXTO_LEGACY_ENA_MSK; 2158 2160 2159 2161 wr_regl(port, S3C2410_UCON, ucon); 2160 2162 ··· 2543 2541 .name = "Apple S5L UART", 2544 2542 .type = TYPE_APPLE_S5L, 2545 2543 .port_type = PORT_8250, 2546 - .iotype = UPIO_MEM, 2544 + .iotype = UPIO_MEM32, 2547 2545 .fifosize = 16, 2548 2546 .rx_fifomask = S3C2410_UFSTAT_RXMASK, 2549 2547 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT, ··· 2829 2827 static int __init apple_s5l_early_console_setup(struct earlycon_device *device, 2830 2828 const char *opt) 2831 2829 { 2830 + /* Apple A7-A11 requires MMIO32 register accesses. */ 2831 + device->port.iotype = UPIO_MEM32; 2832 + 2832 2833 /* Close enough to S3C2410 for earlycon... */ 2833 2834 device->port.private_data = &s3c2410_early_console_data; 2834 2835

+94 -89

drivers/tty/serial/sc16is7xx.c

··· 10 10 #undef DEFAULT_SYMBOL_NAMESPACE 11 11 #define DEFAULT_SYMBOL_NAMESPACE SERIAL_NXP_SC16IS7XX 12 12 13 + #include <linux/bits.h> 13 14 #include <linux/clk.h> 14 15 #include <linux/delay.h> 15 16 #include <linux/device.h> ··· 79 78 #define SC16IS7XX_XOFF2_REG (0x07) /* Xoff2 word */ 80 79 81 80 /* IER register bits */ 82 - #define SC16IS7XX_IER_RDI_BIT (1 << 0) /* Enable RX data interrupt */ 83 - #define SC16IS7XX_IER_THRI_BIT (1 << 1) /* Enable TX holding register 81 + #define SC16IS7XX_IER_RDI_BIT BIT(0) /* Enable RX data interrupt */ 82 + #define SC16IS7XX_IER_THRI_BIT BIT(1) /* Enable TX holding register 84 83 * interrupt */ 85 - #define SC16IS7XX_IER_RLSI_BIT (1 << 2) /* Enable RX line status 84 + #define SC16IS7XX_IER_RLSI_BIT BIT(2) /* Enable RX line status 86 85 * interrupt */ 87 - #define SC16IS7XX_IER_MSI_BIT (1 << 3) /* Enable Modem status 86 + #define SC16IS7XX_IER_MSI_BIT BIT(3) /* Enable Modem status 88 87 * interrupt */ 89 88 90 89 /* IER register bits - write only if (EFR[4] == 1) */ 91 - #define SC16IS7XX_IER_SLEEP_BIT (1 << 4) /* Enable Sleep mode */ 92 - #define SC16IS7XX_IER_XOFFI_BIT (1 << 5) /* Enable Xoff interrupt */ 93 - #define SC16IS7XX_IER_RTSI_BIT (1 << 6) /* Enable nRTS interrupt */ 94 - #define SC16IS7XX_IER_CTSI_BIT (1 << 7) /* Enable nCTS interrupt */ 90 + #define SC16IS7XX_IER_SLEEP_BIT BIT(4) /* Enable Sleep mode */ 91 + #define SC16IS7XX_IER_XOFFI_BIT BIT(5) /* Enable Xoff interrupt */ 92 + #define SC16IS7XX_IER_RTSI_BIT BIT(6) /* Enable nRTS interrupt */ 93 + #define SC16IS7XX_IER_CTSI_BIT BIT(7) /* Enable nCTS interrupt */ 95 94 96 95 /* FCR register bits */ 97 - #define SC16IS7XX_FCR_FIFO_BIT (1 << 0) /* Enable FIFO */ 98 - #define SC16IS7XX_FCR_RXRESET_BIT (1 << 1) /* Reset RX FIFO */ 99 - #define SC16IS7XX_FCR_TXRESET_BIT (1 << 2) /* Reset TX FIFO */ 100 - #define SC16IS7XX_FCR_RXLVLL_BIT (1 << 6) /* RX Trigger level LSB */ 101 - #define SC16IS7XX_FCR_RXLVLH_BIT (1 << 7) /* RX Trigger level MSB */ 96 + #define SC16IS7XX_FCR_FIFO_BIT BIT(0) /* Enable FIFO */ 97 + #define SC16IS7XX_FCR_RXRESET_BIT BIT(1) /* Reset RX FIFO */ 98 + #define SC16IS7XX_FCR_TXRESET_BIT BIT(2) /* Reset TX FIFO */ 99 + #define SC16IS7XX_FCR_RXLVLL_BIT BIT(6) /* RX Trigger level LSB */ 100 + #define SC16IS7XX_FCR_RXLVLH_BIT BIT(7) /* RX Trigger level MSB */ 102 101 103 102 /* FCR register bits - write only if (EFR[4] == 1) */ 104 - #define SC16IS7XX_FCR_TXLVLL_BIT (1 << 4) /* TX Trigger level LSB */ 105 - #define SC16IS7XX_FCR_TXLVLH_BIT (1 << 5) /* TX Trigger level MSB */ 103 + #define SC16IS7XX_FCR_TXLVLL_BIT BIT(4) /* TX Trigger level LSB */ 104 + #define SC16IS7XX_FCR_TXLVLH_BIT BIT(5) /* TX Trigger level MSB */ 106 105 107 106 /* IIR register bits */ 108 - #define SC16IS7XX_IIR_NO_INT_BIT (1 << 0) /* No interrupts pending */ 109 - #define SC16IS7XX_IIR_ID_MASK 0x3e /* Mask for the interrupt ID */ 110 - #define SC16IS7XX_IIR_THRI_SRC 0x02 /* TX holding register empty */ 111 - #define SC16IS7XX_IIR_RDI_SRC 0x04 /* RX data interrupt */ 112 - #define SC16IS7XX_IIR_RLSE_SRC 0x06 /* RX line status error */ 113 - #define SC16IS7XX_IIR_RTOI_SRC 0x0c /* RX time-out interrupt */ 114 - #define SC16IS7XX_IIR_MSI_SRC 0x00 /* Modem status interrupt 115 - * - only on 75x/76x 116 - */ 117 - #define SC16IS7XX_IIR_INPIN_SRC 0x30 /* Input pin change of state 118 - * - only on 75x/76x 119 - */ 120 - #define SC16IS7XX_IIR_XOFFI_SRC 0x10 /* Received Xoff */ 121 - #define SC16IS7XX_IIR_CTSRTS_SRC 0x20 /* nCTS,nRTS change of state 122 - * from active (LOW) 123 - * to inactive (HIGH) 124 - */ 107 + #define SC16IS7XX_IIR_NO_INT_BIT 0x01 /* No interrupts pending */ 108 + #define SC16IS7XX_IIR_ID_MASK GENMASK(5, 1) /* Mask for the interrupt ID */ 109 + #define SC16IS7XX_IIR_THRI_SRC 0x02 /* TX holding register empty */ 110 + #define SC16IS7XX_IIR_RDI_SRC 0x04 /* RX data interrupt */ 111 + #define SC16IS7XX_IIR_RLSE_SRC 0x06 /* RX line status error */ 112 + #define SC16IS7XX_IIR_RTOI_SRC 0x0c /* RX time-out interrupt */ 113 + #define SC16IS7XX_IIR_MSI_SRC 0x00 /* Modem status interrupt 114 + * - only on 75x/76x 115 + */ 116 + #define SC16IS7XX_IIR_INPIN_SRC 0x30 /* Input pin change of state 117 + * - only on 75x/76x 118 + */ 119 + #define SC16IS7XX_IIR_XOFFI_SRC 0x10 /* Received Xoff */ 120 + #define SC16IS7XX_IIR_CTSRTS_SRC 0x20 /* nCTS,nRTS change of state 121 + * from active (LOW) 122 + * to inactive (HIGH) 123 + */ 125 124 /* LCR register bits */ 126 - #define SC16IS7XX_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */ 127 - #define SC16IS7XX_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1 125 + #define SC16IS7XX_LCR_LENGTH0_BIT BIT(0) /* Word length bit 0 */ 126 + #define SC16IS7XX_LCR_LENGTH1_BIT BIT(1) /* Word length bit 1 128 127 * 129 128 * Word length bits table: 130 129 * 00 -> 5 bit words ··· 132 131 * 10 -> 7 bit words 133 132 * 11 -> 8 bit words 134 133 */ 135 - #define SC16IS7XX_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit 134 + #define SC16IS7XX_LCR_STOPLEN_BIT BIT(2) /* STOP length bit 136 135 * 137 136 * STOP length bit table: 138 137 * 0 -> 1 stop bit ··· 140 139 * word length is 5, 141 140 * 2 stop bits otherwise 142 141 */ 143 - #define SC16IS7XX_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */ 144 - #define SC16IS7XX_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */ 145 - #define SC16IS7XX_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */ 146 - #define SC16IS7XX_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */ 147 - #define SC16IS7XX_LCR_DLAB_BIT (1 << 7) /* Divisor Latch enable */ 142 + #define SC16IS7XX_LCR_PARITY_BIT BIT(3) /* Parity bit enable */ 143 + #define SC16IS7XX_LCR_EVENPARITY_BIT BIT(4) /* Even parity bit enable */ 144 + #define SC16IS7XX_LCR_FORCEPARITY_BIT BIT(5) /* 9-bit multidrop parity */ 145 + #define SC16IS7XX_LCR_TXBREAK_BIT BIT(6) /* TX break enable */ 146 + #define SC16IS7XX_LCR_DLAB_BIT BIT(7) /* Divisor Latch enable */ 148 147 #define SC16IS7XX_LCR_WORD_LEN_5 (0x00) 149 148 #define SC16IS7XX_LCR_WORD_LEN_6 (0x01) 150 149 #define SC16IS7XX_LCR_WORD_LEN_7 (0x02) ··· 155 154 * reg set */ 156 155 157 156 /* MCR register bits */ 158 - #define SC16IS7XX_MCR_DTR_BIT (1 << 0) /* DTR complement 157 + #define SC16IS7XX_MCR_DTR_BIT BIT(0) /* DTR complement 159 158 * - only on 75x/76x 160 159 */ 161 - #define SC16IS7XX_MCR_RTS_BIT (1 << 1) /* RTS complement */ 162 - #define SC16IS7XX_MCR_TCRTLR_BIT (1 << 2) /* TCR/TLR register enable */ 163 - #define SC16IS7XX_MCR_LOOP_BIT (1 << 4) /* Enable loopback test mode */ 164 - #define SC16IS7XX_MCR_XONANY_BIT (1 << 5) /* Enable Xon Any 160 + #define SC16IS7XX_MCR_RTS_BIT BIT(1) /* RTS complement */ 161 + #define SC16IS7XX_MCR_TCRTLR_BIT BIT(2) /* TCR/TLR register enable */ 162 + #define SC16IS7XX_MCR_LOOP_BIT BIT(4) /* Enable loopback test mode */ 163 + #define SC16IS7XX_MCR_XONANY_BIT BIT(5) /* Enable Xon Any 165 164 * - write enabled 166 165 * if (EFR[4] == 1) 167 166 */ 168 - #define SC16IS7XX_MCR_IRDA_BIT (1 << 6) /* Enable IrDA mode 167 + #define SC16IS7XX_MCR_IRDA_BIT BIT(6) /* Enable IrDA mode 169 168 * - write enabled 170 169 * if (EFR[4] == 1) 171 170 */ 172 - #define SC16IS7XX_MCR_CLKSEL_BIT (1 << 7) /* Divide clock by 4 171 + #define SC16IS7XX_MCR_CLKSEL_BIT BIT(7) /* Divide clock by 4 173 172 * - write enabled 174 173 * if (EFR[4] == 1) 175 174 */ 176 175 177 176 /* LSR register bits */ 178 - #define SC16IS7XX_LSR_DR_BIT (1 << 0) /* Receiver data ready */ 179 - #define SC16IS7XX_LSR_OE_BIT (1 << 1) /* Overrun Error */ 180 - #define SC16IS7XX_LSR_PE_BIT (1 << 2) /* Parity Error */ 181 - #define SC16IS7XX_LSR_FE_BIT (1 << 3) /* Frame Error */ 182 - #define SC16IS7XX_LSR_BI_BIT (1 << 4) /* Break Interrupt */ 183 - #define SC16IS7XX_LSR_BRK_ERROR_MASK 0x1E /* BI, FE, PE, OE bits */ 184 - #define SC16IS7XX_LSR_THRE_BIT (1 << 5) /* TX holding register empty */ 185 - #define SC16IS7XX_LSR_TEMT_BIT (1 << 6) /* Transmitter empty */ 186 - #define SC16IS7XX_LSR_FIFOE_BIT (1 << 7) /* Fifo Error */ 177 + #define SC16IS7XX_LSR_DR_BIT BIT(0) /* Receiver data ready */ 178 + #define SC16IS7XX_LSR_OE_BIT BIT(1) /* Overrun Error */ 179 + #define SC16IS7XX_LSR_PE_BIT BIT(2) /* Parity Error */ 180 + #define SC16IS7XX_LSR_FE_BIT BIT(3) /* Frame Error */ 181 + #define SC16IS7XX_LSR_BI_BIT BIT(4) /* Break Interrupt */ 182 + #define SC16IS7XX_LSR_BRK_ERROR_MASK \ 183 + (SC16IS7XX_LSR_OE_BIT | \ 184 + SC16IS7XX_LSR_PE_BIT | \ 185 + SC16IS7XX_LSR_FE_BIT | \ 186 + SC16IS7XX_LSR_BI_BIT) 187 + 188 + #define SC16IS7XX_LSR_THRE_BIT BIT(5) /* TX holding register empty */ 189 + #define SC16IS7XX_LSR_TEMT_BIT BIT(6) /* Transmitter empty */ 190 + #define SC16IS7XX_LSR_FIFOE_BIT BIT(7) /* Fifo Error */ 187 191 188 192 /* MSR register bits */ 189 - #define SC16IS7XX_MSR_DCTS_BIT (1 << 0) /* Delta CTS Clear To Send */ 190 - #define SC16IS7XX_MSR_DDSR_BIT (1 << 1) /* Delta DSR Data Set Ready 193 + #define SC16IS7XX_MSR_DCTS_BIT BIT(0) /* Delta CTS Clear To Send */ 194 + #define SC16IS7XX_MSR_DDSR_BIT BIT(1) /* Delta DSR Data Set Ready 191 195 * or (IO4) 192 196 * - only on 75x/76x 193 197 */ 194 - #define SC16IS7XX_MSR_DRI_BIT (1 << 2) /* Delta RI Ring Indicator 198 + #define SC16IS7XX_MSR_DRI_BIT BIT(2) /* Delta RI Ring Indicator 195 199 * or (IO7) 196 200 * - only on 75x/76x 197 201 */ 198 - #define SC16IS7XX_MSR_DCD_BIT (1 << 3) /* Delta CD Carrier Detect 202 + #define SC16IS7XX_MSR_DCD_BIT BIT(3) /* Delta CD Carrier Detect 199 203 * or (IO6) 200 204 * - only on 75x/76x 201 205 */ 202 - #define SC16IS7XX_MSR_CTS_BIT (1 << 4) /* CTS */ 203 - #define SC16IS7XX_MSR_DSR_BIT (1 << 5) /* DSR (IO4) 206 + #define SC16IS7XX_MSR_CTS_BIT BIT(4) /* CTS */ 207 + #define SC16IS7XX_MSR_DSR_BIT BIT(5) /* DSR (IO4) 204 208 * - only on 75x/76x 205 209 */ 206 - #define SC16IS7XX_MSR_RI_BIT (1 << 6) /* RI (IO7) 210 + #define SC16IS7XX_MSR_RI_BIT BIT(6) /* RI (IO7) 207 211 * - only on 75x/76x 208 212 */ 209 - #define SC16IS7XX_MSR_CD_BIT (1 << 7) /* CD (IO6) 213 + #define SC16IS7XX_MSR_CD_BIT BIT(7) /* CD (IO6) 210 214 * - only on 75x/76x 211 215 */ 212 - #define SC16IS7XX_MSR_DELTA_MASK 0x0F /* Any of the delta bits! */ 213 216 214 217 /* 215 218 * TCR register bits ··· 246 241 #define SC16IS7XX_TLR_RX_TRIGGER(words) ((((words) / 4) & 0x0f) << 4) 247 242 248 243 /* IOControl register bits (Only 75x/76x) */ 249 - #define SC16IS7XX_IOCONTROL_LATCH_BIT (1 << 0) /* Enable input latching */ 250 - #define SC16IS7XX_IOCONTROL_MODEM_A_BIT (1 << 1) /* Enable GPIO[7:4] as modem A pins */ 251 - #define SC16IS7XX_IOCONTROL_MODEM_B_BIT (1 << 2) /* Enable GPIO[3:0] as modem B pins */ 252 - #define SC16IS7XX_IOCONTROL_SRESET_BIT (1 << 3) /* Software Reset */ 244 + #define SC16IS7XX_IOCONTROL_LATCH_BIT BIT(0) /* Enable input latching */ 245 + #define SC16IS7XX_IOCONTROL_MODEM_A_BIT BIT(1) /* Enable GPIO[7:4] as modem A pins */ 246 + #define SC16IS7XX_IOCONTROL_MODEM_B_BIT BIT(2) /* Enable GPIO[3:0] as modem B pins */ 247 + #define SC16IS7XX_IOCONTROL_SRESET_BIT BIT(3) /* Software Reset */ 253 248 254 249 /* EFCR register bits */ 255 - #define SC16IS7XX_EFCR_9BIT_MODE_BIT (1 << 0) /* Enable 9-bit or Multidrop 250 + #define SC16IS7XX_EFCR_9BIT_MODE_BIT BIT(0) /* Enable 9-bit or Multidrop 256 251 * mode (RS485) */ 257 - #define SC16IS7XX_EFCR_RXDISABLE_BIT (1 << 1) /* Disable receiver */ 258 - #define SC16IS7XX_EFCR_TXDISABLE_BIT (1 << 2) /* Disable transmitter */ 259 - #define SC16IS7XX_EFCR_AUTO_RS485_BIT (1 << 4) /* Auto RS485 RTS direction */ 260 - #define SC16IS7XX_EFCR_RTS_INVERT_BIT (1 << 5) /* RTS output inversion */ 261 - #define SC16IS7XX_EFCR_IRDA_MODE_BIT (1 << 7) /* IrDA mode 252 + #define SC16IS7XX_EFCR_RXDISABLE_BIT BIT(1) /* Disable receiver */ 253 + #define SC16IS7XX_EFCR_TXDISABLE_BIT BIT(2) /* Disable transmitter */ 254 + #define SC16IS7XX_EFCR_AUTO_RS485_BIT BIT(4) /* Auto RS485 RTS direction */ 255 + #define SC16IS7XX_EFCR_RTS_INVERT_BIT BIT(5) /* RTS output inversion */ 256 + #define SC16IS7XX_EFCR_IRDA_MODE_BIT BIT(7) /* IrDA mode 262 257 * 0 = rate upto 115.2 kbit/s 263 258 * - Only 75x/76x 264 259 * 1 = rate upto 1.152 Mbit/s ··· 266 261 */ 267 262 268 263 /* EFR register bits */ 269 - #define SC16IS7XX_EFR_AUTORTS_BIT (1 << 6) /* Auto RTS flow ctrl enable */ 270 - #define SC16IS7XX_EFR_AUTOCTS_BIT (1 << 7) /* Auto CTS flow ctrl enable */ 271 - #define SC16IS7XX_EFR_XOFF2_DETECT_BIT (1 << 5) /* Enable Xoff2 detection */ 272 - #define SC16IS7XX_EFR_ENABLE_BIT (1 << 4) /* Enable enhanced functions 264 + #define SC16IS7XX_EFR_AUTORTS_BIT BIT(6) /* Auto RTS flow ctrl enable */ 265 + #define SC16IS7XX_EFR_AUTOCTS_BIT BIT(7) /* Auto CTS flow ctrl enable */ 266 + #define SC16IS7XX_EFR_XOFF2_DETECT_BIT BIT(5) /* Enable Xoff2 detection */ 267 + #define SC16IS7XX_EFR_ENABLE_BIT BIT(4) /* Enable enhanced functions 273 268 * and writing to IER[7:4], 274 269 * FCR[5:4], MCR[7:5] 275 270 */ 276 - #define SC16IS7XX_EFR_SWFLOW3_BIT (1 << 3) /* SWFLOW bit 3 */ 277 - #define SC16IS7XX_EFR_SWFLOW2_BIT (1 << 2) /* SWFLOW bit 2 278 - * 271 + #define SC16IS7XX_EFR_SWFLOW3_BIT BIT(3) 272 + #define SC16IS7XX_EFR_SWFLOW2_BIT BIT(2) 273 + /* 279 274 * SWFLOW bits 3 & 2 table: 280 275 * 00 -> no transmitter flow 281 276 * control ··· 287 282 * XON1, XON2, XOFF1 and 288 283 * XOFF2 289 284 */ 290 - #define SC16IS7XX_EFR_SWFLOW1_BIT (1 << 1) /* SWFLOW bit 2 */ 291 - #define SC16IS7XX_EFR_SWFLOW0_BIT (1 << 0) /* SWFLOW bit 3 292 - * 293 - * SWFLOW bits 3 & 2 table: 285 + #define SC16IS7XX_EFR_SWFLOW1_BIT BIT(1) 286 + #define SC16IS7XX_EFR_SWFLOW0_BIT BIT(0) 287 + /* 288 + * SWFLOW bits 1 & 0 table: 294 289 * 00 -> no received flow 295 290 * control 296 291 * 01 -> receiver compares ··· 314 309 #define SC16IS7XX_FIFO_SIZE (64) 315 310 #define SC16IS7XX_GPIOS_PER_BANK 4 316 311 317 - #define SC16IS7XX_RECONF_MD (1 << 0) 318 - #define SC16IS7XX_RECONF_IER (1 << 1) 319 - #define SC16IS7XX_RECONF_RS485 (1 << 2) 312 + #define SC16IS7XX_RECONF_MD BIT(0) 313 + #define SC16IS7XX_RECONF_IER BIT(1) 314 + #define SC16IS7XX_RECONF_RS485 BIT(2) 320 315 321 316 struct sc16is7xx_one_config { 322 317 unsigned int flags;

+62 -80

drivers/tty/serial/serial_core.c

··· 407 407 /* 408 408 * Turn off DTR and RTS early. 409 409 */ 410 - if (uport && uart_console(uport) && tty) { 411 - uport->cons->cflag = tty->termios.c_cflag; 412 - uport->cons->ispeed = tty->termios.c_ispeed; 413 - uport->cons->ospeed = tty->termios.c_ospeed; 414 - } 410 + if (uport) { 411 + if (uart_console(uport) && tty) { 412 + uport->cons->cflag = tty->termios.c_cflag; 413 + uport->cons->ispeed = tty->termios.c_ispeed; 414 + uport->cons->ospeed = tty->termios.c_ospeed; 415 + } 415 416 416 - if (!tty || C_HUPCL(tty)) 417 - uart_port_dtr_rts(uport, false); 417 + if (!tty || C_HUPCL(tty)) 418 + uart_port_dtr_rts(uport, false); 419 + } 418 420 419 421 uart_port_shutdown(port); 420 422 } ··· 1104 1102 struct uart_state *state = tty->driver_data; 1105 1103 struct tty_port *port = &state->port; 1106 1104 struct uart_port *uport; 1107 - int result = -EIO; 1105 + int result; 1108 1106 1109 - mutex_lock(&port->mutex); 1107 + guard(mutex)(&port->mutex); 1108 + 1110 1109 uport = uart_port_check(state); 1111 - if (!uport) 1112 - goto out; 1110 + if (!uport || tty_io_error(tty)) 1111 + return -EIO; 1113 1112 1114 - if (!tty_io_error(tty)) { 1115 - uart_port_lock_irq(uport); 1116 - result = uport->mctrl; 1117 - result |= uport->ops->get_mctrl(uport); 1118 - uart_port_unlock_irq(uport); 1119 - } 1120 - out: 1121 - mutex_unlock(&port->mutex); 1113 + uart_port_lock_irq(uport); 1114 + result = uport->mctrl; 1115 + result |= uport->ops->get_mctrl(uport); 1116 + uart_port_unlock_irq(uport); 1117 + 1122 1118 return result; 1123 1119 } 1124 1120 ··· 1126 1126 struct uart_state *state = tty->driver_data; 1127 1127 struct tty_port *port = &state->port; 1128 1128 struct uart_port *uport; 1129 - int ret = -EIO; 1130 1129 1131 - mutex_lock(&port->mutex); 1130 + guard(mutex)(&port->mutex); 1131 + 1132 1132 uport = uart_port_check(state); 1133 - if (!uport) 1134 - goto out; 1133 + if (!uport || tty_io_error(tty)) 1134 + return -EIO; 1135 1135 1136 - if (!tty_io_error(tty)) { 1137 - uart_update_mctrl(uport, set, clear); 1138 - ret = 0; 1139 - } 1140 - out: 1141 - mutex_unlock(&port->mutex); 1142 - return ret; 1136 + uart_update_mctrl(uport, set, clear); 1137 + 1138 + return 0; 1143 1139 } 1144 1140 1145 1141 static int uart_break_ctl(struct tty_struct *tty, int break_state) ··· 1143 1147 struct uart_state *state = tty->driver_data; 1144 1148 struct tty_port *port = &state->port; 1145 1149 struct uart_port *uport; 1146 - int ret = -EIO; 1147 1150 1148 - mutex_lock(&port->mutex); 1151 + guard(mutex)(&port->mutex); 1152 + 1149 1153 uport = uart_port_check(state); 1150 1154 if (!uport) 1151 - goto out; 1155 + return -EIO; 1152 1156 1153 1157 if (uport->type != PORT_UNKNOWN && uport->ops->break_ctl) 1154 1158 uport->ops->break_ctl(uport, break_state); 1155 - ret = 0; 1156 - out: 1157 - mutex_unlock(&port->mutex); 1158 - return ret; 1159 + 1160 + return 0; 1159 1161 } 1160 1162 1161 1163 static int uart_do_autoconfig(struct tty_struct *tty, struct uart_state *state) ··· 1170 1176 * changing, and hence any extra opens of the port while 1171 1177 * we're auto-configuring. 1172 1178 */ 1173 - if (mutex_lock_interruptible(&port->mutex)) 1174 - return -ERESTARTSYS; 1179 + scoped_cond_guard(mutex_intr, return -ERESTARTSYS, &port->mutex) { 1180 + uport = uart_port_check(state); 1181 + if (!uport) 1182 + return -EIO; 1175 1183 1176 - uport = uart_port_check(state); 1177 - if (!uport) { 1178 - ret = -EIO; 1179 - goto out; 1180 - } 1184 + if (tty_port_users(port) != 1) 1185 + return -EBUSY; 1181 1186 1182 - ret = -EBUSY; 1183 - if (tty_port_users(port) == 1) { 1184 1187 uart_shutdown(tty, state); 1185 1188 1186 1189 /* ··· 1198 1207 uport->ops->config_port(uport, flags); 1199 1208 1200 1209 ret = uart_startup(tty, state, true); 1201 - if (ret == 0) 1202 - tty_port_set_initialized(port, true); 1210 + if (ret < 0) 1211 + return ret; 1203 1212 if (ret > 0) 1204 - ret = 0; 1213 + return 0; 1214 + 1215 + tty_port_set_initialized(port, true); 1205 1216 } 1206 - out: 1207 - mutex_unlock(&port->mutex); 1208 - return ret; 1217 + 1218 + return 0; 1209 1219 } 1210 1220 1211 1221 static void uart_enable_ms(struct uart_port *uport) ··· 1701 1709 unsigned int iflag_mask = IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK; 1702 1710 bool sw_changed = false; 1703 1711 1704 - mutex_lock(&state->port.mutex); 1712 + guard(mutex)(&state->port.mutex); 1713 + 1705 1714 uport = uart_port_check(state); 1706 1715 if (!uport) 1707 - goto out; 1716 + return; 1708 1717 1709 1718 /* 1710 1719 * Drivers doing software flow control also need to know ··· 1728 1735 tty->termios.c_ospeed == old_termios->c_ospeed && 1729 1736 tty->termios.c_ispeed == old_termios->c_ispeed && 1730 1737 ((tty->termios.c_iflag ^ old_termios->c_iflag) & iflag_mask) == 0 && 1731 - !sw_changed) { 1732 - goto out; 1733 - } 1738 + !sw_changed) 1739 + return; 1734 1740 1735 1741 uart_change_line_settings(tty, state, old_termios); 1736 1742 /* reload cflag from termios; port driver may have overridden flags */ ··· 1746 1754 mask |= TIOCM_RTS; 1747 1755 uart_set_mctrl(uport, mask); 1748 1756 } 1749 - out: 1750 - mutex_unlock(&state->port.mutex); 1751 1757 } 1752 1758 1753 1759 /* ··· 2039 2049 unsigned int status; 2040 2050 int mmio; 2041 2051 2042 - mutex_lock(&port->mutex); 2052 + guard(mutex)(&port->mutex); 2053 + 2043 2054 uport = uart_port_check(state); 2044 2055 if (!uport) 2045 - goto out; 2056 + return; 2046 2057 2047 2058 mmio = uport->iotype >= UPIO_MEM; 2048 2059 seq_printf(m, "%d: uart:%s %s%08llX irq:%d", ··· 2055 2064 2056 2065 if (uport->type == PORT_UNKNOWN) { 2057 2066 seq_putc(m, '\n'); 2058 - goto out; 2067 + return; 2059 2068 } 2060 2069 2061 2070 if (capable(CAP_SYS_ADMIN)) { ··· 2106 2115 seq_putc(m, '\n'); 2107 2116 #undef STATBIT 2108 2117 #undef INFOBIT 2109 - out: 2110 - mutex_unlock(&port->mutex); 2111 2118 } 2112 2119 2113 2120 static int uart_proc_show(struct seq_file *m, void *v) ··· 2382 2393 struct device *tty_dev; 2383 2394 struct uart_match match = {uport, drv}; 2384 2395 2385 - mutex_lock(&port->mutex); 2396 + guard(mutex)(&port->mutex); 2386 2397 2387 2398 tty_dev = device_find_child(&uport->port_dev->dev, &match, serial_match_port); 2388 2399 if (tty_dev && device_may_wakeup(tty_dev)) { 2389 2400 enable_irq_wake(uport->irq); 2390 2401 put_device(tty_dev); 2391 - mutex_unlock(&port->mutex); 2392 2402 return 0; 2393 2403 } 2394 2404 put_device(tty_dev); ··· 2405 2417 uart_port_unlock_irq(uport); 2406 2418 } 2407 2419 device_set_awake_path(uport->dev); 2408 - goto unlock; 2420 + return 0; 2409 2421 } 2410 2422 2411 2423 uport->suspended = 1; ··· 2448 2460 console_stop(uport->cons); 2449 2461 2450 2462 uart_change_pm(state, UART_PM_STATE_OFF); 2451 - unlock: 2452 - mutex_unlock(&port->mutex); 2453 2463 2454 2464 return 0; 2455 2465 } ··· 2461 2475 struct uart_match match = {uport, drv}; 2462 2476 struct ktermios termios; 2463 2477 2464 - mutex_lock(&port->mutex); 2478 + guard(mutex)(&port->mutex); 2465 2479 2466 2480 tty_dev = device_find_child(&uport->port_dev->dev, &match, serial_match_port); 2467 2481 if (!uport->suspended && device_may_wakeup(tty_dev)) { 2468 2482 if (irqd_is_wakeup_set(irq_get_irq_data((uport->irq)))) 2469 2483 disable_irq_wake(uport->irq); 2470 2484 put_device(tty_dev); 2471 - mutex_unlock(&port->mutex); 2472 2485 return 0; 2473 2486 } 2474 2487 put_device(tty_dev); ··· 2539 2554 2540 2555 tty_port_set_suspended(port, false); 2541 2556 } 2542 - 2543 - mutex_unlock(&port->mutex); 2544 2557 2545 2558 return 0; 2546 2559 } ··· 2679 2696 int ret = 0; 2680 2697 2681 2698 tport = &state->port; 2682 - mutex_lock(&tport->mutex); 2699 + 2700 + guard(mutex)(&tport->mutex); 2683 2701 2684 2702 port = uart_port_check(state); 2685 2703 if (!port || port->type == PORT_UNKNOWN || 2686 - !(port->ops->poll_get_char && port->ops->poll_put_char)) { 2687 - ret = -1; 2688 - goto out; 2689 - } 2704 + !(port->ops->poll_get_char && port->ops->poll_put_char)) 2705 + return -1; 2690 2706 2691 2707 pm_state = state->pm_state; 2692 2708 uart_change_pm(state, UART_PM_STATE_ON); ··· 2705 2723 ret = uart_set_options(port, NULL, baud, parity, bits, flow); 2706 2724 console_list_unlock(); 2707 2725 } 2708 - out: 2726 + 2709 2727 if (ret) 2710 2728 uart_change_pm(state, pm_state); 2711 - mutex_unlock(&tport->mutex); 2729 + 2712 2730 return ret; 2713 2731 } 2714 2732

+3 -7

drivers/tty/serial/st-asc.c

··· 808 808 uart_remove_one_port(&asc_uart_driver, port); 809 809 } 810 810 811 - #ifdef CONFIG_PM_SLEEP 812 811 static int asc_serial_suspend(struct device *dev) 813 812 { 814 813 struct uart_port *port = dev_get_drvdata(dev); ··· 821 822 822 823 return uart_resume_port(&asc_uart_driver, port); 823 824 } 824 - 825 - #endif /* CONFIG_PM_SLEEP */ 826 825 827 826 /*----------------------------------------------------------------------*/ 828 827 ··· 929 932 .cons = ASC_SERIAL_CONSOLE, 930 933 }; 931 934 932 - static const struct dev_pm_ops asc_serial_pm_ops = { 933 - SET_SYSTEM_SLEEP_PM_OPS(asc_serial_suspend, asc_serial_resume) 934 - }; 935 + static DEFINE_SIMPLE_DEV_PM_OPS(asc_serial_pm_ops, asc_serial_suspend, 936 + asc_serial_resume); 935 937 936 938 static struct platform_driver asc_serial_driver = { 937 939 .probe = asc_serial_probe, 938 940 .remove_new = asc_serial_remove, 939 941 .driver = { 940 942 .name = DRIVER_NAME, 941 - .pm = &asc_serial_pm_ops, 943 + .pm = pm_sleep_ptr(&asc_serial_pm_ops), 942 944 .of_match_table = of_match_ptr(asc_match), 943 945 }, 944 946 };

+1 -1

drivers/tty/serial/xilinx_uartps.c

··· 219 219 u32 quirks; 220 220 }; 221 221 222 - struct serial_rs485 cdns_rs485_supported = { 222 + static struct serial_rs485 cdns_rs485_supported = { 223 223 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | 224 224 SER_RS485_RTS_AFTER_SEND, 225 225 .delay_rts_before_send = 1,

+4 -7

drivers/tty/tty_io.c

··· 350 350 return ret; 351 351 352 352 prefix_length = str - name; 353 - mutex_lock(&tty_mutex); 353 + 354 + guard(mutex)(&tty_mutex); 354 355 355 356 list_for_each_entry(p, &tty_drivers, tty_drivers) 356 357 if (prefix_length == strlen(p->name) && strncmp(name, 357 358 p->name, prefix_length) == 0) { 358 359 if (index < p->num) { 359 360 *number = MKDEV(p->major, p->minor_start + index); 360 - goto out; 361 + return 0; 361 362 } 362 363 } 363 364 364 - /* if here then driver wasn't found */ 365 - ret = -ENODEV; 366 - out: 367 - mutex_unlock(&tty_mutex); 368 - return ret; 365 + return -ENODEV; 369 366 } 370 367 EXPORT_SYMBOL_GPL(tty_dev_name_to_number); 371 368

-1

drivers/usb/host/xhci-dbgcap.h

··· 110 110 struct tasklet_struct push; 111 111 112 112 struct list_head write_pool; 113 - struct kfifo write_fifo; 114 113 115 114 bool registered; 116 115 };

+9 -21

drivers/usb/host/xhci-dbgtty.c

··· 24 24 return dbc->priv; 25 25 } 26 26 27 - static unsigned int 28 - dbc_send_packet(struct dbc_port *port, char *packet, unsigned int size) 29 - { 30 - unsigned int len; 31 - 32 - len = kfifo_len(&port->write_fifo); 33 - if (len < size) 34 - size = len; 35 - if (size != 0) 36 - size = kfifo_out(&port->write_fifo, packet, size); 37 - return size; 38 - } 39 - 40 27 static int dbc_start_tx(struct dbc_port *port) 41 28 __releases(&port->port_lock) 42 29 __acquires(&port->port_lock) ··· 36 49 37 50 while (!list_empty(pool)) { 38 51 req = list_entry(pool->next, struct dbc_request, list_pool); 39 - len = dbc_send_packet(port, req->buf, DBC_MAX_PACKET); 52 + len = kfifo_out(&port->port.xmit_fifo, req->buf, DBC_MAX_PACKET); 40 53 if (len == 0) 41 54 break; 42 55 do_tty_wake = true; ··· 203 216 204 217 spin_lock_irqsave(&port->port_lock, flags); 205 218 if (count) 206 - count = kfifo_in(&port->write_fifo, buf, count); 219 + count = kfifo_in(&port->port.xmit_fifo, buf, count); 207 220 dbc_start_tx(port); 208 221 spin_unlock_irqrestore(&port->port_lock, flags); 209 222 ··· 217 230 int status; 218 231 219 232 spin_lock_irqsave(&port->port_lock, flags); 220 - status = kfifo_put(&port->write_fifo, ch); 233 + status = kfifo_put(&port->port.xmit_fifo, ch); 221 234 spin_unlock_irqrestore(&port->port_lock, flags); 222 235 223 236 return status; ··· 240 253 unsigned int room; 241 254 242 255 spin_lock_irqsave(&port->port_lock, flags); 243 - room = kfifo_avail(&port->write_fifo); 256 + room = kfifo_avail(&port->port.xmit_fifo); 244 257 spin_unlock_irqrestore(&port->port_lock, flags); 245 258 246 259 return room; ··· 253 266 unsigned int chars; 254 267 255 268 spin_lock_irqsave(&port->port_lock, flags); 256 - chars = kfifo_len(&port->write_fifo); 269 + chars = kfifo_len(&port->port.xmit_fifo); 257 270 spin_unlock_irqrestore(&port->port_lock, flags); 258 271 259 272 return chars; ··· 411 424 goto err_idr; 412 425 } 413 426 414 - ret = kfifo_alloc(&port->write_fifo, DBC_WRITE_BUF_SIZE, GFP_KERNEL); 427 + ret = kfifo_alloc(&port->port.xmit_fifo, DBC_WRITE_BUF_SIZE, 428 + GFP_KERNEL); 415 429 if (ret) 416 430 goto err_exit_port; 417 431 ··· 441 453 xhci_dbc_free_requests(&port->read_pool); 442 454 xhci_dbc_free_requests(&port->write_pool); 443 455 err_free_fifo: 444 - kfifo_free(&port->write_fifo); 456 + kfifo_free(&port->port.xmit_fifo); 445 457 err_exit_port: 446 458 idr_remove(&dbc_tty_minors, port->minor); 447 459 err_idr: ··· 466 478 idr_remove(&dbc_tty_minors, port->minor); 467 479 mutex_unlock(&dbc_tty_minors_lock); 468 480 469 - kfifo_free(&port->write_fifo); 481 + kfifo_free(&port->port.xmit_fifo); 470 482 xhci_dbc_free_requests(&port->read_pool); 471 483 xhci_dbc_free_requests(&port->read_queue); 472 484 xhci_dbc_free_requests(&port->write_pool);

+1 -1

include/linux/serial_8250.h

··· 193 193 unsigned int oldstate); 194 194 void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl); 195 195 void serial8250_do_set_divisor(struct uart_port *port, unsigned int baud, 196 - unsigned int quot, unsigned int quot_frac); 196 + unsigned int quot); 197 197 int fsl8250_handle_irq(struct uart_port *port); 198 198 int serial8250_handle_irq(struct uart_port *port, unsigned int iir); 199 199 u16 serial8250_rx_chars(struct uart_8250_port *up, u16 lsr);

+14 -10

include/linux/serial_s3c.h

··· 246 246 S5PV210_UFCON_TXTRIG4 | \ 247 247 S5PV210_UFCON_RXTRIG4) 248 248 249 - #define APPLE_S5L_UCON_RXTO_ENA 9 250 - #define APPLE_S5L_UCON_RXTHRESH_ENA 12 251 - #define APPLE_S5L_UCON_TXTHRESH_ENA 13 252 - #define APPLE_S5L_UCON_RXTO_ENA_MSK (1 << APPLE_S5L_UCON_RXTO_ENA) 253 - #define APPLE_S5L_UCON_RXTHRESH_ENA_MSK (1 << APPLE_S5L_UCON_RXTHRESH_ENA) 254 - #define APPLE_S5L_UCON_TXTHRESH_ENA_MSK (1 << APPLE_S5L_UCON_TXTHRESH_ENA) 249 + #define APPLE_S5L_UCON_RXTO_ENA 9 250 + #define APPLE_S5L_UCON_RXTO_LEGACY_ENA 11 251 + #define APPLE_S5L_UCON_RXTHRESH_ENA 12 252 + #define APPLE_S5L_UCON_TXTHRESH_ENA 13 253 + #define APPLE_S5L_UCON_RXTO_ENA_MSK BIT(APPLE_S5L_UCON_RXTO_ENA) 254 + #define APPLE_S5L_UCON_RXTO_LEGACY_ENA_MSK BIT(APPLE_S5L_UCON_RXTO_LEGACY_ENA) 255 + #define APPLE_S5L_UCON_RXTHRESH_ENA_MSK BIT(APPLE_S5L_UCON_RXTHRESH_ENA) 256 + #define APPLE_S5L_UCON_TXTHRESH_ENA_MSK BIT(APPLE_S5L_UCON_TXTHRESH_ENA) 255 257 256 258 #define APPLE_S5L_UCON_DEFAULT (S3C2410_UCON_TXIRQMODE | \ 257 259 S3C2410_UCON_RXIRQMODE | \ 258 260 S3C2410_UCON_RXFIFO_TOI) 259 261 #define APPLE_S5L_UCON_MASK (APPLE_S5L_UCON_RXTO_ENA_MSK | \ 262 + APPLE_S5L_UCON_RXTO_LEGACY_ENA_MSK | \ 260 263 APPLE_S5L_UCON_RXTHRESH_ENA_MSK | \ 261 264 APPLE_S5L_UCON_TXTHRESH_ENA_MSK) 262 265 263 - #define APPLE_S5L_UTRSTAT_RXTHRESH (1<<4) 264 - #define APPLE_S5L_UTRSTAT_TXTHRESH (1<<5) 265 - #define APPLE_S5L_UTRSTAT_RXTO (1<<9) 266 - #define APPLE_S5L_UTRSTAT_ALL_FLAGS (0x3f0) 266 + #define APPLE_S5L_UTRSTAT_RXTO_LEGACY BIT(3) 267 + #define APPLE_S5L_UTRSTAT_RXTHRESH BIT(4) 268 + #define APPLE_S5L_UTRSTAT_TXTHRESH BIT(5) 269 + #define APPLE_S5L_UTRSTAT_RXTO BIT(9) 270 + #define APPLE_S5L_UTRSTAT_ALL_FLAGS GENMASK(9, 3) 267 271 268 272 #ifndef __ASSEMBLY__ 269 273

+9

include/linux/soc/qcom/geni-se.h

··· 88 88 #define SE_GENI_M_IRQ_STATUS 0x610 89 89 #define SE_GENI_M_IRQ_EN 0x614 90 90 #define SE_GENI_M_IRQ_CLEAR 0x618 91 + #define SE_GENI_M_IRQ_EN_SET 0x61c 92 + #define SE_GENI_M_IRQ_EN_CLEAR 0x620 91 93 #define SE_GENI_S_CMD0 0x630 92 94 #define SE_GENI_S_CMD_CTRL_REG 0x634 93 95 #define SE_GENI_S_IRQ_STATUS 0x640 94 96 #define SE_GENI_S_IRQ_EN 0x644 95 97 #define SE_GENI_S_IRQ_CLEAR 0x648 98 + #define SE_GENI_S_IRQ_EN_SET 0x64c 99 + #define SE_GENI_S_IRQ_EN_CLEAR 0x650 96 100 #define SE_GENI_TX_FIFOn 0x700 97 101 #define SE_GENI_RX_FIFOn 0x780 98 102 #define SE_GENI_TX_FIFO_STATUS 0x800 ··· 105 101 #define SE_GENI_RX_WATERMARK_REG 0x810 106 102 #define SE_GENI_RX_RFR_WATERMARK_REG 0x814 107 103 #define SE_GENI_IOS 0x908 104 + #define SE_GENI_M_GP_LENGTH 0x910 105 + #define SE_GENI_S_GP_LENGTH 0x914 108 106 #define SE_DMA_TX_IRQ_STAT 0xc40 109 107 #define SE_DMA_TX_IRQ_CLR 0xc44 110 108 #define SE_DMA_TX_FSM_RST 0xc58 ··· 239 233 /* SE_GENI_IOS fields */ 240 234 #define IO2_DATA_IN BIT(1) 241 235 #define RX_DATA_IN BIT(0) 236 + 237 + /* SE_GENI_M_GP_LENGTH and SE_GENI_S_GP_LENGTH fields */ 238 + #define GP_LENGTH GENMASK(31, 0) 242 239 243 240 /* SE_DMA_TX_IRQ_STAT Register fields */ 244 241 #define TX_DMA_DONE BIT(0)

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