Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'spi-nor/for-7.1' into mtd/next
SPI NOR changes for 7.1
There is only a collection of bugfixes this time around, with no notable
changes to the core. Some of the more noteworthy bugfixes listed below.
- Enable die erase on MT35XU02GCBA. We knew this flash needed this fixup
since 7f77c561e227 ("mtd: spi-nor: micron-st: add TODO for fixing
mt35xu02gcba") but did not add it due to lack of hardware to test on.
- Fix locking on some Winbond w25q series flashes.
- Fix Auto Address Increment (AAI) writes on SST that flashes that start
on odd address. The write enable latch needs to be set again after the
single byte program.
+35
-17
+1
-1
drivers/mtd/spi-nor/core.c
+1
-1
drivers/mtd/spi-nor/core.c
···
2393
2393
/* convert the dummy cycles to the number of bytes */
2394
2394
op.dummy.nbytes = (read->num_mode_clocks + read->num_wait_states) *
2395
2395
op.dummy.buswidth / 8;
2396
-
if (spi_nor_protocol_is_dtr(nor->read_proto))
2396
+
if (spi_nor_protocol_is_dtr(read->proto))
2397
2397
op.dummy.nbytes *= 2;
2398
2398
2399
2399
return spi_nor_spimem_check_op(nor, &op);
+1
-1
drivers/mtd/spi-nor/core.h
+1
-1
drivers/mtd/spi-nor/core.h
···
413
413
* number of dummy cycles in read register ops.
414
414
* @smpt_map_id: called after map ID in SMPT table has been determined for the
415
415
* case the map ID is wrong and needs to be fixed.
416
-
* @post_sfdp: called after SFDP has been parsed (is also called for SPI NORs
416
+
* @post_sfdp: called after SFDP has been parsed (is not called for SPI NORs
417
417
* that do not support RDSFDP). Typically used to tweak various
418
418
* parameters that could not be extracted by other means (i.e.
419
419
* when information provided by the SFDP/flash_info tables are
+14
-13
drivers/mtd/spi-nor/micron-st.c
+14
-13
drivers/mtd/spi-nor/micron-st.c
···
167
167
0, 20, SPINOR_OP_MT_DTR_RD,
168
168
SNOR_PROTO_8_8_8_DTR);
169
169
170
+
/*
171
+
* Some batches of mt35xu512aba do not contain the OCT DTR command
172
+
* information, but do support OCT DTR mode. Add the settings for
173
+
* SNOR_CMD_PP_8_8_8_DTR here. This also makes sure the flash can switch
174
+
* to OCT DTR mode.
175
+
*/
176
+
nor->params->hwcaps.mask |= SNOR_HWCAPS_PP_8_8_8_DTR;
177
+
spi_nor_set_pp_settings(&nor->params->page_programs[SNOR_CMD_PP_8_8_8_DTR],
178
+
SPINOR_OP_PP_4B, SNOR_PROTO_8_8_8_DTR);
179
+
170
180
nor->cmd_ext_type = SPI_NOR_EXT_REPEAT;
171
181
nor->params->rdsr_dummy = 8;
172
182
nor->params->rdsr_addr_nbytes = 0;
···
195
185
.post_sfdp = mt35xu512aba_post_sfdp_fixup,
196
186
};
197
187
198
-
static const struct spi_nor_fixups mt35xu01gbba_fixups = {
188
+
static const struct spi_nor_fixups mt35_two_die_fixups = {
199
189
.post_sfdp = mt35xu512aba_post_sfdp_fixup,
200
190
.late_init = micron_st_nor_two_die_late_init,
201
191
};
···
212
202
.id = SNOR_ID(0x2c, 0x5b, 0x1b),
213
203
.mfr_flags = USE_FSR,
214
204
.fixup_flags = SPI_NOR_IO_MODE_EN_VOLATILE,
215
-
.fixups = &mt35xu01gbba_fixups,
205
+
.fixups = &mt35_two_die_fixups,
216
206
}, {
217
-
/*
218
-
* The MT35XU02GCBA flash device does not support chip erase,
219
-
* according to its datasheet. It supports die erase, which
220
-
* means the current driver implementation will likely need to
221
-
* be converted to use die erase. Furthermore, similar to the
222
-
* MT35XU01GBBA, the SPI_NOR_IO_MODE_EN_VOLATILE flag probably
223
-
* needs to be enabled.
224
-
*
225
-
* TODO: Fix these and test on real hardware.
226
-
*/
227
207
.id = SNOR_ID(0x2c, 0x5b, 0x1c),
228
208
.name = "mt35xu02g",
229
209
.sector_size = SZ_128K,
230
210
.size = SZ_256M,
231
211
.no_sfdp_flags = SECT_4K | SPI_NOR_OCTAL_READ,
232
212
.mfr_flags = USE_FSR,
233
-
.fixup_flags = SPI_NOR_4B_OPCODES,
213
+
.fixup_flags = SPI_NOR_4B_OPCODES | SPI_NOR_IO_MODE_EN_VOLATILE,
214
+
.fixups = &mt35_two_die_fixups,
234
215
},
235
216
};
236
217
+13
drivers/mtd/spi-nor/sst.c
+13
drivers/mtd/spi-nor/sst.c
···
203
203
204
204
/* Start write from odd address. */
205
205
if (to % 2) {
206
+
bool needs_write_enable = (len > 1);
207
+
206
208
/* write one byte. */
207
209
ret = sst_nor_write_data(nor, to, 1, buf);
208
210
if (ret < 0)
···
212
210
213
211
to++;
214
212
actual++;
213
+
214
+
/*
215
+
* Byte program clears the write enable latch. If more
216
+
* data needs to be written using the AAI sequence,
217
+
* re-enable writes.
218
+
*/
219
+
if (needs_write_enable) {
220
+
ret = spi_nor_write_enable(nor);
221
+
if (ret)
222
+
goto out;
223
+
}
215
224
}
216
225
217
226
/* Write out most of the data here. */
+3
-1
drivers/mtd/spi-nor/swp.c
+3
-1
drivers/mtd/spi-nor/swp.c
+3
-1
drivers/mtd/spi-nor/winbond.c
+3
-1
drivers/mtd/spi-nor/winbond.c
···
274
274
.id = SNOR_ID(0xef, 0x60, 0x19),
275
275
.name = "w25q256jw",
276
276
.size = SZ_32M,
277
+
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 | SPI_NOR_4BIT_BP,
277
278
.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
278
279
}, {
279
280
.id = SNOR_ID(0xef, 0x60, 0x20),
···
296
295
.id = SNOR_ID(0xef, 0x70, 0x17),
297
296
.name = "w25q64jvm",
298
297
.size = SZ_8M,
298
+
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB,
299
299
.no_sfdp_flags = SECT_4K,
300
300
}, {
301
301
.id = SNOR_ID(0xef, 0x70, 0x18),
···
339
337
.id = SNOR_ID(0xef, 0x80, 0x19),
340
338
.name = "w25q256jwm",
341
339
.size = SZ_32M,
342
-
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB,
340
+
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 | SPI_NOR_4BIT_BP,
343
341
.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
344
342
}, {
345
343
.id = SNOR_ID(0xef, 0x80, 0x20),