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pwm: sifive: Enable clk only after period check in .apply()

For the period check and the initial calculations of register values there
is no hardware access needed. So delay enabling the clk a bit to simplify
the code flow a bit.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Tested-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>

authored by

Uwe Kleine-König and committed by
Thierry Reding
3586b026 0f02f491

+8 -10
+8 -10
drivers/pwm/pwm-sifive.c
··· 139 139 if (state->polarity != PWM_POLARITY_INVERSED) 140 140 return -EINVAL; 141 141 142 - ret = clk_enable(ddata->clk); 143 - if (ret) { 144 - dev_err(ddata->chip.dev, "Enable clk failed\n"); 145 - return ret; 146 - } 147 - 148 142 cur_state = pwm->state; 149 143 enabled = cur_state.enabled; 150 144 ··· 161 167 if (state->period != ddata->approx_period) { 162 168 if (ddata->user_count != 1) { 163 169 mutex_unlock(&ddata->lock); 164 - ret = -EBUSY; 165 - goto exit; 170 + return -EBUSY; 166 171 } 167 172 ddata->approx_period = state->period; 168 173 pwm_sifive_update_clock(ddata, clk_get_rate(ddata->clk)); 169 174 } 170 175 mutex_unlock(&ddata->lock); 176 + 177 + ret = clk_enable(ddata->clk); 178 + if (ret) { 179 + dev_err(ddata->chip.dev, "Enable clk failed\n"); 180 + return ret; 181 + } 171 182 172 183 writel(frac, ddata->regs + PWM_SIFIVE_PWMCMP(pwm->hwpwm)); 173 184 ··· 185 186 } 186 187 } 187 188 188 - exit: 189 189 clk_disable(ddata->clk); 190 - return ret; 190 + return 0; 191 191 } 192 192 193 193 static const struct pwm_ops pwm_sifive_ops = {