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dt-bindings: clock: Add Qualcomm QCS615 Graphics clock controller

Add DT bindings for the Graphics clock on QCS615 platforms. Add the
relevant DT include definitions as well.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20250702-qcs615-mm-v10-clock-controllers-v11-6-9c216e1615ab@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

authored by

Taniya Das and committed by
Bjorn Andersson 3590dfbd 9b47105f

+88
+49
Documentation/devicetree/bindings/clock/qcom,qcs615-gpucc.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/clock/qcom,qcs615-gpucc.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Qualcomm Graphics Clock & Reset Controller on QCS615 8 + 9 + maintainers: 10 + - Taniya Das <quic_tdas@quicinc.com> 11 + 12 + description: | 13 + Qualcomm graphics clock control module provides clocks, resets and power 14 + domains on QCS615 Qualcomm SoCs. 15 + 16 + See also: include/dt-bindings/clock/qcom,qcs615-gpucc.h 17 + 18 + properties: 19 + compatible: 20 + const: qcom,qcs615-gpucc 21 + 22 + clocks: 23 + items: 24 + - description: Board XO source 25 + - description: GPLL0 main branch source 26 + - description: GPLL0 GPUCC div branch source 27 + 28 + allOf: 29 + - $ref: qcom,gcc.yaml# 30 + 31 + unevaluatedProperties: false 32 + 33 + examples: 34 + - | 35 + #include <dt-bindings/clock/qcom,rpmh.h> 36 + #include <dt-bindings/clock/qcom,qcs615-gcc.h> 37 + 38 + clock-controller@5090000 { 39 + compatible = "qcom,qcs615-gpucc"; 40 + reg = <0x5090000 0x9000>; 41 + clocks = <&rpmhcc RPMH_CXO_CLK>, 42 + <&gcc GPLL0>, 43 + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 44 + 45 + #clock-cells = <1>; 46 + #reset-cells = <1>; 47 + #power-domain-cells = <1>; 48 + }; 49 + ...
+39
include/dt-bindings/clock/qcom,qcs615-gpucc.h
··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + /* 3 + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 + */ 5 + 6 + #ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_QCS615_H 7 + #define _DT_BINDINGS_CLK_QCOM_GPU_CC_QCS615_H 8 + 9 + /* GPU_CC clocks */ 10 + #define CRC_DIV_PLL0 0 11 + #define CRC_DIV_PLL1 1 12 + #define GPU_CC_PLL0 2 13 + #define GPU_CC_PLL1 3 14 + #define GPU_CC_CRC_AHB_CLK 4 15 + #define GPU_CC_CX_GFX3D_CLK 5 16 + #define GPU_CC_CX_GFX3D_SLV_CLK 6 17 + #define GPU_CC_CX_GMU_CLK 7 18 + #define GPU_CC_CX_SNOC_DVM_CLK 8 19 + #define GPU_CC_CXO_AON_CLK 9 20 + #define GPU_CC_CXO_CLK 10 21 + #define GPU_CC_GMU_CLK_SRC 11 22 + #define GPU_CC_GX_GFX3D_CLK 12 23 + #define GPU_CC_GX_GFX3D_CLK_SRC 13 24 + #define GPU_CC_GX_GMU_CLK 14 25 + #define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 15 26 + #define GPU_CC_SLEEP_CLK 16 27 + 28 + /* GPU_CC power domains */ 29 + #define CX_GDSC 0 30 + #define GX_GDSC 1 31 + 32 + /* GPU_CC resets */ 33 + #define GPU_CC_CX_BCR 0 34 + #define GPU_CC_GFX3D_AON_BCR 1 35 + #define GPU_CC_GMU_BCR 2 36 + #define GPU_CC_GX_BCR 3 37 + #define GPU_CC_XO_BCR 4 38 + 39 + #endif