phy: qcom-qmp: pcs-v3: add missing registers

+82

1 changed file

expand all

drivers

phy

qualcomm

phy-qcom-qmp-pcs-v3.h

+82

drivers/phy/qualcomm/phy-qcom-qmp-pcs-v3.h

··· 7 7 #define QCOM_PHY_QMP_PCS_V3_H_ 8 8 9 9 /* Only for QMP V3 PHY - PCS registers */ 10 + #define QPHY_V3_PCS_SW_RESET 0x000 10 11 #define QPHY_V3_PCS_POWER_DOWN_CONTROL 0x004 12 + #define QPHY_V3_PCS_START_CONTROL 0x008 11 13 #define QPHY_V3_PCS_TXMGN_V0 0x00c 12 14 #define QPHY_V3_PCS_TXMGN_V1 0x010 13 15 #define QPHY_V3_PCS_TXMGN_V2 0x014 ··· 33 31 #define QPHY_V3_PCS_RATE_SLEW_CNTRL 0x05c 34 32 #define QPHY_V3_PCS_POWER_STATE_CONFIG1 0x060 35 33 #define QPHY_V3_PCS_POWER_STATE_CONFIG2 0x064 34 + #define QPHY_V3_PCS_POWER_STATE_CONFIG3 0x068 36 35 #define QPHY_V3_PCS_POWER_STATE_CONFIG4 0x06c 37 36 #define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L 0x070 38 37 #define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H 0x074 ··· 43 40 #define QPHY_V3_PCS_LOCK_DETECT_CONFIG2 0x084 44 41 #define QPHY_V3_PCS_LOCK_DETECT_CONFIG3 0x088 45 42 #define QPHY_V3_PCS_TSYNC_RSYNC_TIME 0x08c 43 + #define QPHY_V3_PCS_SIGDET_LOW_2_IDLE_TIME 0x090 44 + #define QPHY_V3_PCS_BEACON_2_IDLE_TIME_L 0x094 45 + #define QPHY_V3_PCS_BEACON_2_IDLE_TIME_H 0x098 46 + #define QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_SYSCLK 0x09c 46 47 #define QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x0a0 47 48 #define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0x0a4 48 49 #define QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME 0x0a8 50 + #define QPHY_V3_PCS_LFPS_DET_HIGH_COUNT_VAL 0x0ac 49 51 #define QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK 0x0b0 52 + #define QPHY_V3_PCS_LFPS_TX_END_CNT_P2U3_START 0x0b4 50 53 #define QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME 0x0b8 51 54 #define QPHY_V3_PCS_RXEQTRAINING_RUN_TIME 0x0bc 55 + #define QPHY_V3_PCS_TXONESZEROS_RUN_LENGTH 0x0c0 52 56 #define QPHY_V3_PCS_FLL_CNTRL1 0x0c4 53 57 #define QPHY_V3_PCS_FLL_CNTRL2 0x0c8 54 58 #define QPHY_V3_PCS_FLL_CNT_VAL_L 0x0cc 55 59 #define QPHY_V3_PCS_FLL_CNT_VAL_H_TOL 0x0d0 56 60 #define QPHY_V3_PCS_FLL_MAN_CODE 0x0d4 61 + #define QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL 0x0d8 62 + #define QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR 0x0dc 63 + #define QPHY_V3_PCS_ARCVR_DTCT_EN_PERIOD 0x0e0 64 + #define QPHY_V3_PCS_ARCVR_DTCT_CM_DLY 0x0e4 65 + #define QPHY_V3_PCS_ALFPS_DEGLITCH_VAL 0x0e8 66 + #define QPHY_V3_PCS_INSIG_SW_CTRL1 0x0ec 67 + #define QPHY_V3_PCS_INSIG_SW_CTRL2 0x0f0 68 + #define QPHY_V3_PCS_INSIG_SW_CTRL3 0x0f4 69 + #define QPHY_V3_PCS_INSIG_MX_CTRL1 0x0f8 70 + #define QPHY_V3_PCS_INSIG_MX_CTRL2 0x0fc 71 + #define QPHY_V3_PCS_INSIG_MX_CTRL3 0x100 72 + #define QPHY_V3_PCS_OUTSIG_SW_CTRL1 0x104 73 + #define QPHY_V3_PCS_OUTSIG_MX_CTRL1 0x108 74 + #define QPHY_V3_PCS_CLK_DEBUG_BYPASS_CTRL 0x10c 75 + #define QPHY_V3_PCS_TEST_CONTROL 0x110 76 + #define QPHY_V3_PCS_TEST_CONTROL2 0x114 77 + #define QPHY_V3_PCS_TEST_CONTROL3 0x118 78 + #define QPHY_V3_PCS_TEST_CONTROL4 0x11c 79 + #define QPHY_V3_PCS_TEST_CONTROL5 0x120 80 + #define QPHY_V3_PCS_TEST_CONTROL6 0x124 81 + #define QPHY_V3_PCS_TEST_CONTROL7 0x128 82 + #define QPHY_V3_PCS_COM_RESET_CONTROL 0x12c 83 + #define QPHY_V3_PCS_BIST_CTRL 0x130 84 + #define QPHY_V3_PCS_PRBS_POLY0 0x134 85 + #define QPHY_V3_PCS_PRBS_POLY1 0x138 86 + #define QPHY_V3_PCS_PRBS_SEED0 0x13c 87 + #define QPHY_V3_PCS_PRBS_SEED1 0x140 88 + #define QPHY_V3_PCS_FIXED_PAT_CTRL 0x144 89 + #define QPHY_V3_PCS_FIXED_PAT0 0x148 90 + #define QPHY_V3_PCS_FIXED_PAT1 0x14c 91 + #define QPHY_V3_PCS_FIXED_PAT2 0x150 92 + #define QPHY_V3_PCS_FIXED_PAT3 0x154 93 + #define QPHY_V3_PCS_COM_CLK_SWITCH_CTRL 0x158 94 + #define QPHY_V3_PCS_ELECIDLE_DLY_SEL 0x15c 95 + #define QPHY_V3_PCS_SPARE1 0x160 96 + #define QPHY_V3_PCS_BIST_CHK_ERR_CNT_L_STATUS 0x164 97 + #define QPHY_V3_PCS_BIST_CHK_ERR_CNT_H_STATUS 0x168 98 + #define QPHY_V3_PCS_BIST_CHK_STATUS 0x16c 99 + #define QPHY_V3_PCS_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x170 100 + #define QPHY_V3_PCS_PCS_STATUS 0x174 101 + #define QPHY_V3_PCS_PCS_STATUS2 0x178 102 + #define QPHY_V3_PCS_PCS_STATUS3 0x17c 103 + #define QPHY_V3_PCS_COM_RESET_STATUS 0x180 104 + #define QPHY_V3_PCS_OSC_DTCT_STATUS 0x184 105 + #define QPHY_V3_PCS_REVISION_ID0 0x188 106 + #define QPHY_V3_PCS_REVISION_ID1 0x18c 107 + #define QPHY_V3_PCS_REVISION_ID2 0x190 108 + #define QPHY_V3_PCS_REVISION_ID3 0x194 109 + #define QPHY_V3_PCS_DEBUG_BUS_0_STATUS 0x198 110 + #define QPHY_V3_PCS_DEBUG_BUS_1_STATUS 0x19c 111 + #define QPHY_V3_PCS_DEBUG_BUS_2_STATUS 0x1a0 112 + #define QPHY_V3_PCS_DEBUG_BUS_3_STATUS 0x1a4 57 113 #define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1a8 58 114 #define QPHY_V3_PCS_OSC_DTCT_ACTIONS 0x1ac 59 115 #define QPHY_V3_PCS_SIGDET_CNTRL 0x1b0 116 + #define QPHY_V3_PCS_IDAC_CAL_CNTRL 0x1b4 117 + #define QPHY_V3_PCS_CMN_ACK_OUT_SEL 0x1b8 118 + #define QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME_SYSCLK 0x1bc 119 + #define QPHY_V3_PCS_AUTONOMOUS_MODE_STATUS 0x1c0 120 + #define QPHY_V3_PCS_ENDPOINT_REFCLK_CNTRL 0x1c4 121 + #define QPHY_V3_PCS_EPCLK_PRE_PLL_LOCK_DLY_SYSCLK 0x1c8 122 + #define QPHY_V3_PCS_EPCLK_PRE_PLL_LOCK_DLY_AUXCLK 0x1cc 123 + #define QPHY_V3_PCS_EPCLK_DLY_COUNT_VAL_L 0x1d0 124 + #define QPHY_V3_PCS_EPCLK_DLY_COUNT_VAL_H 0x1d4 60 125 #define QPHY_V3_PCS_RX_SIGDET_LVL 0x1d8 61 126 #define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc 62 127 #define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0 128 + #define QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL2 0x1e4 129 + #define QPHY_V3_PCS_RXTERMINATION_DLY_SEL 0x1e8 130 + #define QPHY_V3_PCS_LFPS_PER_TIMER_VAL 0x1ec 131 + #define QPHY_V3_PCS_SIGDET_STARTUP_TIMER_VAL 0x1f0 132 + #define QPHY_V3_PCS_LOCK_DETECT_CONFIG4 0x1f4 133 + #define QPHY_V3_PCS_RX_SIGDET_DTCT_CNTRL 0x1f8 134 + #define QPHY_V3_PCS_PCS_STATUS4 0x1fc 135 + #define QPHY_V3_PCS_PCS_STATUS4_CLEAR 0x200 136 + #define QPHY_V3_PCS_DEC_ERROR_COUNT_STATUS 0x204 137 + #define QPHY_V3_PCS_COMMA_POS_STATUS 0x208 63 138 #define QPHY_V3_PCS_REFGEN_REQ_CONFIG1 0x20c 64 139 #define QPHY_V3_PCS_REFGEN_REQ_CONFIG2 0x210 140 + #define QPHY_V3_PCS_REFGEN_REQ_CONFIG3 0x214 65 141 66 142 #endif

Configure Feed

Configure Feed