Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
pmdomain: Merge branch dt into next
Merge the immutable branch dt into next, to allow the DT bindings to be
tested together with changes that are targeted for v6.19.
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+234
-6
+117
Documentation/devicetree/bindings/power/mediatek,mt8196-gpufreq.yaml
+117
Documentation/devicetree/bindings/power/mediatek,mt8196-gpufreq.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/power/mediatek,mt8196-gpufreq.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: MediaTek MFlexGraphics Power and Frequency Controller
8
+
9
+
maintainers:
10
+
- Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
11
+
12
+
description:
13
+
A special-purpose embedded MCU to control power and frequency of GPU devices
14
+
using MediaTek Flexible Graphics integration hardware.
15
+
16
+
properties:
17
+
$nodename:
18
+
pattern: '^power-controller@[a-f0-9]+$'
19
+
20
+
compatible:
21
+
enum:
22
+
- mediatek,mt8196-gpufreq
23
+
24
+
reg:
25
+
items:
26
+
- description: GPR memory area
27
+
- description: RPC memory area
28
+
- description: SoC variant ID register
29
+
30
+
reg-names:
31
+
items:
32
+
- const: gpr
33
+
- const: rpc
34
+
- const: hw-revision
35
+
36
+
clocks:
37
+
items:
38
+
- description: main clock of the embedded controller (EB)
39
+
- description: core PLL
40
+
- description: stack 0 PLL
41
+
- description: stack 1 PLL
42
+
43
+
clock-names:
44
+
items:
45
+
- const: eb
46
+
- const: core
47
+
- const: stack0
48
+
- const: stack1
49
+
50
+
mboxes:
51
+
items:
52
+
- description: FastDVFS events
53
+
- description: frequency control
54
+
- description: sleep control
55
+
- description: timer control
56
+
- description: frequency hopping control
57
+
- description: hardware voter control
58
+
- description: FastDVFS control
59
+
60
+
mbox-names:
61
+
items:
62
+
- const: fast-dvfs-event
63
+
- const: gpufreq
64
+
- const: sleep
65
+
- const: timer
66
+
- const: fhctl
67
+
- const: ccf
68
+
- const: fast-dvfs
69
+
70
+
memory-region:
71
+
items:
72
+
- description: phandle to the GPUEB shared memory
73
+
74
+
"#clock-cells":
75
+
const: 1
76
+
77
+
"#power-domain-cells":
78
+
const: 0
79
+
80
+
required:
81
+
- compatible
82
+
- reg
83
+
- reg-names
84
+
- clocks
85
+
- clock-names
86
+
- mboxes
87
+
- mbox-names
88
+
- memory-region
89
+
- "#clock-cells"
90
+
- "#power-domain-cells"
91
+
92
+
additionalProperties: false
93
+
94
+
examples:
95
+
- |
96
+
#include <dt-bindings/clock/mediatek,mt8196-clock.h>
97
+
98
+
power-controller@4b09fd00 {
99
+
compatible = "mediatek,mt8196-gpufreq";
100
+
reg = <0x4b09fd00 0x80>,
101
+
<0x4b800000 0x1000>,
102
+
<0x4b860128 0x4>;
103
+
reg-names = "gpr", "rpc", "hw-revision";
104
+
clocks = <&topckgen CLK_TOP_MFG_EB>,
105
+
<&mfgpll CLK_MFG_AO_MFGPLL>,
106
+
<&mfgpll_sc0 CLK_MFGSC0_AO_MFGPLL_SC0>,
107
+
<&mfgpll_sc1 CLK_MFGSC1_AO_MFGPLL_SC1>;
108
+
clock-names = "eb", "core", "stack0", "stack1";
109
+
mboxes = <&gpueb_mbox 0>, <&gpueb_mbox 1>, <&gpueb_mbox 2>,
110
+
<&gpueb_mbox 3>, <&gpueb_mbox 4>, <&gpueb_mbox 5>,
111
+
<&gpueb_mbox 7>;
112
+
mbox-names = "fast-dvfs-event", "gpufreq", "sleep", "timer", "fhctl",
113
+
"ccf", "fast-dvfs";
114
+
memory-region = <&gpueb_shared_memory>;
115
+
#clock-cells = <1>;
116
+
#power-domain-cells = <0>;
117
+
};
+4
Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
+4
Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
···
33
33
- mediatek,mt8188-power-controller
34
34
- mediatek,mt8192-power-controller
35
35
- mediatek,mt8195-power-controller
36
+
- mediatek,mt8196-hwv-hfrp-power-controller
37
+
- mediatek,mt8196-hwv-scp-power-controller
38
+
- mediatek,mt8196-power-controller
36
39
- mediatek,mt8365-power-controller
37
40
38
41
'#power-domain-cells':
···
160
157
contains:
161
158
enum:
162
159
- mediatek,mt8183-power-controller
160
+
- mediatek,mt8196-power-controller
163
161
then:
164
162
properties:
165
163
access-controllers:
+1
Documentation/devicetree/bindings/power/qcom,rpmpd.yaml
+1
Documentation/devicetree/bindings/power/qcom,rpmpd.yaml
+2
Documentation/devicetree/bindings/power/rockchip,power-controller.yaml
+2
Documentation/devicetree/bindings/power/rockchip,power-controller.yaml
···
46
46
- rockchip,rk3576-power-controller
47
47
- rockchip,rk3588-power-controller
48
48
- rockchip,rv1126-power-controller
49
+
- rockchip,rv1126b-power-controller
49
50
50
51
"#power-domain-cells":
51
52
const: 1
···
127
126
"include/dt-bindings/power/rk3568-power.h"
128
127
"include/dt-bindings/power/rk3588-power.h"
129
128
"include/dt-bindings/power/rockchip,rv1126-power.h"
129
+
"include/dt-bindings/power/rockchip,rv1126b-power-controller.h"
130
130
131
131
clocks:
132
132
minItems: 1
+32
-6
Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-pm.yaml
+32
-6
Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-pm.yaml
···
13
13
maintainers:
14
14
- Nicolas Saenz Julienne <nsaenz@kernel.org>
15
15
16
-
allOf:
17
-
- $ref: /schemas/watchdog/watchdog.yaml#
18
-
19
16
properties:
20
17
compatible:
21
18
items:
22
19
- enum:
23
20
- brcm,bcm2835-pm
24
21
- brcm,bcm2711-pm
22
+
- brcm,bcm2712-pm
25
23
- const: brcm,bcm2835-pm-wdt
26
24
27
25
reg:
28
-
minItems: 2
26
+
minItems: 1
29
27
maxItems: 3
30
28
31
29
reg-names:
32
-
minItems: 2
30
+
minItems: 1
33
31
items:
34
32
- const: pm
35
33
- const: asb
···
60
62
- reg
61
63
- "#power-domain-cells"
62
64
- "#reset-cells"
63
-
- clocks
65
+
66
+
allOf:
67
+
- $ref: /schemas/watchdog/watchdog.yaml#
68
+
69
+
- if:
70
+
properties:
71
+
compatible:
72
+
contains:
73
+
enum:
74
+
- brcm,bcm2835-pm
75
+
- brcm,bcm2711-pm
76
+
then:
77
+
required:
78
+
- clocks
79
+
80
+
properties:
81
+
reg:
82
+
minItems: 2
83
+
84
+
reg-names:
85
+
minItems: 2
86
+
87
+
else:
88
+
properties:
89
+
reg:
90
+
maxItems: 1
91
+
92
+
reg-names:
93
+
maxItems: 1
64
94
65
95
additionalProperties: false
66
96
+58
include/dt-bindings/power/mediatek,mt8196-power.h
+58
include/dt-bindings/power/mediatek,mt8196-power.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
2
+
/*
3
+
* Copyright (c) 2025 Collabora Ltd
4
+
* AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
5
+
*/
6
+
7
+
#ifndef _DT_BINDINGS_POWER_MT8196_POWER_H
8
+
#define _DT_BINDINGS_POWER_MT8196_POWER_H
9
+
10
+
/* SCPSYS Secure Power Manager - Direct Control */
11
+
#define MT8196_POWER_DOMAIN_MD 0
12
+
#define MT8196_POWER_DOMAIN_CONN 1
13
+
#define MT8196_POWER_DOMAIN_SSUSB_P0 2
14
+
#define MT8196_POWER_DOMAIN_SSUSB_DP_PHY_P0 3
15
+
#define MT8196_POWER_DOMAIN_SSUSB_P1 4
16
+
#define MT8196_POWER_DOMAIN_SSUSB_P23 5
17
+
#define MT8196_POWER_DOMAIN_SSUSB_PHY_P2 6
18
+
#define MT8196_POWER_DOMAIN_PEXTP_MAC0 7
19
+
#define MT8196_POWER_DOMAIN_PEXTP_MAC1 8
20
+
#define MT8196_POWER_DOMAIN_PEXTP_MAC2 9
21
+
#define MT8196_POWER_DOMAIN_PEXTP_PHY0 10
22
+
#define MT8196_POWER_DOMAIN_PEXTP_PHY1 11
23
+
#define MT8196_POWER_DOMAIN_PEXTP_PHY2 12
24
+
#define MT8196_POWER_DOMAIN_AUDIO 13
25
+
#define MT8196_POWER_DOMAIN_ADSP_TOP_DORMANT 14
26
+
#define MT8196_POWER_DOMAIN_ADSP_INFRA 15
27
+
#define MT8196_POWER_DOMAIN_ADSP_AO 16
28
+
29
+
/* SCPSYS Secure Power Manager - HW Voter */
30
+
#define MT8196_POWER_DOMAIN_MM_PROC_DORMANT 0
31
+
#define MT8196_POWER_DOMAIN_SSR 1
32
+
33
+
/* HFRPSYS MultiMedia Power Control (MMPC) - HW Voter */
34
+
#define MT8196_POWER_DOMAIN_VDE0 0
35
+
#define MT8196_POWER_DOMAIN_VDE1 1
36
+
#define MT8196_POWER_DOMAIN_VDE_VCORE0 2
37
+
#define MT8196_POWER_DOMAIN_VEN0 3
38
+
#define MT8196_POWER_DOMAIN_VEN1 4
39
+
#define MT8196_POWER_DOMAIN_VEN2 5
40
+
#define MT8196_POWER_DOMAIN_DISP_VCORE 6
41
+
#define MT8196_POWER_DOMAIN_DIS0_DORMANT 7
42
+
#define MT8196_POWER_DOMAIN_DIS1_DORMANT 8
43
+
#define MT8196_POWER_DOMAIN_OVL0_DORMANT 9
44
+
#define MT8196_POWER_DOMAIN_OVL1_DORMANT 10
45
+
#define MT8196_POWER_DOMAIN_DISP_EDPTX_DORMANT 11
46
+
#define MT8196_POWER_DOMAIN_DISP_DPTX_DORMANT 12
47
+
#define MT8196_POWER_DOMAIN_MML0_SHUTDOWN 13
48
+
#define MT8196_POWER_DOMAIN_MML1_SHUTDOWN 14
49
+
#define MT8196_POWER_DOMAIN_MM_INFRA0 15
50
+
#define MT8196_POWER_DOMAIN_MM_INFRA1 16
51
+
#define MT8196_POWER_DOMAIN_MM_INFRA_AO 17
52
+
#define MT8196_POWER_DOMAIN_CSI_BS_RX 18
53
+
#define MT8196_POWER_DOMAIN_CSI_LS_RX 19
54
+
#define MT8196_POWER_DOMAIN_DSI_PHY0 20
55
+
#define MT8196_POWER_DOMAIN_DSI_PHY1 21
56
+
#define MT8196_POWER_DOMAIN_DSI_PHY2 22
57
+
58
+
#endif /* _DT_BINDINGS_POWER_MT8196_POWER_H */
+3
include/dt-bindings/power/qcom,rpmhpd.h
+3
include/dt-bindings/power/qcom,rpmhpd.h
···
33
33
#define RPMH_REGULATOR_LEVEL_RETENTION 16
34
34
#define RPMH_REGULATOR_LEVEL_MIN_SVS 48
35
35
#define RPMH_REGULATOR_LEVEL_LOW_SVS_D3 50
36
+
#define RPMH_REGULATOR_LEVEL_LOW_SVS_D2_1 51
36
37
#define RPMH_REGULATOR_LEVEL_LOW_SVS_D2 52
38
+
#define RPMH_REGULATOR_LEVEL_LOW_SVS_D1_1 54
37
39
#define RPMH_REGULATOR_LEVEL_LOW_SVS_D1 56
38
40
#define RPMH_REGULATOR_LEVEL_LOW_SVS_D0 60
39
41
#define RPMH_REGULATOR_LEVEL_LOW_SVS 64
40
42
#define RPMH_REGULATOR_LEVEL_LOW_SVS_P1 72
43
+
#define RPMH_REGULATOR_LEVEL_LOW_SVS_L0 76
41
44
#define RPMH_REGULATOR_LEVEL_LOW_SVS_L1 80
42
45
#define RPMH_REGULATOR_LEVEL_LOW_SVS_L2 96
43
46
#define RPMH_REGULATOR_LEVEL_SVS 128
+17
include/dt-bindings/power/rockchip,rv1126b-power-controller.h
+17
include/dt-bindings/power/rockchip,rv1126b-power-controller.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
2
+
/*
3
+
* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
4
+
* Author: Finley Xiao <finley.xiao@rock-chips.com>
5
+
*/
6
+
7
+
#ifndef __DT_BINDINGS_POWER_RV1126B_POWER_CONTROLLER_H__
8
+
#define __DT_BINDINGS_POWER_RV1126B_POWER_CONTROLLER_H__
9
+
10
+
/* VD_NPU */
11
+
#define RV1126B_PD_NPU 0
12
+
13
+
/* VD_LOGIC */
14
+
#define RV1126B_PD_VDO 1
15
+
#define RV1126B_PD_AIISP 2
16
+
17
+
#endif