Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie:
"Definitely seems quieter this week,
Radeon, intel, intel broadwell, vmwgfx, ttm, armada, and a couple of
core fixes, one revert in radeon
Most of these are either going to stable or fixes for things
introduced in the merge window"
* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: (30 commits)
drm/edid: add quirk for BPC in Samsung NP700G7A-S01PL notebook
drm/ttm: Fix accesses through vmas with only partial coverage
drm/nouveau: only runtime suspend by default in optimus configuration
drm: don't double-free on driver load error
Revert "drm/radeon: Implement radeon_pci_shutdown"
drm/radeon: add missing display tiling setup for oland
drm/radeon: fix typo in cik_copy_dma
drm/radeon/cik: plug in missing blit callback
drm/radeon/dpm: Fix hwmon crash
drm/radeon: Fix sideport problems on certain RS690 boards
drm/i915: don't update the dri1 breadcrumb with modesetting
DRM: Armada: prime refcounting bug fix
DRM: Armada: fix printing of phys_addr_t/dma_addr_t
DRM: Armada: destroy framebuffer after helper
DRM: Armada: implement lastclose() for fbhelper
drm/i915: Repeat eviction search after idling the GPU
drm/vmwgfx: Add max surface memory param
drm/i915: Fix use-after-free in do_switch
drm/i915: fix pm init ordering
drm/i915: Hold mutex across i915_gem_release
...
+171
-58
+1
drivers/gpu/drm/armada/armada_drm.h
+1
drivers/gpu/drm/armada/armada_drm.h
···
103
103
extern const struct drm_mode_config_funcs armada_drm_mode_config_funcs;
104
104
105
105
int armada_fbdev_init(struct drm_device *);
106
+
void armada_fbdev_lastclose(struct drm_device *);
106
107
void armada_fbdev_fini(struct drm_device *);
107
108
108
109
int armada_overlay_plane_create(struct drm_device *, unsigned long);
+6
-1
drivers/gpu/drm/armada/armada_drv.c
+6
-1
drivers/gpu/drm/armada/armada_drv.c
···
321
321
DRM_UNLOCKED),
322
322
};
323
323
324
+
static void armada_drm_lastclose(struct drm_device *dev)
325
+
{
326
+
armada_fbdev_lastclose(dev);
327
+
}
328
+
324
329
static const struct file_operations armada_drm_fops = {
325
330
.owner = THIS_MODULE,
326
331
.llseek = no_llseek,
···
342
337
.open = NULL,
343
338
.preclose = NULL,
344
339
.postclose = NULL,
345
-
.lastclose = NULL,
340
+
.lastclose = armada_drm_lastclose,
346
341
.unload = armada_drm_unload,
347
342
.get_vblank_counter = drm_vblank_count,
348
343
.enable_vblank = armada_drm_enable_vblank,
+15
-5
drivers/gpu/drm/armada/armada_fbdev.c
+15
-5
drivers/gpu/drm/armada/armada_fbdev.c
···
105
105
drm_fb_helper_fill_fix(info, dfb->fb.pitches[0], dfb->fb.depth);
106
106
drm_fb_helper_fill_var(info, fbh, sizes->fb_width, sizes->fb_height);
107
107
108
-
DRM_DEBUG_KMS("allocated %dx%d %dbpp fb: 0x%08x\n",
109
-
dfb->fb.width, dfb->fb.height,
110
-
dfb->fb.bits_per_pixel, obj->phys_addr);
108
+
DRM_DEBUG_KMS("allocated %dx%d %dbpp fb: 0x%08llx\n",
109
+
dfb->fb.width, dfb->fb.height, dfb->fb.bits_per_pixel,
110
+
(unsigned long long)obj->phys_addr);
111
111
112
112
return 0;
113
113
···
177
177
return ret;
178
178
}
179
179
180
+
void armada_fbdev_lastclose(struct drm_device *dev)
181
+
{
182
+
struct armada_private *priv = dev->dev_private;
183
+
184
+
drm_modeset_lock_all(dev);
185
+
if (priv->fbdev)
186
+
drm_fb_helper_restore_fbdev_mode(priv->fbdev);
187
+
drm_modeset_unlock_all(dev);
188
+
}
189
+
180
190
void armada_fbdev_fini(struct drm_device *dev)
181
191
{
182
192
struct armada_private *priv = dev->dev_private;
···
202
192
framebuffer_release(info);
203
193
}
204
194
195
+
drm_fb_helper_fini(fbh);
196
+
205
197
if (fbh->fb)
206
198
fbh->fb->funcs->destroy(fbh->fb);
207
-
208
-
drm_fb_helper_fini(fbh);
209
199
210
200
priv->fbdev = NULL;
211
201
}
+4
-3
drivers/gpu/drm/armada/armada_gem.c
+4
-3
drivers/gpu/drm/armada/armada_gem.c
···
172
172
obj->dev_addr = obj->linear->start;
173
173
}
174
174
175
-
DRM_DEBUG_DRIVER("obj %p phys %#x dev %#x\n",
176
-
obj, obj->phys_addr, obj->dev_addr);
175
+
DRM_DEBUG_DRIVER("obj %p phys %#llx dev %#llx\n", obj,
176
+
(unsigned long long)obj->phys_addr,
177
+
(unsigned long long)obj->dev_addr);
177
178
178
179
return 0;
179
180
}
···
558
557
* refcount on the gem object itself.
559
558
*/
560
559
drm_gem_object_reference(obj);
561
-
dma_buf_put(buf);
562
560
return obj;
563
561
}
564
562
}
···
573
573
}
574
574
575
575
dobj->obj.import_attach = attach;
576
+
get_dma_buf(buf);
576
577
577
578
/*
578
579
* Don't call dma_buf_map_attachment() here - it maps the
+8
drivers/gpu/drm/drm_edid.c
+8
drivers/gpu/drm/drm_edid.c
···
68
68
#define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
69
69
/* Force reduced-blanking timings for detailed modes */
70
70
#define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
71
+
/* Force 8bpc */
72
+
#define EDID_QUIRK_FORCE_8BPC (1 << 8)
71
73
72
74
struct detailed_mode_closure {
73
75
struct drm_connector *connector;
···
130
128
131
129
/* Medion MD 30217 PG */
132
130
{ "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
131
+
132
+
/* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
133
+
{ "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
133
134
};
134
135
135
136
/*
···
3439
3434
edid_fixup_preferred(connector, quirks);
3440
3435
3441
3436
drm_add_display_info(edid, &connector->display_info);
3437
+
3438
+
if (quirks & EDID_QUIRK_FORCE_8BPC)
3439
+
connector->display_info.bpc = 8;
3442
3440
3443
3441
return num_modes;
3444
3442
}
+3
-3
drivers/gpu/drm/drm_stub.c
+3
-3
drivers/gpu/drm/drm_stub.c
···
566
566
if (dev->driver->unload)
567
567
dev->driver->unload(dev);
568
568
err_primary_node:
569
-
drm_put_minor(dev->primary);
569
+
drm_unplug_minor(dev->primary);
570
570
err_render_node:
571
-
drm_put_minor(dev->render);
571
+
drm_unplug_minor(dev->render);
572
572
err_control_node:
573
-
drm_put_minor(dev->control);
573
+
drm_unplug_minor(dev->control);
574
574
err_agp:
575
575
if (dev->driver->bus->agp_destroy)
576
576
dev->driver->bus->agp_destroy(dev);
+11
-9
drivers/gpu/drm/i915/i915_dma.c
+11
-9
drivers/gpu/drm/i915/i915_dma.c
···
83
83
drm_i915_private_t *dev_priv = dev->dev_private;
84
84
struct drm_i915_master_private *master_priv;
85
85
86
+
/*
87
+
* The dri breadcrumb update races against the drm master disappearing.
88
+
* Instead of trying to fix this (this is by far not the only ums issue)
89
+
* just don't do the update in kms mode.
90
+
*/
91
+
if (drm_core_check_feature(dev, DRIVER_MODESET))
92
+
return;
93
+
86
94
if (dev->primary->master) {
87
95
master_priv = dev->primary->master->driver_priv;
88
96
if (master_priv->sarea_priv)
···
1498
1490
spin_lock_init(&dev_priv->uncore.lock);
1499
1491
spin_lock_init(&dev_priv->mm.object_stat_lock);
1500
1492
mutex_init(&dev_priv->dpio_lock);
1501
-
mutex_init(&dev_priv->rps.hw_lock);
1502
1493
mutex_init(&dev_priv->modeset_restore_lock);
1503
1494
1504
-
mutex_init(&dev_priv->pc8.lock);
1505
-
dev_priv->pc8.requirements_met = false;
1506
-
dev_priv->pc8.gpu_idle = false;
1507
-
dev_priv->pc8.irqs_disabled = false;
1508
-
dev_priv->pc8.enabled = false;
1509
-
dev_priv->pc8.disable_count = 2; /* requirements_met + gpu_idle */
1510
-
INIT_DELAYED_WORK(&dev_priv->pc8.enable_work, hsw_enable_pc8_work);
1495
+
intel_pm_setup(dev);
1511
1496
1512
1497
intel_display_crc_init(dev);
1513
1498
···
1604
1603
}
1605
1604
1606
1605
intel_irq_init(dev);
1607
-
intel_pm_init(dev);
1608
1606
intel_uncore_sanitize(dev);
1609
1607
1610
1608
/* Try to make sure MCHBAR is enabled before poking at it */
···
1848
1848
1849
1849
void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1850
1850
{
1851
+
mutex_lock(&dev->struct_mutex);
1851
1852
i915_gem_context_close(dev, file_priv);
1852
1853
i915_gem_release(dev, file_priv);
1854
+
mutex_unlock(&dev->struct_mutex);
1853
1855
}
1854
1856
1855
1857
void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
+1
drivers/gpu/drm/i915/i915_drv.c
+1
drivers/gpu/drm/i915/i915_drv.c
+6
-3
drivers/gpu/drm/i915/i915_drv.h
+6
-3
drivers/gpu/drm/i915/i915_drv.h
···
1755
1755
#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1756
1756
#define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
1757
1757
((dev)->pdev->device & 0xFF00) == 0x0C00)
1758
-
#define IS_ULT(dev) (IS_HASWELL(dev) && \
1758
+
#define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
1759
+
(((dev)->pdev->device & 0xf) == 0x2 || \
1760
+
((dev)->pdev->device & 0xf) == 0x6 || \
1761
+
((dev)->pdev->device & 0xf) == 0xe))
1762
+
#define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
1759
1763
((dev)->pdev->device & 0xFF00) == 0x0A00)
1764
+
#define IS_ULT(dev) (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
1760
1765
#define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
1761
1766
((dev)->pdev->device & 0x00F0) == 0x0020)
1762
1767
#define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
···
1906
1901
void i915_handle_error(struct drm_device *dev, bool wedged);
1907
1902
1908
1903
extern void intel_irq_init(struct drm_device *dev);
1909
-
extern void intel_pm_init(struct drm_device *dev);
1910
1904
extern void intel_hpd_init(struct drm_device *dev);
1911
-
extern void intel_pm_init(struct drm_device *dev);
1912
1905
1913
1906
extern void intel_uncore_sanitize(struct drm_device *dev);
1914
1907
extern void intel_uncore_early_sanitize(struct drm_device *dev);
+12
-4
drivers/gpu/drm/i915/i915_gem_context.c
+12
-4
drivers/gpu/drm/i915/i915_gem_context.c
···
347
347
{
348
348
struct drm_i915_file_private *file_priv = file->driver_priv;
349
349
350
-
mutex_lock(&dev->struct_mutex);
351
350
idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL);
352
351
idr_destroy(&file_priv->context_idr);
353
-
mutex_unlock(&dev->struct_mutex);
354
352
}
355
353
356
354
static struct i915_hw_context *
···
421
423
if (ret)
422
424
return ret;
423
425
424
-
/* Clear this page out of any CPU caches for coherent swap-in/out. Note
426
+
/*
427
+
* Pin can switch back to the default context if we end up calling into
428
+
* evict_everything - as a last ditch gtt defrag effort that also
429
+
* switches to the default context. Hence we need to reload from here.
430
+
*/
431
+
from = ring->last_context;
432
+
433
+
/*
434
+
* Clear this page out of any CPU caches for coherent swap-in/out. Note
425
435
* that thanks to write = false in this call and us not setting any gpu
426
436
* write domains when putting a context object onto the active list
427
437
* (when switching away from it), this won't block.
428
-
* XXX: We need a real interface to do this instead of trickery. */
438
+
*
439
+
* XXX: We need a real interface to do this instead of trickery.
440
+
*/
429
441
ret = i915_gem_object_set_to_gtt_domain(to->obj, false);
430
442
if (ret) {
431
443
i915_gem_object_unpin(to->obj);
+11
-3
drivers/gpu/drm/i915/i915_gem_evict.c
+11
-3
drivers/gpu/drm/i915/i915_gem_evict.c
···
88
88
} else
89
89
drm_mm_init_scan(&vm->mm, min_size, alignment, cache_level);
90
90
91
+
search_again:
91
92
/* First see if there is a large enough contiguous idle region... */
92
93
list_for_each_entry(vma, &vm->inactive_list, mm_list) {
93
94
if (mark_free(vma, &unwind_list))
···
116
115
list_del_init(&vma->exec_list);
117
116
}
118
117
119
-
/* We expect the caller to unpin, evict all and try again, or give up.
120
-
* So calling i915_gem_evict_vm() is unnecessary.
118
+
/* Can we unpin some objects such as idle hw contents,
119
+
* or pending flips?
121
120
*/
122
-
return -ENOSPC;
121
+
ret = nonblocking ? -ENOSPC : i915_gpu_idle(dev);
122
+
if (ret)
123
+
return ret;
124
+
125
+
/* Only idle the GPU and repeat the search once */
126
+
i915_gem_retire_requests(dev);
127
+
nonblocking = true;
128
+
goto search_again;
123
129
124
130
found:
125
131
/* drm_mm doesn't allow any other other operations while
+7
-2
drivers/gpu/drm/i915/i915_gem_gtt.c
+7
-2
drivers/gpu/drm/i915/i915_gem_gtt.c
···
337
337
kfree(ppgtt->gen8_pt_dma_addr[i]);
338
338
}
339
339
340
-
__free_pages(ppgtt->gen8_pt_pages, ppgtt->num_pt_pages << PAGE_SHIFT);
341
-
__free_pages(ppgtt->pd_pages, ppgtt->num_pd_pages << PAGE_SHIFT);
340
+
__free_pages(ppgtt->gen8_pt_pages, get_order(ppgtt->num_pt_pages << PAGE_SHIFT));
341
+
__free_pages(ppgtt->pd_pages, get_order(ppgtt->num_pd_pages << PAGE_SHIFT));
342
342
}
343
343
344
344
/**
···
1241
1241
bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
1242
1242
if (bdw_gmch_ctl)
1243
1243
bdw_gmch_ctl = 1 << bdw_gmch_ctl;
1244
+
if (bdw_gmch_ctl > 4) {
1245
+
WARN_ON(!i915_preliminary_hw_support);
1246
+
return 4<<20;
1247
+
}
1248
+
1244
1249
return bdw_gmch_ctl << 20;
1245
1250
}
1246
1251
+4
-3
drivers/gpu/drm/i915/intel_display.c
+4
-3
drivers/gpu/drm/i915/intel_display.c
···
9135
9135
if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
9136
9136
PIPE_CONF_CHECK_I(pipe_bpp);
9137
9137
9138
-
if (!IS_HASWELL(dev)) {
9138
+
if (!HAS_DDI(dev)) {
9139
9139
PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
9140
9140
PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
9141
9141
}
···
11036
11036
}
11037
11037
11038
11038
intel_modeset_check_state(dev);
11039
-
11040
-
drm_mode_config_reset(dev);
11041
11039
}
11042
11040
11043
11041
void intel_modeset_gem_init(struct drm_device *dev)
···
11044
11046
11045
11047
intel_setup_overlay(dev);
11046
11048
11049
+
drm_modeset_lock_all(dev);
11050
+
drm_mode_config_reset(dev);
11047
11051
intel_modeset_setup_hw_state(dev, false);
11052
+
drm_modeset_unlock_all(dev);
11048
11053
}
11049
11054
11050
11055
void intel_modeset_cleanup(struct drm_device *dev)
+1
drivers/gpu/drm/i915/intel_drv.h
+1
drivers/gpu/drm/i915/intel_drv.h
···
821
821
uint32_t sprite_width, int pixel_size,
822
822
bool enabled, bool scaled);
823
823
void intel_init_pm(struct drm_device *dev);
824
+
void intel_pm_setup(struct drm_device *dev);
824
825
bool intel_fbc_enabled(struct drm_device *dev);
825
826
void intel_update_fbc(struct drm_device *dev);
826
827
void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
+23
-3
drivers/gpu/drm/i915/intel_panel.c
+23
-3
drivers/gpu/drm/i915/intel_panel.c
···
451
451
452
452
spin_lock_irqsave(&dev_priv->backlight.lock, flags);
453
453
454
-
if (HAS_PCH_SPLIT(dev)) {
454
+
if (IS_BROADWELL(dev)) {
455
+
val = I915_READ(BLC_PWM_PCH_CTL2) & BACKLIGHT_DUTY_CYCLE_MASK;
456
+
} else if (HAS_PCH_SPLIT(dev)) {
455
457
val = I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
456
458
} else {
457
459
if (IS_VALLEYVIEW(dev))
···
481
479
return val;
482
480
}
483
481
482
+
static void intel_bdw_panel_set_backlight(struct drm_device *dev, u32 level)
483
+
{
484
+
struct drm_i915_private *dev_priv = dev->dev_private;
485
+
u32 val = I915_READ(BLC_PWM_PCH_CTL2) & ~BACKLIGHT_DUTY_CYCLE_MASK;
486
+
I915_WRITE(BLC_PWM_PCH_CTL2, val | level);
487
+
}
488
+
484
489
static void intel_pch_panel_set_backlight(struct drm_device *dev, u32 level)
485
490
{
486
491
struct drm_i915_private *dev_priv = dev->dev_private;
···
505
496
DRM_DEBUG_DRIVER("set backlight PWM = %d\n", level);
506
497
level = intel_panel_compute_brightness(dev, pipe, level);
507
498
508
-
if (HAS_PCH_SPLIT(dev))
499
+
if (IS_BROADWELL(dev))
500
+
return intel_bdw_panel_set_backlight(dev, level);
501
+
else if (HAS_PCH_SPLIT(dev))
509
502
return intel_pch_panel_set_backlight(dev, level);
510
503
511
504
if (is_backlight_combination_mode(dev)) {
···
677
666
POSTING_READ(reg);
678
667
I915_WRITE(reg, tmp | BLM_PWM_ENABLE);
679
668
680
-
if (HAS_PCH_SPLIT(dev) &&
669
+
if (IS_BROADWELL(dev)) {
670
+
/*
671
+
* Broadwell requires PCH override to drive the PCH
672
+
* backlight pin. The above will configure the CPU
673
+
* backlight pin, which we don't plan to use.
674
+
*/
675
+
tmp = I915_READ(BLC_PWM_PCH_CTL1);
676
+
tmp |= BLM_PCH_OVERRIDE_ENABLE | BLM_PCH_PWM_ENABLE;
677
+
I915_WRITE(BLC_PWM_PCH_CTL1, tmp);
678
+
} else if (HAS_PCH_SPLIT(dev) &&
681
679
!(dev_priv->quirks & QUIRK_NO_PCH_PWM_ENABLE)) {
682
680
tmp = I915_READ(BLC_PWM_PCH_CTL1);
683
681
tmp |= BLM_PCH_PWM_ENABLE;
+27
-2
drivers/gpu/drm/i915/intel_pm.c
+27
-2
drivers/gpu/drm/i915/intel_pm.c
···
5685
5685
{
5686
5686
struct drm_i915_private *dev_priv = dev->dev_private;
5687
5687
bool is_enabled, enable_requested;
5688
+
unsigned long irqflags;
5688
5689
uint32_t tmp;
5689
5690
5690
5691
tmp = I915_READ(HSW_PWR_WELL_DRIVER);
···
5703
5702
HSW_PWR_WELL_STATE_ENABLED), 20))
5704
5703
DRM_ERROR("Timeout enabling power well\n");
5705
5704
}
5705
+
5706
+
if (IS_BROADWELL(dev)) {
5707
+
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
5708
+
I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_B),
5709
+
dev_priv->de_irq_mask[PIPE_B]);
5710
+
I915_WRITE(GEN8_DE_PIPE_IER(PIPE_B),
5711
+
~dev_priv->de_irq_mask[PIPE_B] |
5712
+
GEN8_PIPE_VBLANK);
5713
+
I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_C),
5714
+
dev_priv->de_irq_mask[PIPE_C]);
5715
+
I915_WRITE(GEN8_DE_PIPE_IER(PIPE_C),
5716
+
~dev_priv->de_irq_mask[PIPE_C] |
5717
+
GEN8_PIPE_VBLANK);
5718
+
POSTING_READ(GEN8_DE_PIPE_IER(PIPE_C));
5719
+
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
5720
+
}
5706
5721
} else {
5707
5722
if (enable_requested) {
5708
-
unsigned long irqflags;
5709
5723
enum pipe p;
5710
5724
5711
5725
I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
···
6146
6130
return val;
6147
6131
}
6148
6132
6149
-
void intel_pm_init(struct drm_device *dev)
6133
+
void intel_pm_setup(struct drm_device *dev)
6150
6134
{
6151
6135
struct drm_i915_private *dev_priv = dev->dev_private;
6152
6136
6137
+
mutex_init(&dev_priv->rps.hw_lock);
6138
+
6139
+
mutex_init(&dev_priv->pc8.lock);
6140
+
dev_priv->pc8.requirements_met = false;
6141
+
dev_priv->pc8.gpu_idle = false;
6142
+
dev_priv->pc8.irqs_disabled = false;
6143
+
dev_priv->pc8.enabled = false;
6144
+
dev_priv->pc8.disable_count = 2; /* requirements_met + gpu_idle */
6145
+
INIT_DELAYED_WORK(&dev_priv->pc8.enable_work, hsw_enable_pc8_work);
6153
6146
INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
6154
6147
intel_gen6_powersave_work);
6155
6148
}
+1
drivers/gpu/drm/i915/intel_ringbuffer.c
+1
drivers/gpu/drm/i915/intel_ringbuffer.c
+1
drivers/gpu/drm/i915/intel_uncore.c
+1
drivers/gpu/drm/i915/intel_uncore.c
+6
drivers/gpu/drm/nouveau/nouveau_drm.c
+6
drivers/gpu/drm/nouveau/nouveau_drm.c
···
858
858
if (nouveau_runtime_pm == 0)
859
859
return -EINVAL;
860
860
861
+
/* are we optimus enabled? */
862
+
if (nouveau_runtime_pm == -1 && !nouveau_is_optimus() && !nouveau_is_v1_dsm()) {
863
+
DRM_DEBUG_DRIVER("failing to power off - not optimus\n");
864
+
return -EINVAL;
865
+
}
866
+
861
867
nv_debug_level(SILENT);
862
868
drm_kms_helper_poll_disable(drm_dev);
863
869
vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF);
+3
-1
drivers/gpu/drm/radeon/atombios_crtc.c
+3
-1
drivers/gpu/drm/radeon/atombios_crtc.c
···
1196
1196
} else if ((rdev->family == CHIP_TAHITI) ||
1197
1197
(rdev->family == CHIP_PITCAIRN))
1198
1198
fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16);
1199
-
else if (rdev->family == CHIP_VERDE)
1199
+
else if ((rdev->family == CHIP_VERDE) ||
1200
+
(rdev->family == CHIP_OLAND) ||
1201
+
(rdev->family == CHIP_HAINAN)) /* for completeness. HAINAN has no display hw */
1200
1202
fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16);
1201
1203
1202
1204
switch (radeon_crtc->crtc_id) {
+1
-1
drivers/gpu/drm/radeon/cik_sdma.c
+1
-1
drivers/gpu/drm/radeon/cik_sdma.c
···
458
458
radeon_ring_write(ring, 0); /* src/dst endian swap */
459
459
radeon_ring_write(ring, src_offset & 0xffffffff);
460
460
radeon_ring_write(ring, upper_32_bits(src_offset) & 0xffffffff);
461
-
radeon_ring_write(ring, dst_offset & 0xfffffffc);
461
+
radeon_ring_write(ring, dst_offset & 0xffffffff);
462
462
radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xffffffff);
463
463
src_offset += cur_size_in_bytes;
464
464
dst_offset += cur_size_in_bytes;
+2
-2
drivers/gpu/drm/radeon/radeon_asic.c
+2
-2
drivers/gpu/drm/radeon/radeon_asic.c
···
2021
2021
.hdmi_setmode = &evergreen_hdmi_setmode,
2022
2022
},
2023
2023
.copy = {
2024
-
.blit = NULL,
2024
+
.blit = &cik_copy_cpdma,
2025
2025
.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2026
2026
.dma = &cik_copy_dma,
2027
2027
.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
···
2122
2122
.hdmi_setmode = &evergreen_hdmi_setmode,
2123
2123
},
2124
2124
.copy = {
2125
-
.blit = NULL,
2125
+
.blit = &cik_copy_cpdma,
2126
2126
.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2127
2127
.dma = &cik_copy_dma,
2128
2128
.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
-10
drivers/gpu/drm/radeon/radeon_drv.c
-10
drivers/gpu/drm/radeon/radeon_drv.c
···
508
508
#endif
509
509
};
510
510
511
-
512
-
static void
513
-
radeon_pci_shutdown(struct pci_dev *pdev)
514
-
{
515
-
struct drm_device *dev = pci_get_drvdata(pdev);
516
-
517
-
radeon_driver_unload_kms(dev);
518
-
}
519
-
520
511
static struct drm_driver kms_driver = {
521
512
.driver_features =
522
513
DRIVER_USE_AGP |
···
577
586
.probe = radeon_pci_probe,
578
587
.remove = radeon_pci_remove,
579
588
.driver.pm = &radeon_pm_ops,
580
-
.shutdown = radeon_pci_shutdown,
581
589
};
582
590
583
591
static int __init radeon_init(void)
+10
drivers/gpu/drm/radeon/rs690.c
+10
drivers/gpu/drm/radeon/rs690.c
···
162
162
base = RREG32_MC(R_000100_MCCFG_FB_LOCATION);
163
163
base = G_000100_MC_FB_START(base) << 16;
164
164
rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
165
+
/* Some boards seem to be configured for 128MB of sideport memory,
166
+
* but really only have 64MB. Just skip the sideport and use
167
+
* UMA memory.
168
+
*/
169
+
if (rdev->mc.igp_sideport_enabled &&
170
+
(rdev->mc.real_vram_size == (384 * 1024 * 1024))) {
171
+
base += 128 * 1024 * 1024;
172
+
rdev->mc.real_vram_size -= 128 * 1024 * 1024;
173
+
rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
174
+
}
165
175
166
176
/* Use K8 direct mapping for fast fb access. */
167
177
rdev->fastfb_working = false;
+3
-3
drivers/gpu/drm/ttm/ttm_bo_vm.c
+3
-3
drivers/gpu/drm/ttm/ttm_bo_vm.c
···
169
169
}
170
170
171
171
page_offset = ((address - vma->vm_start) >> PAGE_SHIFT) +
172
-
drm_vma_node_start(&bo->vma_node) - vma->vm_pgoff;
173
-
page_last = vma_pages(vma) +
174
-
drm_vma_node_start(&bo->vma_node) - vma->vm_pgoff;
172
+
vma->vm_pgoff - drm_vma_node_start(&bo->vma_node);
173
+
page_last = vma_pages(vma) + vma->vm_pgoff -
174
+
drm_vma_node_start(&bo->vma_node);
175
175
176
176
if (unlikely(page_offset >= bo->num_pages)) {
177
177
retval = VM_FAULT_SIGBUS;
+3
drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c
+3
drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c