Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
interconnect: qcom: sdm845: Retire DEFINE_QBCM
The struct definition macros are hard to read and compare, expand them.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Link: https://lore.kernel.org/r/20230811-topic-icc_retire_macrosd-v1-13-c03aaeffc769@linaro.org
Signed-off-by: Georgi Djakov <djakov@kernel.org>
authored by
Konrad Dybcio
and committed by
Georgi Djakov
35f490c5
46cd2018
+249
-28
+249
-28
drivers/interconnect/qcom/sdm845.c
+249
-28
drivers/interconnect/qcom/sdm845.c
···
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.buswidth = 8,
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};
1265
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1266
-
DEFINE_QBCM(bcm_acv, "ACV", false, &ebi);
1267
-
DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
1268
-
DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
1269
-
DEFINE_QBCM(bcm_mm0, "MM0", false, &qns_mem_noc_hf);
1270
-
DEFINE_QBCM(bcm_sh1, "SH1", false, &qns_apps_io);
1271
-
DEFINE_QBCM(bcm_mm1, "MM1", true, &qxm_camnoc_hf0_uncomp, &qxm_camnoc_hf1_uncomp, &qxm_camnoc_sf_uncomp, &qxm_camnoc_hf0, &qxm_camnoc_hf1, &qxm_mdp0, &qxm_mdp1);
1272
-
DEFINE_QBCM(bcm_sh2, "SH2", false, &qns_memnoc_snoc);
1273
-
DEFINE_QBCM(bcm_mm2, "MM2", false, &qns2_mem_noc);
1274
-
DEFINE_QBCM(bcm_sh3, "SH3", false, &acm_tcu);
1275
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DEFINE_QBCM(bcm_mm3, "MM3", false, &qxm_camnoc_sf, &qxm_rot, &qxm_venus0, &qxm_venus1, &qxm_venus_arm9);
1276
-
DEFINE_QBCM(bcm_sh5, "SH5", false, &qnm_apps);
1277
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DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_memnoc_sf);
1278
-
DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
1279
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DEFINE_QBCM(bcm_cn0, "CN0", false, &qhm_spdm, &qhm_tic, &qnm_snoc, &xm_qdss_dap, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_aop, &qhs_aoss, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_compute_dsp_cfg, &qhs_cpr_cx, &qhs_crypto0_cfg, &qhs_dcc_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_glm, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mnoc_cfg, &qhs_pcie0_cfg, &qhs_pcie_gen3_cfg, &qhs_pdm, &qhs_phy_refgen_south, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qupv3_north, &qhs_qupv3_south, &qhs_sdc2, &qhs_sdc4, &qhs_snoc_cfg, &qhs_spdm, &qhs_spss_cfg, &qhs_tcsr, &qhs_tlmm_north, &qhs_tlmm_south, &qhs_tsif, &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_usb3_1, &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, &qns_cnoc_a2noc, &srvc_cnoc);
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-
DEFINE_QBCM(bcm_qup0, "QUP0", false, &qhm_qup1, &qhm_qup2);
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DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem);
1282
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DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_memnoc_gc);
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DEFINE_QBCM(bcm_sn3, "SN3", false, &qns_cnoc);
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DEFINE_QBCM(bcm_sn4, "SN4", false, &qxm_pimem);
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DEFINE_QBCM(bcm_sn5, "SN5", false, &xs_qdss_stm);
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-
DEFINE_QBCM(bcm_sn6, "SN6", false, &qhs_apss, &srvc_snoc, &xs_sys_tcu_cfg);
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-
DEFINE_QBCM(bcm_sn7, "SN7", false, &qxs_pcie);
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DEFINE_QBCM(bcm_sn8, "SN8", false, &qxs_pcie_gen3);
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-
DEFINE_QBCM(bcm_sn9, "SN9", false, &srvc_aggre1_noc, &qnm_aggre1_noc);
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-
DEFINE_QBCM(bcm_sn11, "SN11", false, &srvc_aggre2_noc, &qnm_aggre2_noc);
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DEFINE_QBCM(bcm_sn12, "SN12", false, &qnm_gladiator_sodv, &xm_gic);
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DEFINE_QBCM(bcm_sn14, "SN14", false, &qnm_pcie_anoc);
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-
DEFINE_QBCM(bcm_sn15, "SN15", false, &qnm_memnoc);
1266
+
static struct qcom_icc_bcm bcm_acv = {
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+
.name = "ACV",
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+
.keepalive = false,
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+
.num_nodes = 1,
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+
.nodes = { &ebi },
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+
};
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+
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+
static struct qcom_icc_bcm bcm_mc0 = {
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+
.name = "MC0",
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+
.keepalive = true,
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+
.num_nodes = 1,
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+
.nodes = { &ebi },
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+
};
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+
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+
static struct qcom_icc_bcm bcm_sh0 = {
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+
.name = "SH0",
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+
.keepalive = true,
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+
.num_nodes = 1,
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+
.nodes = { &qns_llcc },
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+
};
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+
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+
static struct qcom_icc_bcm bcm_mm0 = {
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+
.name = "MM0",
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+
.keepalive = false,
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+
.num_nodes = 1,
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+
.nodes = { &qns_mem_noc_hf },
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+
};
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+
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static struct qcom_icc_bcm bcm_sh1 = {
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+
.name = "SH1",
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+
.keepalive = false,
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+
.num_nodes = 1,
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+
.nodes = { &qns_apps_io },
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+
};
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+
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+
static struct qcom_icc_bcm bcm_mm1 = {
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+
.name = "MM1",
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+
.keepalive = true,
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+
.num_nodes = 7,
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+
.nodes = { &qxm_camnoc_hf0_uncomp,
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&qxm_camnoc_hf1_uncomp,
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+
&qxm_camnoc_sf_uncomp,
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+
&qxm_camnoc_hf0,
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+
&qxm_camnoc_hf1,
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+
&qxm_mdp0,
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+
&qxm_mdp1
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+
},
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+
};
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+
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static struct qcom_icc_bcm bcm_sh2 = {
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.name = "SH2",
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+
.keepalive = false,
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+
.num_nodes = 1,
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.nodes = { &qns_memnoc_snoc },
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};
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+
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static struct qcom_icc_bcm bcm_mm2 = {
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.name = "MM2",
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.keepalive = false,
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+
.num_nodes = 1,
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.nodes = { &qns2_mem_noc },
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+
};
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+
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static struct qcom_icc_bcm bcm_sh3 = {
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.name = "SH3",
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.keepalive = false,
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+
.num_nodes = 1,
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.nodes = { &acm_tcu },
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+
};
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+
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static struct qcom_icc_bcm bcm_mm3 = {
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.name = "MM3",
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.keepalive = false,
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.num_nodes = 5,
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.nodes = { &qxm_camnoc_sf, &qxm_rot, &qxm_venus0, &qxm_venus1, &qxm_venus_arm9 },
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};
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+
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static struct qcom_icc_bcm bcm_sh5 = {
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.name = "SH5",
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.keepalive = false,
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.num_nodes = 1,
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.nodes = { &qnm_apps },
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};
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static struct qcom_icc_bcm bcm_sn0 = {
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.name = "SN0",
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.keepalive = true,
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.num_nodes = 1,
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.nodes = { &qns_memnoc_sf },
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};
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+
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static struct qcom_icc_bcm bcm_ce0 = {
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.name = "CE0",
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.keepalive = false,
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+
.num_nodes = 1,
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.nodes = { &qxm_crypto },
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+
};
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+
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static struct qcom_icc_bcm bcm_cn0 = {
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.name = "CN0",
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.keepalive = false,
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.num_nodes = 47,
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.nodes = { &qhm_spdm,
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&qhm_tic,
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&qnm_snoc,
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&xm_qdss_dap,
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&qhs_a1_noc_cfg,
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&qhs_a2_noc_cfg,
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&qhs_aop,
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&qhs_aoss,
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&qhs_camera_cfg,
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&qhs_clk_ctl,
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&qhs_compute_dsp_cfg,
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&qhs_cpr_cx,
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&qhs_crypto0_cfg,
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&qhs_dcc_cfg,
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&qhs_ddrss_cfg,
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&qhs_display_cfg,
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&qhs_glm,
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&qhs_gpuss_cfg,
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&qhs_imem_cfg,
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&qhs_ipa,
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&qhs_mnoc_cfg,
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&qhs_pcie0_cfg,
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&qhs_pcie_gen3_cfg,
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&qhs_pdm,
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&qhs_phy_refgen_south,
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&qhs_pimem_cfg,
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&qhs_prng,
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&qhs_qdss_cfg,
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&qhs_qupv3_north,
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&qhs_qupv3_south,
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&qhs_sdc2,
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&qhs_sdc4,
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&qhs_snoc_cfg,
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&qhs_spdm,
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&qhs_spss_cfg,
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&qhs_tcsr,
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&qhs_tlmm_north,
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&qhs_tlmm_south,
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&qhs_tsif,
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&qhs_ufs_card_cfg,
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&qhs_ufs_mem_cfg,
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&qhs_usb3_0,
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&qhs_usb3_1,
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&qhs_venus_cfg,
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&qhs_vsense_ctrl_cfg,
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&qns_cnoc_a2noc,
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&srvc_cnoc
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},
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};
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+
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static struct qcom_icc_bcm bcm_qup0 = {
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.name = "QUP0",
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.keepalive = false,
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+
.num_nodes = 2,
1422
+
.nodes = { &qhm_qup1, &qhm_qup2 },
1423
+
};
1424
+
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static struct qcom_icc_bcm bcm_sn1 = {
1426
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.name = "SN1",
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.keepalive = false,
1428
+
.num_nodes = 1,
1429
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.nodes = { &qxs_imem },
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+
};
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+
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static struct qcom_icc_bcm bcm_sn2 = {
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.name = "SN2",
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.keepalive = false,
1435
+
.num_nodes = 1,
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.nodes = { &qns_memnoc_gc },
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+
};
1438
+
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static struct qcom_icc_bcm bcm_sn3 = {
1440
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.name = "SN3",
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+
.keepalive = false,
1442
+
.num_nodes = 1,
1443
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.nodes = { &qns_cnoc },
1444
+
};
1445
+
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static struct qcom_icc_bcm bcm_sn4 = {
1447
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.name = "SN4",
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.keepalive = false,
1449
+
.num_nodes = 1,
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.nodes = { &qxm_pimem },
1451
+
};
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+
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static struct qcom_icc_bcm bcm_sn5 = {
1454
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.name = "SN5",
1455
+
.keepalive = false,
1456
+
.num_nodes = 1,
1457
+
.nodes = { &xs_qdss_stm },
1458
+
};
1459
+
1460
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static struct qcom_icc_bcm bcm_sn6 = {
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.name = "SN6",
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+
.keepalive = false,
1463
+
.num_nodes = 3,
1464
+
.nodes = { &qhs_apss, &srvc_snoc, &xs_sys_tcu_cfg },
1465
+
};
1466
+
1467
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static struct qcom_icc_bcm bcm_sn7 = {
1468
+
.name = "SN7",
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+
.keepalive = false,
1470
+
.num_nodes = 1,
1471
+
.nodes = { &qxs_pcie },
1472
+
};
1473
+
1474
+
static struct qcom_icc_bcm bcm_sn8 = {
1475
+
.name = "SN8",
1476
+
.keepalive = false,
1477
+
.num_nodes = 1,
1478
+
.nodes = { &qxs_pcie_gen3 },
1479
+
};
1480
+
1481
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static struct qcom_icc_bcm bcm_sn9 = {
1482
+
.name = "SN9",
1483
+
.keepalive = false,
1484
+
.num_nodes = 2,
1485
+
.nodes = { &srvc_aggre1_noc, &qnm_aggre1_noc },
1486
+
};
1487
+
1488
+
static struct qcom_icc_bcm bcm_sn11 = {
1489
+
.name = "SN11",
1490
+
.keepalive = false,
1491
+
.num_nodes = 2,
1492
+
.nodes = { &srvc_aggre2_noc, &qnm_aggre2_noc },
1493
+
};
1494
+
1495
+
static struct qcom_icc_bcm bcm_sn12 = {
1496
+
.name = "SN12",
1497
+
.keepalive = false,
1498
+
.num_nodes = 2,
1499
+
.nodes = { &qnm_gladiator_sodv, &xm_gic },
1500
+
};
1501
+
1502
+
static struct qcom_icc_bcm bcm_sn14 = {
1503
+
.name = "SN14",
1504
+
.keepalive = false,
1505
+
.num_nodes = 1,
1506
+
.nodes = { &qnm_pcie_anoc },
1507
+
};
1508
+
1509
+
static struct qcom_icc_bcm bcm_sn15 = {
1510
+
.name = "SN15",
1511
+
.keepalive = false,
1512
+
.num_nodes = 1,
1513
+
.nodes = { &qnm_memnoc },
1514
+
};
1294
1515
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1516
static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
1296
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&bcm_sn9,