tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
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pinctrl: qcom: add the tlmm driver for Kaanapali platforms

Add support for Kaanapali TLMM configuration and control via the pinctrl
framework.

Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

authored by

Jingyi Wang and committed by
Linus Walleij 35ff9c6b e7db6f15

+1812
+8
drivers/pinctrl/qcom/Kconfig.msm
··· 92 92 Qualcomm Technologies Inc. IPQ9574 platform. Select this for 93 93 IPQ9574. 94 94 95 + config PINCTRL_KAANAPALI 96 + tristate "Qualcomm Technologies Inc Kaanapali pin controller driver" 97 + depends on ARM64 || COMPILE_TEST 98 + help 99 + This is the pinctrl, pinmux, pinconf and gpiolib driver for the 100 + Qualcomm Technologies Inc TLMM block found on the Qualcomm 101 + Technologies Inc Kaanapali platform. 102 + 95 103 config PINCTRL_MSM8226 96 104 tristate "Qualcomm 8226 pin controller driver" 97 105 depends on ARM || COMPILE_TEST
+1
drivers/pinctrl/qcom/Makefile
··· 12 12 obj-$(CONFIG_PINCTRL_IPQ8074) += pinctrl-ipq8074.o 13 13 obj-$(CONFIG_PINCTRL_IPQ6018) += pinctrl-ipq6018.o 14 14 obj-$(CONFIG_PINCTRL_IPQ9574) += pinctrl-ipq9574.o 15 + obj-$(CONFIG_PINCTRL_KAANAPALI) += pinctrl-kaanapali.o 15 16 obj-$(CONFIG_PINCTRL_MSM8226) += pinctrl-msm8226.o 16 17 obj-$(CONFIG_PINCTRL_MSM8660) += pinctrl-msm8660.o 17 18 obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o
+1803
drivers/pinctrl/qcom/pinctrl-kaanapali.c
··· 1 + // SPDX-License-Identifier: GPL-2.0-only 2 + /* 3 + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 + */ 5 + 6 + #include <linux/module.h> 7 + #include <linux/of.h> 8 + #include <linux/platform_device.h> 9 + 10 + #include "pinctrl-msm.h" 11 + 12 + #define REG_SIZE 0x1000 13 + #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \ 14 + { \ 15 + .grp = PINCTRL_PINGROUP("gpio" #id, \ 16 + gpio##id##_pins, \ 17 + ARRAY_SIZE(gpio##id##_pins)), \ 18 + .funcs = (int[]){ \ 19 + msm_mux_gpio, /* gpio mode */ \ 20 + msm_mux_##f1, \ 21 + msm_mux_##f2, \ 22 + msm_mux_##f3, \ 23 + msm_mux_##f4, \ 24 + msm_mux_##f5, \ 25 + msm_mux_##f6, \ 26 + msm_mux_##f7, \ 27 + msm_mux_##f8, \ 28 + msm_mux_##f9, \ 29 + msm_mux_##f10, \ 30 + msm_mux_##f11 /* egpio mode */ \ 31 + }, \ 32 + .nfuncs = 12, \ 33 + .ctl_reg = REG_SIZE * id, \ 34 + .io_reg = 0x4 + REG_SIZE * id, \ 35 + .intr_cfg_reg = 0x8 + REG_SIZE * id, \ 36 + .intr_status_reg = 0xc + REG_SIZE * id, \ 37 + .intr_target_reg = 0x8 + REG_SIZE * id, \ 38 + .mux_bit = 2, \ 39 + .pull_bit = 0, \ 40 + .drv_bit = 6, \ 41 + .egpio_enable = 12, \ 42 + .egpio_present = 11, \ 43 + .oe_bit = 9, \ 44 + .in_bit = 0, \ 45 + .out_bit = 1, \ 46 + .intr_enable_bit = 0, \ 47 + .intr_status_bit = 0, \ 48 + .intr_wakeup_present_bit = 6, \ 49 + .intr_wakeup_enable_bit = 7, \ 50 + .intr_target_bit = 8, \ 51 + .intr_target_kpss_val = 3, \ 52 + .intr_raw_status_bit = 4, \ 53 + .intr_polarity_bit = 1, \ 54 + .intr_detection_bit = 2, \ 55 + .intr_detection_width = 2, \ 56 + } 57 + 58 + #define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ 59 + { \ 60 + .grp = PINCTRL_PINGROUP(#pg_name, \ 61 + pg_name##_pins, \ 62 + ARRAY_SIZE(pg_name##_pins)), \ 63 + .ctl_reg = ctl, \ 64 + .io_reg = 0, \ 65 + .intr_cfg_reg = 0, \ 66 + .intr_status_reg = 0, \ 67 + .intr_target_reg = 0, \ 68 + .mux_bit = -1, \ 69 + .pull_bit = pull, \ 70 + .drv_bit = drv, \ 71 + .oe_bit = -1, \ 72 + .in_bit = -1, \ 73 + .out_bit = -1, \ 74 + .intr_enable_bit = -1, \ 75 + .intr_status_bit = -1, \ 76 + .intr_target_bit = -1, \ 77 + .intr_raw_status_bit = -1, \ 78 + .intr_polarity_bit = -1, \ 79 + .intr_detection_bit = -1, \ 80 + .intr_detection_width = -1, \ 81 + } 82 + 83 + #define UFS_RESET(pg_name, ctl, io) \ 84 + { \ 85 + .grp = PINCTRL_PINGROUP(#pg_name, \ 86 + pg_name##_pins, \ 87 + ARRAY_SIZE(pg_name##_pins)), \ 88 + .ctl_reg = ctl, \ 89 + .io_reg = io, \ 90 + .intr_cfg_reg = 0, \ 91 + .intr_status_reg = 0, \ 92 + .intr_target_reg = 0, \ 93 + .mux_bit = -1, \ 94 + .pull_bit = 3, \ 95 + .drv_bit = 0, \ 96 + .oe_bit = -1, \ 97 + .in_bit = -1, \ 98 + .out_bit = 0, \ 99 + .intr_enable_bit = -1, \ 100 + .intr_status_bit = -1, \ 101 + .intr_target_bit = -1, \ 102 + .intr_raw_status_bit = -1, \ 103 + .intr_polarity_bit = -1, \ 104 + .intr_detection_bit = -1, \ 105 + .intr_detection_width = -1, \ 106 + } 107 + 108 + static const struct pinctrl_pin_desc kaanapali_pins[] = { 109 + PINCTRL_PIN(0, "GPIO_0"), 110 + PINCTRL_PIN(1, "GPIO_1"), 111 + PINCTRL_PIN(2, "GPIO_2"), 112 + PINCTRL_PIN(3, "GPIO_3"), 113 + PINCTRL_PIN(4, "GPIO_4"), 114 + PINCTRL_PIN(5, "GPIO_5"), 115 + PINCTRL_PIN(6, "GPIO_6"), 116 + PINCTRL_PIN(7, "GPIO_7"), 117 + PINCTRL_PIN(8, "GPIO_8"), 118 + PINCTRL_PIN(9, "GPIO_9"), 119 + PINCTRL_PIN(10, "GPIO_10"), 120 + PINCTRL_PIN(11, "GPIO_11"), 121 + PINCTRL_PIN(12, "GPIO_12"), 122 + PINCTRL_PIN(13, "GPIO_13"), 123 + PINCTRL_PIN(14, "GPIO_14"), 124 + PINCTRL_PIN(15, "GPIO_15"), 125 + PINCTRL_PIN(16, "GPIO_16"), 126 + PINCTRL_PIN(17, "GPIO_17"), 127 + PINCTRL_PIN(18, "GPIO_18"), 128 + PINCTRL_PIN(19, "GPIO_19"), 129 + PINCTRL_PIN(20, "GPIO_20"), 130 + PINCTRL_PIN(21, "GPIO_21"), 131 + PINCTRL_PIN(22, "GPIO_22"), 132 + PINCTRL_PIN(23, "GPIO_23"), 133 + PINCTRL_PIN(24, "GPIO_24"), 134 + PINCTRL_PIN(25, "GPIO_25"), 135 + PINCTRL_PIN(26, "GPIO_26"), 136 + PINCTRL_PIN(27, "GPIO_27"), 137 + PINCTRL_PIN(28, "GPIO_28"), 138 + PINCTRL_PIN(29, "GPIO_29"), 139 + PINCTRL_PIN(30, "GPIO_30"), 140 + PINCTRL_PIN(31, "GPIO_31"), 141 + PINCTRL_PIN(32, "GPIO_32"), 142 + PINCTRL_PIN(33, "GPIO_33"), 143 + PINCTRL_PIN(34, "GPIO_34"), 144 + PINCTRL_PIN(35, "GPIO_35"), 145 + PINCTRL_PIN(36, "GPIO_36"), 146 + PINCTRL_PIN(37, "GPIO_37"), 147 + PINCTRL_PIN(38, "GPIO_38"), 148 + PINCTRL_PIN(39, "GPIO_39"), 149 + PINCTRL_PIN(40, "GPIO_40"), 150 + PINCTRL_PIN(41, "GPIO_41"), 151 + PINCTRL_PIN(42, "GPIO_42"), 152 + PINCTRL_PIN(43, "GPIO_43"), 153 + PINCTRL_PIN(44, "GPIO_44"), 154 + PINCTRL_PIN(45, "GPIO_45"), 155 + PINCTRL_PIN(46, "GPIO_46"), 156 + PINCTRL_PIN(47, "GPIO_47"), 157 + PINCTRL_PIN(48, "GPIO_48"), 158 + PINCTRL_PIN(49, "GPIO_49"), 159 + PINCTRL_PIN(50, "GPIO_50"), 160 + PINCTRL_PIN(51, "GPIO_51"), 161 + PINCTRL_PIN(52, "GPIO_52"), 162 + PINCTRL_PIN(53, "GPIO_53"), 163 + PINCTRL_PIN(54, "GPIO_54"), 164 + PINCTRL_PIN(55, "GPIO_55"), 165 + PINCTRL_PIN(56, "GPIO_56"), 166 + PINCTRL_PIN(57, "GPIO_57"), 167 + PINCTRL_PIN(58, "GPIO_58"), 168 + PINCTRL_PIN(59, "GPIO_59"), 169 + PINCTRL_PIN(60, "GPIO_60"), 170 + PINCTRL_PIN(61, "GPIO_61"), 171 + PINCTRL_PIN(62, "GPIO_62"), 172 + PINCTRL_PIN(63, "GPIO_63"), 173 + PINCTRL_PIN(64, "GPIO_64"), 174 + PINCTRL_PIN(65, "GPIO_65"), 175 + PINCTRL_PIN(66, "GPIO_66"), 176 + PINCTRL_PIN(67, "GPIO_67"), 177 + PINCTRL_PIN(68, "GPIO_68"), 178 + PINCTRL_PIN(69, "GPIO_69"), 179 + PINCTRL_PIN(70, "GPIO_70"), 180 + PINCTRL_PIN(71, "GPIO_71"), 181 + PINCTRL_PIN(72, "GPIO_72"), 182 + PINCTRL_PIN(73, "GPIO_73"), 183 + PINCTRL_PIN(74, "GPIO_74"), 184 + PINCTRL_PIN(75, "GPIO_75"), 185 + PINCTRL_PIN(76, "GPIO_76"), 186 + PINCTRL_PIN(77, "GPIO_77"), 187 + PINCTRL_PIN(78, "GPIO_78"), 188 + PINCTRL_PIN(79, "GPIO_79"), 189 + PINCTRL_PIN(80, "GPIO_80"), 190 + PINCTRL_PIN(81, "GPIO_81"), 191 + PINCTRL_PIN(82, "GPIO_82"), 192 + PINCTRL_PIN(83, "GPIO_83"), 193 + PINCTRL_PIN(84, "GPIO_84"), 194 + PINCTRL_PIN(85, "GPIO_85"), 195 + PINCTRL_PIN(86, "GPIO_86"), 196 + PINCTRL_PIN(87, "GPIO_87"), 197 + PINCTRL_PIN(88, "GPIO_88"), 198 + PINCTRL_PIN(89, "GPIO_89"), 199 + PINCTRL_PIN(90, "GPIO_90"), 200 + PINCTRL_PIN(91, "GPIO_91"), 201 + PINCTRL_PIN(92, "GPIO_92"), 202 + PINCTRL_PIN(93, "GPIO_93"), 203 + PINCTRL_PIN(94, "GPIO_94"), 204 + PINCTRL_PIN(95, "GPIO_95"), 205 + PINCTRL_PIN(96, "GPIO_96"), 206 + PINCTRL_PIN(97, "GPIO_97"), 207 + PINCTRL_PIN(98, "GPIO_98"), 208 + PINCTRL_PIN(99, "GPIO_99"), 209 + PINCTRL_PIN(100, "GPIO_100"), 210 + PINCTRL_PIN(101, "GPIO_101"), 211 + PINCTRL_PIN(102, "GPIO_102"), 212 + PINCTRL_PIN(103, "GPIO_103"), 213 + PINCTRL_PIN(104, "GPIO_104"), 214 + PINCTRL_PIN(105, "GPIO_105"), 215 + PINCTRL_PIN(106, "GPIO_106"), 216 + PINCTRL_PIN(107, "GPIO_107"), 217 + PINCTRL_PIN(108, "GPIO_108"), 218 + PINCTRL_PIN(109, "GPIO_109"), 219 + PINCTRL_PIN(110, "GPIO_110"), 220 + PINCTRL_PIN(111, "GPIO_111"), 221 + PINCTRL_PIN(112, "GPIO_112"), 222 + PINCTRL_PIN(113, "GPIO_113"), 223 + PINCTRL_PIN(114, "GPIO_114"), 224 + PINCTRL_PIN(115, "GPIO_115"), 225 + PINCTRL_PIN(116, "GPIO_116"), 226 + PINCTRL_PIN(117, "GPIO_117"), 227 + PINCTRL_PIN(118, "GPIO_118"), 228 + PINCTRL_PIN(119, "GPIO_119"), 229 + PINCTRL_PIN(120, "GPIO_120"), 230 + PINCTRL_PIN(121, "GPIO_121"), 231 + PINCTRL_PIN(122, "GPIO_122"), 232 + PINCTRL_PIN(123, "GPIO_123"), 233 + PINCTRL_PIN(124, "GPIO_124"), 234 + PINCTRL_PIN(125, "GPIO_125"), 235 + PINCTRL_PIN(126, "GPIO_126"), 236 + PINCTRL_PIN(127, "GPIO_127"), 237 + PINCTRL_PIN(128, "GPIO_128"), 238 + PINCTRL_PIN(129, "GPIO_129"), 239 + PINCTRL_PIN(130, "GPIO_130"), 240 + PINCTRL_PIN(131, "GPIO_131"), 241 + PINCTRL_PIN(132, "GPIO_132"), 242 + PINCTRL_PIN(133, "GPIO_133"), 243 + PINCTRL_PIN(134, "GPIO_134"), 244 + PINCTRL_PIN(135, "GPIO_135"), 245 + PINCTRL_PIN(136, "GPIO_136"), 246 + PINCTRL_PIN(137, "GPIO_137"), 247 + PINCTRL_PIN(138, "GPIO_138"), 248 + PINCTRL_PIN(139, "GPIO_139"), 249 + PINCTRL_PIN(140, "GPIO_140"), 250 + PINCTRL_PIN(141, "GPIO_141"), 251 + PINCTRL_PIN(142, "GPIO_142"), 252 + PINCTRL_PIN(143, "GPIO_143"), 253 + PINCTRL_PIN(144, "GPIO_144"), 254 + PINCTRL_PIN(145, "GPIO_145"), 255 + PINCTRL_PIN(146, "GPIO_146"), 256 + PINCTRL_PIN(147, "GPIO_147"), 257 + PINCTRL_PIN(148, "GPIO_148"), 258 + PINCTRL_PIN(149, "GPIO_149"), 259 + PINCTRL_PIN(150, "GPIO_150"), 260 + PINCTRL_PIN(151, "GPIO_151"), 261 + PINCTRL_PIN(152, "GPIO_152"), 262 + PINCTRL_PIN(153, "GPIO_153"), 263 + PINCTRL_PIN(154, "GPIO_154"), 264 + PINCTRL_PIN(155, "GPIO_155"), 265 + PINCTRL_PIN(156, "GPIO_156"), 266 + PINCTRL_PIN(157, "GPIO_157"), 267 + PINCTRL_PIN(158, "GPIO_158"), 268 + PINCTRL_PIN(159, "GPIO_159"), 269 + PINCTRL_PIN(160, "GPIO_160"), 270 + PINCTRL_PIN(161, "GPIO_161"), 271 + PINCTRL_PIN(162, "GPIO_162"), 272 + PINCTRL_PIN(163, "GPIO_163"), 273 + PINCTRL_PIN(164, "GPIO_164"), 274 + PINCTRL_PIN(165, "GPIO_165"), 275 + PINCTRL_PIN(166, "GPIO_166"), 276 + PINCTRL_PIN(167, "GPIO_167"), 277 + PINCTRL_PIN(168, "GPIO_168"), 278 + PINCTRL_PIN(169, "GPIO_169"), 279 + PINCTRL_PIN(170, "GPIO_170"), 280 + PINCTRL_PIN(171, "GPIO_171"), 281 + PINCTRL_PIN(172, "GPIO_172"), 282 + PINCTRL_PIN(173, "GPIO_173"), 283 + PINCTRL_PIN(174, "GPIO_174"), 284 + PINCTRL_PIN(175, "GPIO_175"), 285 + PINCTRL_PIN(176, "GPIO_176"), 286 + PINCTRL_PIN(177, "GPIO_177"), 287 + PINCTRL_PIN(178, "GPIO_178"), 288 + PINCTRL_PIN(179, "GPIO_179"), 289 + PINCTRL_PIN(180, "GPIO_180"), 290 + PINCTRL_PIN(181, "GPIO_181"), 291 + PINCTRL_PIN(182, "GPIO_182"), 292 + PINCTRL_PIN(183, "GPIO_183"), 293 + PINCTRL_PIN(184, "GPIO_184"), 294 + PINCTRL_PIN(185, "GPIO_185"), 295 + PINCTRL_PIN(186, "GPIO_186"), 296 + PINCTRL_PIN(187, "GPIO_187"), 297 + PINCTRL_PIN(188, "GPIO_188"), 298 + PINCTRL_PIN(189, "GPIO_189"), 299 + PINCTRL_PIN(190, "GPIO_190"), 300 + PINCTRL_PIN(191, "GPIO_191"), 301 + PINCTRL_PIN(192, "GPIO_192"), 302 + PINCTRL_PIN(193, "GPIO_193"), 303 + PINCTRL_PIN(194, "GPIO_194"), 304 + PINCTRL_PIN(195, "GPIO_195"), 305 + PINCTRL_PIN(196, "GPIO_196"), 306 + PINCTRL_PIN(197, "GPIO_197"), 307 + PINCTRL_PIN(198, "GPIO_198"), 308 + PINCTRL_PIN(199, "GPIO_199"), 309 + PINCTRL_PIN(200, "GPIO_200"), 310 + PINCTRL_PIN(201, "GPIO_201"), 311 + PINCTRL_PIN(202, "GPIO_202"), 312 + PINCTRL_PIN(203, "GPIO_203"), 313 + PINCTRL_PIN(204, "GPIO_204"), 314 + PINCTRL_PIN(205, "GPIO_205"), 315 + PINCTRL_PIN(206, "GPIO_206"), 316 + PINCTRL_PIN(207, "GPIO_207"), 317 + PINCTRL_PIN(208, "GPIO_208"), 318 + PINCTRL_PIN(209, "GPIO_209"), 319 + PINCTRL_PIN(210, "GPIO_210"), 320 + PINCTRL_PIN(211, "GPIO_211"), 321 + PINCTRL_PIN(212, "GPIO_212"), 322 + PINCTRL_PIN(213, "GPIO_213"), 323 + PINCTRL_PIN(214, "GPIO_214"), 324 + PINCTRL_PIN(215, "GPIO_215"), 325 + PINCTRL_PIN(216, "GPIO_216"), 326 + PINCTRL_PIN(217, "UFS_RESET"), 327 + PINCTRL_PIN(218, "SDC2_CLK"), 328 + PINCTRL_PIN(219, "SDC2_CMD"), 329 + PINCTRL_PIN(220, "SDC2_DATA"), 330 + }; 331 + 332 + #define DECLARE_MSM_GPIO_PINS(pin) \ 333 + static const unsigned int gpio##pin##_pins[] = { pin } 334 + DECLARE_MSM_GPIO_PINS(0); 335 + DECLARE_MSM_GPIO_PINS(1); 336 + DECLARE_MSM_GPIO_PINS(2); 337 + DECLARE_MSM_GPIO_PINS(3); 338 + DECLARE_MSM_GPIO_PINS(4); 339 + DECLARE_MSM_GPIO_PINS(5); 340 + DECLARE_MSM_GPIO_PINS(6); 341 + DECLARE_MSM_GPIO_PINS(7); 342 + DECLARE_MSM_GPIO_PINS(8); 343 + DECLARE_MSM_GPIO_PINS(9); 344 + DECLARE_MSM_GPIO_PINS(10); 345 + DECLARE_MSM_GPIO_PINS(11); 346 + DECLARE_MSM_GPIO_PINS(12); 347 + DECLARE_MSM_GPIO_PINS(13); 348 + DECLARE_MSM_GPIO_PINS(14); 349 + DECLARE_MSM_GPIO_PINS(15); 350 + DECLARE_MSM_GPIO_PINS(16); 351 + DECLARE_MSM_GPIO_PINS(17); 352 + DECLARE_MSM_GPIO_PINS(18); 353 + DECLARE_MSM_GPIO_PINS(19); 354 + DECLARE_MSM_GPIO_PINS(20); 355 + DECLARE_MSM_GPIO_PINS(21); 356 + DECLARE_MSM_GPIO_PINS(22); 357 + DECLARE_MSM_GPIO_PINS(23); 358 + DECLARE_MSM_GPIO_PINS(24); 359 + DECLARE_MSM_GPIO_PINS(25); 360 + DECLARE_MSM_GPIO_PINS(26); 361 + DECLARE_MSM_GPIO_PINS(27); 362 + DECLARE_MSM_GPIO_PINS(28); 363 + DECLARE_MSM_GPIO_PINS(29); 364 + DECLARE_MSM_GPIO_PINS(30); 365 + DECLARE_MSM_GPIO_PINS(31); 366 + DECLARE_MSM_GPIO_PINS(32); 367 + DECLARE_MSM_GPIO_PINS(33); 368 + DECLARE_MSM_GPIO_PINS(34); 369 + DECLARE_MSM_GPIO_PINS(35); 370 + DECLARE_MSM_GPIO_PINS(36); 371 + DECLARE_MSM_GPIO_PINS(37); 372 + DECLARE_MSM_GPIO_PINS(38); 373 + DECLARE_MSM_GPIO_PINS(39); 374 + DECLARE_MSM_GPIO_PINS(40); 375 + DECLARE_MSM_GPIO_PINS(41); 376 + DECLARE_MSM_GPIO_PINS(42); 377 + DECLARE_MSM_GPIO_PINS(43); 378 + DECLARE_MSM_GPIO_PINS(44); 379 + DECLARE_MSM_GPIO_PINS(45); 380 + DECLARE_MSM_GPIO_PINS(46); 381 + DECLARE_MSM_GPIO_PINS(47); 382 + DECLARE_MSM_GPIO_PINS(48); 383 + DECLARE_MSM_GPIO_PINS(49); 384 + DECLARE_MSM_GPIO_PINS(50); 385 + DECLARE_MSM_GPIO_PINS(51); 386 + DECLARE_MSM_GPIO_PINS(52); 387 + DECLARE_MSM_GPIO_PINS(53); 388 + DECLARE_MSM_GPIO_PINS(54); 389 + DECLARE_MSM_GPIO_PINS(55); 390 + DECLARE_MSM_GPIO_PINS(56); 391 + DECLARE_MSM_GPIO_PINS(57); 392 + DECLARE_MSM_GPIO_PINS(58); 393 + DECLARE_MSM_GPIO_PINS(59); 394 + DECLARE_MSM_GPIO_PINS(60); 395 + DECLARE_MSM_GPIO_PINS(61); 396 + DECLARE_MSM_GPIO_PINS(62); 397 + DECLARE_MSM_GPIO_PINS(63); 398 + DECLARE_MSM_GPIO_PINS(64); 399 + DECLARE_MSM_GPIO_PINS(65); 400 + DECLARE_MSM_GPIO_PINS(66); 401 + DECLARE_MSM_GPIO_PINS(67); 402 + DECLARE_MSM_GPIO_PINS(68); 403 + DECLARE_MSM_GPIO_PINS(69); 404 + DECLARE_MSM_GPIO_PINS(70); 405 + DECLARE_MSM_GPIO_PINS(71); 406 + DECLARE_MSM_GPIO_PINS(72); 407 + DECLARE_MSM_GPIO_PINS(73); 408 + DECLARE_MSM_GPIO_PINS(74); 409 + DECLARE_MSM_GPIO_PINS(75); 410 + DECLARE_MSM_GPIO_PINS(76); 411 + DECLARE_MSM_GPIO_PINS(77); 412 + DECLARE_MSM_GPIO_PINS(78); 413 + DECLARE_MSM_GPIO_PINS(79); 414 + DECLARE_MSM_GPIO_PINS(80); 415 + DECLARE_MSM_GPIO_PINS(81); 416 + DECLARE_MSM_GPIO_PINS(82); 417 + DECLARE_MSM_GPIO_PINS(83); 418 + DECLARE_MSM_GPIO_PINS(84); 419 + DECLARE_MSM_GPIO_PINS(85); 420 + DECLARE_MSM_GPIO_PINS(86); 421 + DECLARE_MSM_GPIO_PINS(87); 422 + DECLARE_MSM_GPIO_PINS(88); 423 + DECLARE_MSM_GPIO_PINS(89); 424 + DECLARE_MSM_GPIO_PINS(90); 425 + DECLARE_MSM_GPIO_PINS(91); 426 + DECLARE_MSM_GPIO_PINS(92); 427 + DECLARE_MSM_GPIO_PINS(93); 428 + DECLARE_MSM_GPIO_PINS(94); 429 + DECLARE_MSM_GPIO_PINS(95); 430 + DECLARE_MSM_GPIO_PINS(96); 431 + DECLARE_MSM_GPIO_PINS(97); 432 + DECLARE_MSM_GPIO_PINS(98); 433 + DECLARE_MSM_GPIO_PINS(99); 434 + DECLARE_MSM_GPIO_PINS(100); 435 + DECLARE_MSM_GPIO_PINS(101); 436 + DECLARE_MSM_GPIO_PINS(102); 437 + DECLARE_MSM_GPIO_PINS(103); 438 + DECLARE_MSM_GPIO_PINS(104); 439 + DECLARE_MSM_GPIO_PINS(105); 440 + DECLARE_MSM_GPIO_PINS(106); 441 + DECLARE_MSM_GPIO_PINS(107); 442 + DECLARE_MSM_GPIO_PINS(108); 443 + DECLARE_MSM_GPIO_PINS(109); 444 + DECLARE_MSM_GPIO_PINS(110); 445 + DECLARE_MSM_GPIO_PINS(111); 446 + DECLARE_MSM_GPIO_PINS(112); 447 + DECLARE_MSM_GPIO_PINS(113); 448 + DECLARE_MSM_GPIO_PINS(114); 449 + DECLARE_MSM_GPIO_PINS(115); 450 + DECLARE_MSM_GPIO_PINS(116); 451 + DECLARE_MSM_GPIO_PINS(117); 452 + DECLARE_MSM_GPIO_PINS(118); 453 + DECLARE_MSM_GPIO_PINS(119); 454 + DECLARE_MSM_GPIO_PINS(120); 455 + DECLARE_MSM_GPIO_PINS(121); 456 + DECLARE_MSM_GPIO_PINS(122); 457 + DECLARE_MSM_GPIO_PINS(123); 458 + DECLARE_MSM_GPIO_PINS(124); 459 + DECLARE_MSM_GPIO_PINS(125); 460 + DECLARE_MSM_GPIO_PINS(126); 461 + DECLARE_MSM_GPIO_PINS(127); 462 + DECLARE_MSM_GPIO_PINS(128); 463 + DECLARE_MSM_GPIO_PINS(129); 464 + DECLARE_MSM_GPIO_PINS(130); 465 + DECLARE_MSM_GPIO_PINS(131); 466 + DECLARE_MSM_GPIO_PINS(132); 467 + DECLARE_MSM_GPIO_PINS(133); 468 + DECLARE_MSM_GPIO_PINS(134); 469 + DECLARE_MSM_GPIO_PINS(135); 470 + DECLARE_MSM_GPIO_PINS(136); 471 + DECLARE_MSM_GPIO_PINS(137); 472 + DECLARE_MSM_GPIO_PINS(138); 473 + DECLARE_MSM_GPIO_PINS(139); 474 + DECLARE_MSM_GPIO_PINS(140); 475 + DECLARE_MSM_GPIO_PINS(141); 476 + DECLARE_MSM_GPIO_PINS(142); 477 + DECLARE_MSM_GPIO_PINS(143); 478 + DECLARE_MSM_GPIO_PINS(144); 479 + DECLARE_MSM_GPIO_PINS(145); 480 + DECLARE_MSM_GPIO_PINS(146); 481 + DECLARE_MSM_GPIO_PINS(147); 482 + DECLARE_MSM_GPIO_PINS(148); 483 + DECLARE_MSM_GPIO_PINS(149); 484 + DECLARE_MSM_GPIO_PINS(150); 485 + DECLARE_MSM_GPIO_PINS(151); 486 + DECLARE_MSM_GPIO_PINS(152); 487 + DECLARE_MSM_GPIO_PINS(153); 488 + DECLARE_MSM_GPIO_PINS(154); 489 + DECLARE_MSM_GPIO_PINS(155); 490 + DECLARE_MSM_GPIO_PINS(156); 491 + DECLARE_MSM_GPIO_PINS(157); 492 + DECLARE_MSM_GPIO_PINS(158); 493 + DECLARE_MSM_GPIO_PINS(159); 494 + DECLARE_MSM_GPIO_PINS(160); 495 + DECLARE_MSM_GPIO_PINS(161); 496 + DECLARE_MSM_GPIO_PINS(162); 497 + DECLARE_MSM_GPIO_PINS(163); 498 + DECLARE_MSM_GPIO_PINS(164); 499 + DECLARE_MSM_GPIO_PINS(165); 500 + DECLARE_MSM_GPIO_PINS(166); 501 + DECLARE_MSM_GPIO_PINS(167); 502 + DECLARE_MSM_GPIO_PINS(168); 503 + DECLARE_MSM_GPIO_PINS(169); 504 + DECLARE_MSM_GPIO_PINS(170); 505 + DECLARE_MSM_GPIO_PINS(171); 506 + DECLARE_MSM_GPIO_PINS(172); 507 + DECLARE_MSM_GPIO_PINS(173); 508 + DECLARE_MSM_GPIO_PINS(174); 509 + DECLARE_MSM_GPIO_PINS(175); 510 + DECLARE_MSM_GPIO_PINS(176); 511 + DECLARE_MSM_GPIO_PINS(177); 512 + DECLARE_MSM_GPIO_PINS(178); 513 + DECLARE_MSM_GPIO_PINS(179); 514 + DECLARE_MSM_GPIO_PINS(180); 515 + DECLARE_MSM_GPIO_PINS(181); 516 + DECLARE_MSM_GPIO_PINS(182); 517 + DECLARE_MSM_GPIO_PINS(183); 518 + DECLARE_MSM_GPIO_PINS(184); 519 + DECLARE_MSM_GPIO_PINS(185); 520 + DECLARE_MSM_GPIO_PINS(186); 521 + DECLARE_MSM_GPIO_PINS(187); 522 + DECLARE_MSM_GPIO_PINS(188); 523 + DECLARE_MSM_GPIO_PINS(189); 524 + DECLARE_MSM_GPIO_PINS(190); 525 + DECLARE_MSM_GPIO_PINS(191); 526 + DECLARE_MSM_GPIO_PINS(192); 527 + DECLARE_MSM_GPIO_PINS(193); 528 + DECLARE_MSM_GPIO_PINS(194); 529 + DECLARE_MSM_GPIO_PINS(195); 530 + DECLARE_MSM_GPIO_PINS(196); 531 + DECLARE_MSM_GPIO_PINS(197); 532 + DECLARE_MSM_GPIO_PINS(198); 533 + DECLARE_MSM_GPIO_PINS(199); 534 + DECLARE_MSM_GPIO_PINS(200); 535 + DECLARE_MSM_GPIO_PINS(201); 536 + DECLARE_MSM_GPIO_PINS(202); 537 + DECLARE_MSM_GPIO_PINS(203); 538 + DECLARE_MSM_GPIO_PINS(204); 539 + DECLARE_MSM_GPIO_PINS(205); 540 + DECLARE_MSM_GPIO_PINS(206); 541 + DECLARE_MSM_GPIO_PINS(207); 542 + DECLARE_MSM_GPIO_PINS(208); 543 + DECLARE_MSM_GPIO_PINS(209); 544 + DECLARE_MSM_GPIO_PINS(210); 545 + DECLARE_MSM_GPIO_PINS(211); 546 + DECLARE_MSM_GPIO_PINS(212); 547 + DECLARE_MSM_GPIO_PINS(213); 548 + DECLARE_MSM_GPIO_PINS(214); 549 + DECLARE_MSM_GPIO_PINS(215); 550 + DECLARE_MSM_GPIO_PINS(216); 551 + 552 + static const unsigned int ufs_reset_pins[] = { 217 }; 553 + static const unsigned int sdc2_clk_pins[] = { 218 }; 554 + static const unsigned int sdc2_cmd_pins[] = { 219 }; 555 + static const unsigned int sdc2_data_pins[] = { 220 }; 556 + 557 + enum kaanapali_functions { 558 + msm_mux_gpio, 559 + msm_mux_aoss_cti, 560 + msm_mux_atest_char, 561 + msm_mux_atest_usb, 562 + msm_mux_audio_ext_mclk0, 563 + msm_mux_audio_ext_mclk1, 564 + msm_mux_audio_ref_clk, 565 + msm_mux_cam_asc_mclk2, 566 + msm_mux_cam_asc_mclk4, 567 + msm_mux_cam_mclk, 568 + msm_mux_cci_async_in, 569 + msm_mux_cci_i2c_scl, 570 + msm_mux_cci_i2c_sda, 571 + msm_mux_cci_timer, 572 + msm_mux_cmu_rng, 573 + msm_mux_coex_uart1_rx, 574 + msm_mux_coex_uart1_tx, 575 + msm_mux_coex_uart2_rx, 576 + msm_mux_coex_uart2_tx, 577 + msm_mux_dbg_out_clk, 578 + msm_mux_ddr_bist_complete, 579 + msm_mux_ddr_bist_fail, 580 + msm_mux_ddr_bist_start, 581 + msm_mux_ddr_bist_stop, 582 + msm_mux_ddr_pxi0, 583 + msm_mux_ddr_pxi1, 584 + msm_mux_ddr_pxi2, 585 + msm_mux_ddr_pxi3, 586 + msm_mux_dp_hot, 587 + msm_mux_egpio, 588 + msm_mux_gcc_gp1, 589 + msm_mux_gcc_gp2, 590 + msm_mux_gcc_gp3, 591 + msm_mux_gnss_adc0, 592 + msm_mux_gnss_adc1, 593 + msm_mux_i2chub0_se0, 594 + msm_mux_i2chub0_se1, 595 + msm_mux_i2chub0_se2, 596 + msm_mux_i2chub0_se3, 597 + msm_mux_i2chub0_se4, 598 + msm_mux_i2s0_data0, 599 + msm_mux_i2s0_data1, 600 + msm_mux_i2s0_sck, 601 + msm_mux_i2s0_ws, 602 + msm_mux_i2s1_data0, 603 + msm_mux_i2s1_data1, 604 + msm_mux_i2s1_sck, 605 + msm_mux_i2s1_ws, 606 + msm_mux_ibi_i3c, 607 + msm_mux_jitter_bist, 608 + msm_mux_mdp_esync0_out, 609 + msm_mux_mdp_esync1_out, 610 + msm_mux_mdp_vsync, 611 + msm_mux_mdp_vsync0_out, 612 + msm_mux_mdp_vsync1_out, 613 + msm_mux_mdp_vsync2_out, 614 + msm_mux_mdp_vsync3_out, 615 + msm_mux_mdp_vsync5_out, 616 + msm_mux_mdp_vsync_e, 617 + msm_mux_nav_gpio0, 618 + msm_mux_nav_gpio1, 619 + msm_mux_nav_gpio2, 620 + msm_mux_nav_gpio3, 621 + msm_mux_pcie0_clk_req_n, 622 + msm_mux_phase_flag, 623 + msm_mux_pll_bist_sync, 624 + msm_mux_pll_clk_aux, 625 + msm_mux_prng_rosc0, 626 + msm_mux_prng_rosc1, 627 + msm_mux_prng_rosc2, 628 + msm_mux_prng_rosc3, 629 + msm_mux_qdss_cti, 630 + msm_mux_qdss_gpio_traceclk, 631 + msm_mux_qdss_gpio_tracectl, 632 + msm_mux_qdss_gpio_tracedata, 633 + msm_mux_qlink_big_enable, 634 + msm_mux_qlink_big_request, 635 + msm_mux_qlink_little_enable, 636 + msm_mux_qlink_little_request, 637 + msm_mux_qlink_wmss, 638 + msm_mux_qspi0, 639 + msm_mux_qspi1, 640 + msm_mux_qspi2, 641 + msm_mux_qspi3, 642 + msm_mux_qspi_clk, 643 + msm_mux_qspi_cs, 644 + msm_mux_qup1_se0, 645 + msm_mux_qup1_se1, 646 + msm_mux_qup1_se2, 647 + msm_mux_qup1_se3, 648 + msm_mux_qup1_se4, 649 + msm_mux_qup1_se5, 650 + msm_mux_qup1_se6, 651 + msm_mux_qup1_se7, 652 + msm_mux_qup2_se0, 653 + msm_mux_qup2_se1, 654 + msm_mux_qup2_se2, 655 + msm_mux_qup2_se3, 656 + msm_mux_qup2_se4, 657 + msm_mux_qup3_se0, 658 + msm_mux_qup3_se1, 659 + msm_mux_qup3_se2, 660 + msm_mux_qup3_se3, 661 + msm_mux_qup3_se4, 662 + msm_mux_qup3_se5, 663 + msm_mux_qup4_se0, 664 + msm_mux_qup4_se1, 665 + msm_mux_qup4_se2, 666 + msm_mux_qup4_se3, 667 + msm_mux_qup4_se4, 668 + msm_mux_sd_write_protect, 669 + msm_mux_sdc40, 670 + msm_mux_sdc41, 671 + msm_mux_sdc42, 672 + msm_mux_sdc43, 673 + msm_mux_sdc4_clk, 674 + msm_mux_sdc4_cmd, 675 + msm_mux_sys_throttle, 676 + msm_mux_tb_trig_sdc2, 677 + msm_mux_tb_trig_sdc4, 678 + msm_mux_tmess_prng0, 679 + msm_mux_tmess_prng1, 680 + msm_mux_tmess_prng2, 681 + msm_mux_tmess_prng3, 682 + msm_mux_tsense_pwm1, 683 + msm_mux_tsense_pwm2, 684 + msm_mux_tsense_pwm3, 685 + msm_mux_tsense_pwm4, 686 + msm_mux_tsense_pwm5, 687 + msm_mux_tsense_pwm6, 688 + msm_mux_tsense_pwm7, 689 + msm_mux_uim0_clk, 690 + msm_mux_uim0_data, 691 + msm_mux_uim0_present, 692 + msm_mux_uim0_reset, 693 + msm_mux_uim1_clk, 694 + msm_mux_uim1_data, 695 + msm_mux_uim1_present, 696 + msm_mux_uim1_reset, 697 + msm_mux_usb0_hs, 698 + msm_mux_usb_phy, 699 + msm_mux_vfr_0, 700 + msm_mux_vfr_1, 701 + msm_mux_vsense_trigger_mirnat, 702 + msm_mux_wcn_sw, 703 + msm_mux_wcn_sw_ctrl, 704 + msm_mux__, 705 + }; 706 + 707 + static const char *const gpio_groups[] = { 708 + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", 709 + "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", 710 + "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", 711 + "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23", 712 + "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", 713 + "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", 714 + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", 715 + "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", 716 + "gpio48", "gpio49", "gpio50", "gpio51", "gpio52", "gpio53", 717 + "gpio54", "gpio55", "gpio56", "gpio57", "gpio58", "gpio59", 718 + "gpio60", "gpio61", "gpio62", "gpio63", "gpio64", "gpio65", 719 + "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", "gpio71", 720 + "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", 721 + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", 722 + "gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", 723 + "gpio90", "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", 724 + "gpio96", "gpio97", "gpio98", "gpio99", "gpio100", "gpio101", 725 + "gpio102", "gpio103", "gpio104", "gpio105", "gpio106", "gpio107", 726 + "gpio108", "gpio109", "gpio110", "gpio111", "gpio112", "gpio113", 727 + "gpio114", "gpio115", "gpio116", "gpio117", "gpio118", "gpio119", 728 + "gpio120", "gpio121", "gpio122", "gpio123", "gpio124", "gpio125", 729 + "gpio126", "gpio127", "gpio128", "gpio129", "gpio130", "gpio131", 730 + "gpio132", "gpio133", "gpio134", "gpio135", "gpio136", "gpio137", 731 + "gpio138", "gpio139", "gpio140", "gpio141", "gpio142", "gpio143", 732 + "gpio144", "gpio145", "gpio146", "gpio147", "gpio148", "gpio149", 733 + "gpio150", "gpio151", "gpio152", "gpio153", "gpio154", "gpio155", 734 + "gpio156", "gpio157", "gpio158", "gpio159", "gpio160", "gpio161", 735 + "gpio162", "gpio163", "gpio164", "gpio165", "gpio166", "gpio167", 736 + "gpio168", "gpio169", "gpio170", "gpio171", "gpio172", "gpio173", 737 + "gpio174", "gpio175", "gpio176", "gpio177", "gpio178", "gpio179", 738 + "gpio180", "gpio181", "gpio182", "gpio183", "gpio184", "gpio185", 739 + "gpio186", "gpio187", "gpio188", "gpio189", "gpio190", "gpio191", 740 + "gpio192", "gpio193", "gpio194", "gpio195", "gpio196", "gpio197", 741 + "gpio198", "gpio199", "gpio200", "gpio201", "gpio202", "gpio203", 742 + "gpio204", "gpio205", "gpio206", "gpio207", "gpio208", "gpio209", 743 + "gpio210", "gpio211", "gpio212", "gpio213", "gpio214", "gpio215", 744 + "gpio216", 745 + }; 746 + 747 + static const char *const aoss_cti_groups[] = { 748 + "gpio74", "gpio75", "gpio76", "gpio77", 749 + }; 750 + 751 + static const char *const atest_char_groups[] = { 752 + "gpio126", "gpio127", "gpio128", "gpio129", "gpio133", 753 + }; 754 + 755 + static const char *const atest_usb_groups[] = { 756 + "gpio70", "gpio71", "gpio72", "gpio73", "gpio129", 757 + }; 758 + 759 + static const char *const audio_ext_mclk0_groups[] = { 760 + "gpio121", 761 + }; 762 + 763 + static const char *const audio_ext_mclk1_groups[] = { 764 + "gpio120", 765 + }; 766 + 767 + static const char *const audio_ref_clk_groups[] = { 768 + "gpio120", 769 + }; 770 + 771 + static const char *const cam_asc_mclk2_groups[] = { 772 + "gpio91", 773 + }; 774 + 775 + static const char *const cam_asc_mclk4_groups[] = { 776 + "gpio93", 777 + }; 778 + 779 + static const char *const cam_mclk_groups[] = { 780 + "gpio89", "gpio90", "gpio92", "gpio94", "gpio95", "gpio96", 781 + }; 782 + 783 + static const char *const cci_async_in_groups[] = { 784 + "gpio10", "gpio11", "gpio15", 785 + }; 786 + 787 + static const char *const cci_i2c_scl_groups[] = { 788 + "gpio110", "gpio112", "gpio114", "gpio116", "gpio149", "gpio160", 789 + }; 790 + 791 + static const char *const cci_i2c_sda_groups[] = { 792 + "gpio107", "gpio108", "gpio109", "gpio111", "gpio113", "gpio115", 793 + }; 794 + 795 + static const char *const cci_timer_groups[] = { 796 + "gpio105", "gpio106", "gpio107", "gpio159", "gpio160", 797 + }; 798 + 799 + static const char *const cmu_rng_groups[] = { 800 + "gpio40", "gpio41", "gpio42", "gpio43", "gpio144", "gpio145", 801 + "gpio146", "gpio147", 802 + }; 803 + 804 + static const char *const coex_uart1_rx_groups[] = { 805 + "gpio144", 806 + }; 807 + 808 + static const char *const coex_uart1_tx_groups[] = { 809 + "gpio145", 810 + }; 811 + 812 + static const char *const coex_uart2_rx_groups[] = { 813 + "gpio146", 814 + }; 815 + 816 + static const char *const coex_uart2_tx_groups[] = { 817 + "gpio147", 818 + }; 819 + 820 + static const char *const dbg_out_clk_groups[] = { 821 + "gpio42", 822 + }; 823 + 824 + static const char *const ddr_bist_complete_groups[] = { 825 + "gpio44", 826 + }; 827 + 828 + static const char *const ddr_bist_fail_groups[] = { 829 + "gpio40", 830 + }; 831 + 832 + static const char *const ddr_bist_start_groups[] = { 833 + "gpio41", 834 + }; 835 + 836 + static const char *const ddr_bist_stop_groups[] = { 837 + "gpio45", 838 + }; 839 + 840 + static const char *const ddr_pxi0_groups[] = { 841 + "gpio54", "gpio55", 842 + }; 843 + 844 + static const char *const ddr_pxi1_groups[] = { 845 + "gpio44", "gpio45", 846 + }; 847 + 848 + static const char *const ddr_pxi2_groups[] = { 849 + "gpio43", "gpio52", 850 + }; 851 + 852 + static const char *const ddr_pxi3_groups[] = { 853 + "gpio46", "gpio53", 854 + }; 855 + 856 + static const char *const dp_hot_groups[] = { 857 + "gpio47", 858 + }; 859 + 860 + static const char *const egpio_groups[] = { 861 + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", 862 + "gpio6", "gpio7", "gpio28", "gpio29", "gpio48", "gpio49", 863 + "gpio50", "gpio51", "gpio163", "gpio164", "gpio165", "gpio166", 864 + "gpio167", "gpio168", "gpio169", "gpio170", "gpio171", "gpio172", 865 + "gpio173", "gpio174", "gpio175", "gpio176", "gpio177", "gpio178", 866 + "gpio179", "gpio180", "gpio181", "gpio182", "gpio183", "gpio184", 867 + "gpio185", "gpio186", "gpio187", "gpio188", "gpio189", "gpio190", 868 + "gpio191", "gpio192", "gpio193", "gpio194", "gpio195", "gpio196", 869 + "gpio197", "gpio198", "gpio199", "gpio200", "gpio201", "gpio202", 870 + "gpio203", "gpio204", "gpio205", "gpio206", "gpio207", "gpio208", 871 + "gpio209", "gpio210", "gpio211", "gpio212", "gpio213", "gpio214", 872 + "gpio215", "gpio216", 873 + }; 874 + 875 + static const char *const gcc_gp1_groups[] = { 876 + "gpio130", "gpio158", 877 + }; 878 + 879 + static const char *const gcc_gp2_groups[] = { 880 + "gpio86", "gpio131", 881 + }; 882 + 883 + static const char *const gcc_gp3_groups[] = { 884 + "gpio87", "gpio132", 885 + }; 886 + 887 + static const char *const gnss_adc0_groups[] = { 888 + "gpio40", "gpio41", 889 + }; 890 + 891 + static const char *const gnss_adc1_groups[] = { 892 + "gpio42", "gpio77", 893 + }; 894 + 895 + static const char *const i2chub0_se0_groups[] = { 896 + "gpio66", "gpio67", 897 + }; 898 + 899 + static const char *const i2chub0_se1_groups[] = { 900 + "gpio78", "gpio79", 901 + }; 902 + 903 + static const char *const i2chub0_se2_groups[] = { 904 + "gpio68", "gpio69", 905 + }; 906 + 907 + static const char *const i2chub0_se3_groups[] = { 908 + "gpio70", "gpio71", 909 + }; 910 + 911 + static const char *const i2chub0_se4_groups[] = { 912 + "gpio72", "gpio73", 913 + }; 914 + 915 + static const char *const i2s0_data0_groups[] = { 916 + "gpio123", 917 + }; 918 + 919 + static const char *const i2s0_data1_groups[] = { 920 + "gpio124", 921 + }; 922 + 923 + static const char *const i2s0_sck_groups[] = { 924 + "gpio122", 925 + }; 926 + 927 + static const char *const i2s0_ws_groups[] = { 928 + "gpio125", 929 + }; 930 + 931 + static const char *const i2s1_data0_groups[] = { 932 + "gpio118", 933 + }; 934 + 935 + static const char *const i2s1_data1_groups[] = { 936 + "gpio120", 937 + }; 938 + 939 + static const char *const i2s1_sck_groups[] = { 940 + "gpio117", 941 + }; 942 + 943 + static const char *const i2s1_ws_groups[] = { 944 + "gpio119", 945 + }; 946 + 947 + static const char *const ibi_i3c_groups[] = { 948 + "gpio0", "gpio1", "gpio4", "gpio5", "gpio8", "gpio9", 949 + "gpio12", "gpio13", "gpio28", "gpio29", "gpio32", "gpio33", 950 + "gpio36", "gpio37", "gpio48", "gpio49", "gpio60", "gpio61", 951 + }; 952 + 953 + static const char *const jitter_bist_groups[] = { 954 + "gpio73", 955 + }; 956 + 957 + static const char *const mdp_esync0_out_groups[] = { 958 + "gpio88", 959 + }; 960 + 961 + static const char *const mdp_esync1_out_groups[] = { 962 + "gpio100", 963 + }; 964 + 965 + static const char *const mdp_vsync_groups[] = { 966 + "gpio86", "gpio87", "gpio97", "gpio98", 967 + }; 968 + 969 + static const char *const mdp_vsync0_out_groups[] = { 970 + "gpio86", 971 + }; 972 + 973 + static const char *const mdp_vsync1_out_groups[] = { 974 + "gpio86", 975 + }; 976 + 977 + static const char *const mdp_vsync2_out_groups[] = { 978 + "gpio87", 979 + }; 980 + 981 + static const char *const mdp_vsync3_out_groups[] = { 982 + "gpio87", 983 + }; 984 + 985 + static const char *const mdp_vsync5_out_groups[] = { 986 + "gpio87", 987 + }; 988 + 989 + static const char *const mdp_vsync_e_groups[] = { 990 + "gpio88", 991 + }; 992 + 993 + static const char *const nav_gpio0_groups[] = { 994 + "gpio150", 995 + }; 996 + 997 + static const char *const nav_gpio1_groups[] = { 998 + "gpio151", 999 + }; 1000 + 1001 + static const char *const nav_gpio2_groups[] = { 1002 + "gpio148", 1003 + }; 1004 + 1005 + static const char *const nav_gpio3_groups[] = { 1006 + "gpio150", 1007 + }; 1008 + 1009 + static const char *const pcie0_clk_req_n_groups[] = { 1010 + "gpio103", 1011 + }; 1012 + 1013 + static const char *const phase_flag_groups[] = { 1014 + "gpio117", "gpio118", "gpio119", "gpio123", "gpio124", "gpio125", 1015 + "gpio169", "gpio170", "gpio171", "gpio172", "gpio173", "gpio175", 1016 + "gpio176", "gpio179", "gpio180", "gpio181", "gpio184", "gpio185", 1017 + "gpio192", "gpio196", "gpio197", "gpio198", "gpio199", "gpio204", 1018 + "gpio206", "gpio207", "gpio208", "gpio210", "gpio211", "gpio214", 1019 + "gpio215", "gpio216", 1020 + }; 1021 + 1022 + static const char *const pll_bist_sync_groups[] = { 1023 + "gpio104", 1024 + }; 1025 + 1026 + static const char *const pll_clk_aux_groups[] = { 1027 + "gpio94", 1028 + }; 1029 + 1030 + static const char *const prng_rosc0_groups[] = { 1031 + "gpio85", 1032 + }; 1033 + 1034 + static const char *const prng_rosc1_groups[] = { 1035 + "gpio64", 1036 + }; 1037 + 1038 + static const char *const prng_rosc2_groups[] = { 1039 + "gpio65", 1040 + }; 1041 + 1042 + static const char *const prng_rosc3_groups[] = { 1043 + "gpio66", 1044 + }; 1045 + 1046 + static const char *const qdss_cti_groups[] = { 1047 + "gpio27", "gpio31", "gpio72", "gpio73", "gpio82", "gpio83", 1048 + "gpio155", "gpio158", 1049 + }; 1050 + 1051 + static const char *const qdss_gpio_traceclk_groups[] = { 1052 + "gpio128", 1053 + }; 1054 + 1055 + static const char *const qdss_gpio_tracectl_groups[] = { 1056 + "gpio127", 1057 + }; 1058 + 1059 + static const char *const qdss_gpio_tracedata_groups[] = { 1060 + "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43", 1061 + "gpio62", "gpio63", "gpio68", "gpio69", "gpio126", "gpio129", 1062 + "gpio130", "gpio131", "gpio132", "gpio133", 1063 + }; 1064 + 1065 + static const char *const qlink_big_enable_groups[] = { 1066 + "gpio156", 1067 + }; 1068 + 1069 + static const char *const qlink_big_request_groups[] = { 1070 + "gpio155", 1071 + }; 1072 + 1073 + static const char *const qlink_little_enable_groups[] = { 1074 + "gpio153", 1075 + }; 1076 + 1077 + static const char *const qlink_little_request_groups[] = { 1078 + "gpio152", 1079 + }; 1080 + 1081 + static const char *const qlink_wmss_groups[] = { 1082 + "gpio154", 1083 + }; 1084 + 1085 + static const char *const qspi0_groups[] = { 1086 + "gpio80", 1087 + }; 1088 + 1089 + static const char *const qspi1_groups[] = { 1090 + "gpio147", 1091 + }; 1092 + 1093 + static const char *const qspi2_groups[] = { 1094 + "gpio81", 1095 + }; 1096 + 1097 + static const char *const qspi3_groups[] = { 1098 + "gpio82", 1099 + }; 1100 + 1101 + static const char *const qspi_clk_groups[] = { 1102 + "gpio83", 1103 + }; 1104 + 1105 + static const char *const qspi_cs_groups[] = { 1106 + "gpio146", "gpio148", 1107 + }; 1108 + 1109 + static const char *const qup1_se0_groups[] = { 1110 + "gpio80", "gpio81", "gpio82", "gpio83", 1111 + }; 1112 + 1113 + static const char *const qup1_se1_groups[] = { 1114 + "gpio74", "gpio75", "gpio76", "gpio77", 1115 + }; 1116 + 1117 + static const char *const qup1_se2_groups[] = { 1118 + "gpio40", "gpio41", "gpio42", "gpio43", "gpio130", "gpio131", "gpio132", 1119 + }; 1120 + 1121 + static const char *const qup1_se3_groups[] = { 1122 + "gpio44", "gpio45", "gpio46", "gpio47", 1123 + }; 1124 + 1125 + static const char *const qup1_se4_groups[] = { 1126 + "gpio36", "gpio37", "gpio38", "gpio39", 1127 + }; 1128 + 1129 + static const char *const qup1_se5_groups[] = { 1130 + "gpio52", "gpio53", "gpio54", "gpio55", 1131 + }; 1132 + 1133 + static const char *const qup1_se6_groups[] = { 1134 + "gpio56", "gpio57", "gpio58", "gpio59", 1135 + }; 1136 + 1137 + static const char *const qup1_se7_groups[] = { 1138 + "gpio60", "gpio61", "gpio62", "gpio63", 1139 + }; 1140 + 1141 + static const char *const qup2_se0_groups[] = { 1142 + "gpio0", "gpio1", "gpio2", "gpio3", 1143 + }; 1144 + 1145 + static const char *const qup2_se1_groups[] = { 1146 + "gpio4", "gpio5", "gpio6", "gpio7", 1147 + }; 1148 + 1149 + static const char *const qup2_se2_groups[] = { 1150 + "gpio117", "gpio118", "gpio119", "gpio120", 1151 + }; 1152 + 1153 + static const char *const qup2_se3_groups[] = { 1154 + "gpio122", "gpio123", "gpio124", "gpio125", 1155 + }; 1156 + 1157 + static const char *const qup2_se4_groups[] = { 1158 + "gpio208", "gpio209", 1159 + }; 1160 + 1161 + static const char *const qup3_se0_groups[] = { 1162 + "gpio64", "gpio65", 1163 + }; 1164 + 1165 + static const char *const qup3_se1_groups[] = { 1166 + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio15", 1167 + }; 1168 + 1169 + static const char *const qup3_se2_groups[] = { 1170 + "gpio12", "gpio13", "gpio14", "gpio15", 1171 + }; 1172 + 1173 + static const char *const qup3_se3_groups[] = { 1174 + "gpio16", "gpio17", "gpio18", "gpio19", 1175 + }; 1176 + 1177 + static const char *const qup3_se4_groups[] = { 1178 + "gpio20", "gpio21", "gpio22", "gpio23", 1179 + }; 1180 + 1181 + static const char *const qup3_se5_groups[] = { 1182 + "gpio24", "gpio25", "gpio26", "gpio27", 1183 + }; 1184 + 1185 + static const char *const qup4_se0_groups[] = { 1186 + "gpio48", "gpio49", "gpio50", "gpio51", 1187 + }; 1188 + 1189 + static const char *const qup4_se1_groups[] = { 1190 + "gpio28", "gpio29", "gpio30", "gpio31", 1191 + }; 1192 + 1193 + static const char *const qup4_se2_groups[] = { 1194 + "gpio32", "gpio33", "gpio34", "gpio35", 1195 + }; 1196 + 1197 + static const char *const qup4_se3_groups[] = { 1198 + "gpio84", "gpio121", 1199 + }; 1200 + 1201 + static const char *const qup4_se4_groups[] = { 1202 + "gpio161", "gpio162", 1203 + }; 1204 + 1205 + static const char *const sd_write_protect_groups[] = { 1206 + "gpio85", 1207 + }; 1208 + 1209 + static const char *const sdc40_groups[] = { 1210 + "gpio80", 1211 + }; 1212 + 1213 + static const char *const sdc41_groups[] = { 1214 + "gpio147", 1215 + }; 1216 + 1217 + static const char *const sdc42_groups[] = { 1218 + "gpio81", 1219 + }; 1220 + 1221 + static const char *const sdc43_groups[] = { 1222 + "gpio82", 1223 + }; 1224 + 1225 + static const char *const sdc4_clk_groups[] = { 1226 + "gpio83", 1227 + }; 1228 + 1229 + static const char *const sdc4_cmd_groups[] = { 1230 + "gpio148", 1231 + }; 1232 + 1233 + static const char *const sys_throttle_groups[] = { 1234 + "gpio99", 1235 + }; 1236 + 1237 + static const char *const tb_trig_sdc2_groups[] = { 1238 + "gpio88", 1239 + }; 1240 + 1241 + static const char *const tb_trig_sdc4_groups[] = { 1242 + "gpio146", 1243 + }; 1244 + 1245 + static const char *const tmess_prng0_groups[] = { 1246 + "gpio85", 1247 + }; 1248 + 1249 + static const char *const tmess_prng1_groups[] = { 1250 + "gpio64", 1251 + }; 1252 + 1253 + static const char *const tmess_prng2_groups[] = { 1254 + "gpio65", 1255 + }; 1256 + 1257 + static const char *const tmess_prng3_groups[] = { 1258 + "gpio66", 1259 + }; 1260 + 1261 + static const char *const tsense_pwm1_groups[] = { 1262 + "gpio87", 1263 + }; 1264 + 1265 + static const char *const tsense_pwm2_groups[] = { 1266 + "gpio10", 1267 + }; 1268 + 1269 + static const char *const tsense_pwm3_groups[] = { 1270 + "gpio97", 1271 + }; 1272 + 1273 + static const char *const tsense_pwm4_groups[] = { 1274 + "gpio99", 1275 + }; 1276 + 1277 + static const char *const tsense_pwm5_groups[] = { 1278 + "gpio105", 1279 + }; 1280 + 1281 + static const char *const tsense_pwm6_groups[] = { 1282 + "gpio106", 1283 + }; 1284 + 1285 + static const char *const tsense_pwm7_groups[] = { 1286 + "gpio159", 1287 + }; 1288 + 1289 + static const char *const uim0_clk_groups[] = { 1290 + "gpio127", 1291 + }; 1292 + 1293 + static const char *const uim0_data_groups[] = { 1294 + "gpio126", 1295 + }; 1296 + 1297 + static const char *const uim0_present_groups[] = { 1298 + "gpio129", 1299 + }; 1300 + 1301 + static const char *const uim0_reset_groups[] = { 1302 + "gpio128", 1303 + }; 1304 + 1305 + static const char *const uim1_clk_groups[] = { 1306 + "gpio37", "gpio55", "gpio71", "gpio131", 1307 + }; 1308 + 1309 + static const char *const uim1_data_groups[] = { 1310 + "gpio36", "gpio54", "gpio70", "gpio130", 1311 + }; 1312 + 1313 + static const char *const uim1_present_groups[] = { 1314 + "gpio133", 1315 + }; 1316 + 1317 + static const char *const uim1_reset_groups[] = { 1318 + "gpio39", "gpio56", "gpio72", "gpio132", 1319 + }; 1320 + 1321 + static const char *const usb0_hs_groups[] = { 1322 + "gpio79", 1323 + }; 1324 + 1325 + static const char *const usb_phy_groups[] = { 1326 + "gpio59", "gpio60", 1327 + }; 1328 + 1329 + static const char *const vfr_0_groups[] = { 1330 + "gpio146", 1331 + }; 1332 + 1333 + static const char *const vfr_1_groups[] = { 1334 + "gpio151", 1335 + }; 1336 + 1337 + static const char *const vsense_trigger_mirnat_groups[] = { 1338 + "gpio59", 1339 + }; 1340 + 1341 + static const char *const wcn_sw_groups[] = { 1342 + "gpio19", 1343 + }; 1344 + 1345 + static const char *const wcn_sw_ctrl_groups[] = { 1346 + "gpio18", 1347 + }; 1348 + 1349 + static const struct pinfunction kaanapali_functions[] = { 1350 + MSM_GPIO_PIN_FUNCTION(gpio), 1351 + MSM_PIN_FUNCTION(aoss_cti), 1352 + MSM_PIN_FUNCTION(atest_char), 1353 + MSM_PIN_FUNCTION(atest_usb), 1354 + MSM_PIN_FUNCTION(audio_ext_mclk0), 1355 + MSM_PIN_FUNCTION(audio_ext_mclk1), 1356 + MSM_PIN_FUNCTION(audio_ref_clk), 1357 + MSM_PIN_FUNCTION(cam_asc_mclk2), 1358 + MSM_PIN_FUNCTION(cam_asc_mclk4), 1359 + MSM_PIN_FUNCTION(cam_mclk), 1360 + MSM_PIN_FUNCTION(cci_async_in), 1361 + MSM_PIN_FUNCTION(cci_i2c_scl), 1362 + MSM_PIN_FUNCTION(cci_i2c_sda), 1363 + MSM_PIN_FUNCTION(cci_timer), 1364 + MSM_PIN_FUNCTION(cmu_rng), 1365 + MSM_PIN_FUNCTION(coex_uart1_rx), 1366 + MSM_PIN_FUNCTION(coex_uart1_tx), 1367 + MSM_PIN_FUNCTION(coex_uart2_rx), 1368 + MSM_PIN_FUNCTION(coex_uart2_tx), 1369 + MSM_PIN_FUNCTION(dbg_out_clk), 1370 + MSM_PIN_FUNCTION(ddr_bist_complete), 1371 + MSM_PIN_FUNCTION(ddr_bist_fail), 1372 + MSM_PIN_FUNCTION(ddr_bist_start), 1373 + MSM_PIN_FUNCTION(ddr_bist_stop), 1374 + MSM_PIN_FUNCTION(ddr_pxi0), 1375 + MSM_PIN_FUNCTION(ddr_pxi1), 1376 + MSM_PIN_FUNCTION(ddr_pxi2), 1377 + MSM_PIN_FUNCTION(ddr_pxi3), 1378 + MSM_PIN_FUNCTION(dp_hot), 1379 + MSM_PIN_FUNCTION(egpio), 1380 + MSM_PIN_FUNCTION(gcc_gp1), 1381 + MSM_PIN_FUNCTION(gcc_gp2), 1382 + MSM_PIN_FUNCTION(gcc_gp3), 1383 + MSM_PIN_FUNCTION(gnss_adc0), 1384 + MSM_PIN_FUNCTION(gnss_adc1), 1385 + MSM_PIN_FUNCTION(i2chub0_se0), 1386 + MSM_PIN_FUNCTION(i2chub0_se1), 1387 + MSM_PIN_FUNCTION(i2chub0_se2), 1388 + MSM_PIN_FUNCTION(i2chub0_se3), 1389 + MSM_PIN_FUNCTION(i2chub0_se4), 1390 + MSM_PIN_FUNCTION(i2s0_data0), 1391 + MSM_PIN_FUNCTION(i2s0_data1), 1392 + MSM_PIN_FUNCTION(i2s0_sck), 1393 + MSM_PIN_FUNCTION(i2s0_ws), 1394 + MSM_PIN_FUNCTION(i2s1_data0), 1395 + MSM_PIN_FUNCTION(i2s1_data1), 1396 + MSM_PIN_FUNCTION(i2s1_sck), 1397 + MSM_PIN_FUNCTION(i2s1_ws), 1398 + MSM_PIN_FUNCTION(ibi_i3c), 1399 + MSM_PIN_FUNCTION(jitter_bist), 1400 + MSM_PIN_FUNCTION(mdp_esync0_out), 1401 + MSM_PIN_FUNCTION(mdp_esync1_out), 1402 + MSM_PIN_FUNCTION(mdp_vsync), 1403 + MSM_PIN_FUNCTION(mdp_vsync0_out), 1404 + MSM_PIN_FUNCTION(mdp_vsync1_out), 1405 + MSM_PIN_FUNCTION(mdp_vsync2_out), 1406 + MSM_PIN_FUNCTION(mdp_vsync3_out), 1407 + MSM_PIN_FUNCTION(mdp_vsync5_out), 1408 + MSM_PIN_FUNCTION(mdp_vsync_e), 1409 + MSM_PIN_FUNCTION(nav_gpio0), 1410 + MSM_PIN_FUNCTION(nav_gpio1), 1411 + MSM_PIN_FUNCTION(nav_gpio2), 1412 + MSM_PIN_FUNCTION(nav_gpio3), 1413 + MSM_PIN_FUNCTION(pcie0_clk_req_n), 1414 + MSM_PIN_FUNCTION(phase_flag), 1415 + MSM_PIN_FUNCTION(pll_bist_sync), 1416 + MSM_PIN_FUNCTION(pll_clk_aux), 1417 + MSM_PIN_FUNCTION(prng_rosc0), 1418 + MSM_PIN_FUNCTION(prng_rosc1), 1419 + MSM_PIN_FUNCTION(prng_rosc2), 1420 + MSM_PIN_FUNCTION(prng_rosc3), 1421 + MSM_PIN_FUNCTION(qdss_cti), 1422 + MSM_PIN_FUNCTION(qdss_gpio_traceclk), 1423 + MSM_PIN_FUNCTION(qdss_gpio_tracectl), 1424 + MSM_PIN_FUNCTION(qdss_gpio_tracedata), 1425 + MSM_PIN_FUNCTION(qlink_big_enable), 1426 + MSM_PIN_FUNCTION(qlink_big_request), 1427 + MSM_PIN_FUNCTION(qlink_little_enable), 1428 + MSM_PIN_FUNCTION(qlink_little_request), 1429 + MSM_PIN_FUNCTION(qlink_wmss), 1430 + MSM_PIN_FUNCTION(qspi0), 1431 + MSM_PIN_FUNCTION(qspi1), 1432 + MSM_PIN_FUNCTION(qspi2), 1433 + MSM_PIN_FUNCTION(qspi3), 1434 + MSM_PIN_FUNCTION(qspi_clk), 1435 + MSM_PIN_FUNCTION(qspi_cs), 1436 + MSM_PIN_FUNCTION(qup1_se0), 1437 + MSM_PIN_FUNCTION(qup1_se1), 1438 + MSM_PIN_FUNCTION(qup1_se2), 1439 + MSM_PIN_FUNCTION(qup1_se3), 1440 + MSM_PIN_FUNCTION(qup1_se4), 1441 + MSM_PIN_FUNCTION(qup1_se5), 1442 + MSM_PIN_FUNCTION(qup1_se6), 1443 + MSM_PIN_FUNCTION(qup1_se7), 1444 + MSM_PIN_FUNCTION(qup2_se0), 1445 + MSM_PIN_FUNCTION(qup2_se1), 1446 + MSM_PIN_FUNCTION(qup2_se2), 1447 + MSM_PIN_FUNCTION(qup2_se3), 1448 + MSM_PIN_FUNCTION(qup2_se4), 1449 + MSM_PIN_FUNCTION(qup3_se0), 1450 + MSM_PIN_FUNCTION(qup3_se1), 1451 + MSM_PIN_FUNCTION(qup3_se2), 1452 + MSM_PIN_FUNCTION(qup3_se3), 1453 + MSM_PIN_FUNCTION(qup3_se4), 1454 + MSM_PIN_FUNCTION(qup3_se5), 1455 + MSM_PIN_FUNCTION(qup4_se0), 1456 + MSM_PIN_FUNCTION(qup4_se1), 1457 + MSM_PIN_FUNCTION(qup4_se2), 1458 + MSM_PIN_FUNCTION(qup4_se3), 1459 + MSM_PIN_FUNCTION(qup4_se4), 1460 + MSM_PIN_FUNCTION(sd_write_protect), 1461 + MSM_PIN_FUNCTION(sdc40), 1462 + MSM_PIN_FUNCTION(sdc41), 1463 + MSM_PIN_FUNCTION(sdc42), 1464 + MSM_PIN_FUNCTION(sdc43), 1465 + MSM_PIN_FUNCTION(sdc4_clk), 1466 + MSM_PIN_FUNCTION(sdc4_cmd), 1467 + MSM_PIN_FUNCTION(sys_throttle), 1468 + MSM_PIN_FUNCTION(tb_trig_sdc2), 1469 + MSM_PIN_FUNCTION(tb_trig_sdc4), 1470 + MSM_PIN_FUNCTION(tmess_prng0), 1471 + MSM_PIN_FUNCTION(tmess_prng1), 1472 + MSM_PIN_FUNCTION(tmess_prng2), 1473 + MSM_PIN_FUNCTION(tmess_prng3), 1474 + MSM_PIN_FUNCTION(tsense_pwm1), 1475 + MSM_PIN_FUNCTION(tsense_pwm2), 1476 + MSM_PIN_FUNCTION(tsense_pwm3), 1477 + MSM_PIN_FUNCTION(tsense_pwm4), 1478 + MSM_PIN_FUNCTION(tsense_pwm5), 1479 + MSM_PIN_FUNCTION(tsense_pwm6), 1480 + MSM_PIN_FUNCTION(tsense_pwm7), 1481 + MSM_PIN_FUNCTION(uim0_clk), 1482 + MSM_PIN_FUNCTION(uim0_data), 1483 + MSM_PIN_FUNCTION(uim0_present), 1484 + MSM_PIN_FUNCTION(uim0_reset), 1485 + MSM_PIN_FUNCTION(uim1_clk), 1486 + MSM_PIN_FUNCTION(uim1_data), 1487 + MSM_PIN_FUNCTION(uim1_present), 1488 + MSM_PIN_FUNCTION(uim1_reset), 1489 + MSM_PIN_FUNCTION(usb0_hs), 1490 + MSM_PIN_FUNCTION(usb_phy), 1491 + MSM_PIN_FUNCTION(vfr_0), 1492 + MSM_PIN_FUNCTION(vfr_1), 1493 + MSM_PIN_FUNCTION(vsense_trigger_mirnat), 1494 + MSM_PIN_FUNCTION(wcn_sw), 1495 + MSM_PIN_FUNCTION(wcn_sw_ctrl), 1496 + }; 1497 + 1498 + /* Every pin is maintained as a single group, and missing or non-existing pin 1499 + * would be maintained as dummy group to synchronize pin group index with 1500 + * pin descriptor registered with pinctrl core. 1501 + * Clients would not be able to request these dummy pin groups. 1502 + */ 1503 + static const struct msm_pingroup kaanapali_groups[] = { 1504 + [0] = PINGROUP(0, qup2_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio), 1505 + [1] = PINGROUP(1, qup2_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio), 1506 + [2] = PINGROUP(2, qup2_se0, _, _, _, _, _, _, _, _, _, egpio), 1507 + [3] = PINGROUP(3, qup2_se0, _, _, _, _, _, _, _, _, _, egpio), 1508 + [4] = PINGROUP(4, qup2_se1, ibi_i3c, _, _, _, _, _, _, _, _, egpio), 1509 + [5] = PINGROUP(5, qup2_se1, ibi_i3c, _, _, _, _, _, _, _, _, egpio), 1510 + [6] = PINGROUP(6, qup2_se1, _, _, _, _, _, _, _, _, _, egpio), 1511 + [7] = PINGROUP(7, qup2_se1, _, _, _, _, _, _, _, _, _, egpio), 1512 + [8] = PINGROUP(8, qup3_se1, ibi_i3c, _, _, _, _, _, _, _, _, _), 1513 + [9] = PINGROUP(9, qup3_se1, ibi_i3c, _, _, _, _, _, _, _, _, _), 1514 + [10] = PINGROUP(10, qup3_se1, cci_async_in, _, tsense_pwm2, _, _, _, _, _, _, _), 1515 + [11] = PINGROUP(11, qup3_se1, cci_async_in, _, _, _, _, _, _, _, _, _), 1516 + [12] = PINGROUP(12, qup3_se2, ibi_i3c, qup3_se1, _, _, _, _, _, _, _, _), 1517 + [13] = PINGROUP(13, qup3_se2, ibi_i3c, qup3_se1, _, _, _, _, _, _, _, _), 1518 + [14] = PINGROUP(14, qup3_se2, _, _, _, _, _, _, _, _, _, _), 1519 + [15] = PINGROUP(15, qup3_se2, cci_async_in, qup3_se1, _, _, _, _, _, _, _, _), 1520 + [16] = PINGROUP(16, qup3_se3, _, _, _, _, _, _, _, _, _, _), 1521 + [17] = PINGROUP(17, qup3_se3, _, _, _, _, _, _, _, _, _, _), 1522 + [18] = PINGROUP(18, wcn_sw_ctrl, qup3_se3, _, _, _, _, _, _, _, _, _), 1523 + [19] = PINGROUP(19, wcn_sw, qup3_se3, _, _, _, _, _, _, _, _, _), 1524 + [20] = PINGROUP(20, qup3_se4, _, _, _, _, _, _, _, _, _, _), 1525 + [21] = PINGROUP(21, qup3_se4, _, _, _, _, _, _, _, _, _, _), 1526 + [22] = PINGROUP(22, qup3_se4, _, _, _, _, _, _, _, _, _, _), 1527 + [23] = PINGROUP(23, qup3_se4, _, _, _, _, _, _, _, _, _, _), 1528 + [24] = PINGROUP(24, qup3_se5, _, _, _, _, _, _, _, _, _, _), 1529 + [25] = PINGROUP(25, qup3_se5, _, _, _, _, _, _, _, _, _, _), 1530 + [26] = PINGROUP(26, qup3_se5, _, _, _, _, _, _, _, _, _, _), 1531 + [27] = PINGROUP(27, qup3_se5, qdss_cti, _, _, _, _, _, _, _, _, _), 1532 + [28] = PINGROUP(28, qup4_se1, ibi_i3c, _, _, _, _, _, _, _, _, egpio), 1533 + [29] = PINGROUP(29, qup4_se1, ibi_i3c, _, _, _, _, _, _, _, _, egpio), 1534 + [30] = PINGROUP(30, qup4_se1, _, _, _, _, _, _, _, _, _, _), 1535 + [31] = PINGROUP(31, qup4_se1, qdss_cti, _, _, _, _, _, _, _, _, _), 1536 + [32] = PINGROUP(32, qup4_se2, ibi_i3c, _, _, _, _, _, _, _, _, _), 1537 + [33] = PINGROUP(33, qup4_se2, ibi_i3c, _, _, _, _, _, _, _, _, _), 1538 + [34] = PINGROUP(34, qup4_se2, _, _, _, _, _, _, _, _, _, _), 1539 + [35] = PINGROUP(35, qup4_se2, _, _, _, _, _, _, _, _, _, _), 1540 + [36] = PINGROUP(36, qup1_se4, uim1_data, ibi_i3c, _, _, _, _, _, _, _, _), 1541 + [37] = PINGROUP(37, qup1_se4, uim1_clk, ibi_i3c, _, _, _, _, _, _, _, _), 1542 + [38] = PINGROUP(38, qup1_se4, qdss_gpio_tracedata, _, _, _, _, _, _, _, _, _), 1543 + [39] = PINGROUP(39, qup1_se4, uim1_reset, qdss_gpio_tracedata, _, _, _, _, _, _, _, _), 1544 + [40] = PINGROUP(40, qup1_se2, cmu_rng, ddr_bist_fail, _, qdss_gpio_tracedata, gnss_adc0, 1545 + _, _, _, _, _), 1546 + [41] = PINGROUP(41, qup1_se2, cmu_rng, ddr_bist_start, _, qdss_gpio_tracedata, gnss_adc0, 1547 + _, _, _, _, _), 1548 + [42] = PINGROUP(42, qup1_se2, cmu_rng, dbg_out_clk, qdss_gpio_tracedata, gnss_adc1, _, _, 1549 + _, _, _, _), 1550 + [43] = PINGROUP(43, qup1_se2, cmu_rng, _, qdss_gpio_tracedata, ddr_pxi2, _, _, _, _, _, _), 1551 + [44] = PINGROUP(44, qup1_se3, ddr_bist_complete, ddr_pxi1, _, _, _, _, _, _, _, _), 1552 + [45] = PINGROUP(45, qup1_se3, ddr_bist_stop, ddr_pxi1, _, _, _, _, _, _, _, _), 1553 + [46] = PINGROUP(46, qup1_se3, ddr_pxi3, _, _, _, _, _, _, _, _, _), 1554 + [47] = PINGROUP(47, qup1_se3, dp_hot, _, _, _, _, _, _, _, _, _), 1555 + [48] = PINGROUP(48, qup4_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio), 1556 + [49] = PINGROUP(49, qup4_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio), 1557 + [50] = PINGROUP(50, qup4_se0, _, _, _, _, _, _, _, _, _, egpio), 1558 + [51] = PINGROUP(51, qup4_se0, _, _, _, _, _, _, _, _, _, egpio), 1559 + [52] = PINGROUP(52, qup1_se5, ddr_pxi2, _, _, _, _, _, _, _, _, _), 1560 + [53] = PINGROUP(53, qup1_se5, _, ddr_pxi3, _, _, _, _, _, _, _, _), 1561 + [54] = PINGROUP(54, qup1_se5, uim1_data, ddr_pxi0, _, _, _, _, _, _, _, _), 1562 + [55] = PINGROUP(55, qup1_se5, uim1_clk, ddr_pxi0, _, _, _, _, _, _, _, _), 1563 + [56] = PINGROUP(56, qup1_se6, uim1_reset, _, _, _, _, _, _, _, _, _), 1564 + [57] = PINGROUP(57, qup1_se6, _, _, _, _, _, _, _, _, _, _), 1565 + [58] = PINGROUP(58, qup1_se6, _, _, _, _, _, _, _, _, _, _), 1566 + [59] = PINGROUP(59, qup1_se6, usb_phy, vsense_trigger_mirnat, _, _, _, _, _, _, _, _), 1567 + [60] = PINGROUP(60, qup1_se7, usb_phy, ibi_i3c, _, _, _, _, _, _, _, _), 1568 + [61] = PINGROUP(61, qup1_se7, ibi_i3c, _, _, _, _, _, _, _, _, _), 1569 + [62] = PINGROUP(62, qup1_se7, qdss_gpio_tracedata, _, _, _, _, _, _, _, _, _), 1570 + [63] = PINGROUP(63, qup1_se7, qdss_gpio_tracedata, _, _, _, _, _, _, _, _, _), 1571 + [64] = PINGROUP(64, qup3_se0, _, prng_rosc1, tmess_prng1, _, _, _, _, _, _, _), 1572 + [65] = PINGROUP(65, qup3_se0, _, prng_rosc2, tmess_prng2, _, _, _, _, _, _, _), 1573 + [66] = PINGROUP(66, i2chub0_se0, prng_rosc3, tmess_prng3, _, _, _, _, _, _, _, _), 1574 + [67] = PINGROUP(67, i2chub0_se0, _, _, _, _, _, _, _, _, _, _), 1575 + [68] = PINGROUP(68, i2chub0_se2, qdss_gpio_tracedata, _, _, _, _, _, _, _, _, _), 1576 + [69] = PINGROUP(69, i2chub0_se2, qdss_gpio_tracedata, _, _, _, _, _, _, _, _, _), 1577 + [70] = PINGROUP(70, i2chub0_se3, uim1_data, _, atest_usb, _, _, _, _, _, _, _), 1578 + [71] = PINGROUP(71, i2chub0_se3, uim1_clk, _, atest_usb, _, _, _, _, _, _, _), 1579 + [72] = PINGROUP(72, i2chub0_se4, uim1_reset, qdss_cti, _, atest_usb, _, _, _, _, _, _), 1580 + [73] = PINGROUP(73, i2chub0_se4, qdss_cti, jitter_bist, atest_usb, _, _, _, _, _, _, _), 1581 + [74] = PINGROUP(74, qup1_se1, aoss_cti, _, _, _, _, _, _, _, _, _), 1582 + [75] = PINGROUP(75, qup1_se1, aoss_cti, _, _, _, _, _, _, _, _, _), 1583 + [76] = PINGROUP(76, qup1_se1, aoss_cti, _, _, _, _, _, _, _, _, _), 1584 + [77] = PINGROUP(77, qup1_se1, aoss_cti, gnss_adc1, _, _, _, _, _, _, _, _), 1585 + [78] = PINGROUP(78, i2chub0_se1, _, _, _, _, _, _, _, _, _, _), 1586 + [79] = PINGROUP(79, i2chub0_se1, usb0_hs, _, _, _, _, _, _, _, _, _), 1587 + [80] = PINGROUP(80, qup1_se0, sdc40, qspi0, _, _, _, _, _, _, _, _), 1588 + [81] = PINGROUP(81, qup1_se0, sdc42, qspi2, _, _, _, _, _, _, _, _), 1589 + [82] = PINGROUP(82, qup1_se0, sdc43, qdss_cti, qspi3, _, _, _, _, _, _, _), 1590 + [83] = PINGROUP(83, qup1_se0, sdc4_clk, qdss_cti, qspi_clk, _, _, _, _, _, _, _), 1591 + [84] = PINGROUP(84, qup4_se3, _, _, _, _, _, _, _, _, _, _), 1592 + [85] = PINGROUP(85, sd_write_protect, prng_rosc0, tmess_prng0, _, _, _, _, _, _, _, _), 1593 + [86] = PINGROUP(86, mdp_vsync, mdp_vsync0_out, mdp_vsync1_out, gcc_gp2, _, _, _, _, _, _, 1594 + _), 1595 + [87] = PINGROUP(87, mdp_vsync, mdp_vsync2_out, mdp_vsync3_out, mdp_vsync5_out, gcc_gp3, _, 1596 + tsense_pwm1, _, _, _, _), 1597 + [88] = PINGROUP(88, mdp_vsync_e, mdp_esync0_out, tb_trig_sdc2, _, _, _, _, _, _, _, _), 1598 + [89] = PINGROUP(89, cam_mclk, _, _, _, _, _, _, _, _, _, _), 1599 + [90] = PINGROUP(90, cam_mclk, _, _, _, _, _, _, _, _, _, _), 1600 + [91] = PINGROUP(91, cam_asc_mclk2, _, _, _, _, _, _, _, _, _, _), 1601 + [92] = PINGROUP(92, cam_mclk, _, _, _, _, _, _, _, _, _, _), 1602 + [93] = PINGROUP(93, cam_asc_mclk4, _, _, _, _, _, _, _, _, _, _), 1603 + [94] = PINGROUP(94, cam_mclk, pll_clk_aux, _, _, _, _, _, _, _, _, _), 1604 + [95] = PINGROUP(95, cam_mclk, _, _, _, _, _, _, _, _, _, _), 1605 + [96] = PINGROUP(96, cam_mclk, _, _, _, _, _, _, _, _, _, _), 1606 + [97] = PINGROUP(97, mdp_vsync, tsense_pwm3, _, _, _, _, _, _, _, _, _), 1607 + [98] = PINGROUP(98, mdp_vsync, _, _, _, _, _, _, _, _, _, _), 1608 + [99] = PINGROUP(99, sys_throttle, tsense_pwm4, _, _, _, _, _, _, _, _, _), 1609 + [100] = PINGROUP(100, mdp_esync1_out, _, _, _, _, _, _, _, _, _, _), 1610 + [101] = PINGROUP(101, _, _, _, _, _, _, _, _, _, _, _), 1611 + [102] = PINGROUP(102, _, _, _, _, _, _, _, _, _, _, _), 1612 + [103] = PINGROUP(103, pcie0_clk_req_n, _, _, _, _, _, _, _, _, _, _), 1613 + [104] = PINGROUP(104, pll_bist_sync, _, _, _, _, _, _, _, _, _, _), 1614 + [105] = PINGROUP(105, cci_timer, tsense_pwm5, _, _, _, _, _, _, _, _, _), 1615 + [106] = PINGROUP(106, cci_timer, tsense_pwm6, _, _, _, _, _, _, _, _, _), 1616 + [107] = PINGROUP(107, cci_timer, cci_i2c_sda, _, _, _, _, _, _, _, _, _), 1617 + [108] = PINGROUP(108, cci_i2c_sda, _, _, _, _, _, _, _, _, _, _), 1618 + [109] = PINGROUP(109, cci_i2c_sda, _, _, _, _, _, _, _, _, _, _), 1619 + [110] = PINGROUP(110, cci_i2c_scl, _, _, _, _, _, _, _, _, _, _), 1620 + [111] = PINGROUP(111, cci_i2c_sda, _, _, _, _, _, _, _, _, _, _), 1621 + [112] = PINGROUP(112, cci_i2c_scl, _, _, _, _, _, _, _, _, _, _), 1622 + [113] = PINGROUP(113, cci_i2c_sda, _, _, _, _, _, _, _, _, _, _), 1623 + [114] = PINGROUP(114, cci_i2c_scl, _, _, _, _, _, _, _, _, _, _), 1624 + [115] = PINGROUP(115, cci_i2c_sda, _, _, _, _, _, _, _, _, _, _), 1625 + [116] = PINGROUP(116, cci_i2c_scl, _, _, _, _, _, _, _, _, _, _), 1626 + [117] = PINGROUP(117, i2s1_sck, qup2_se2, phase_flag, _, _, _, _, _, _, _, _), 1627 + [118] = PINGROUP(118, i2s1_data0, qup2_se2, phase_flag, _, _, _, _, _, _, _, _), 1628 + [119] = PINGROUP(119, i2s1_ws, qup2_se2, phase_flag, _, _, _, _, _, _, _, _), 1629 + [120] = PINGROUP(120, i2s1_data1, qup2_se2, audio_ext_mclk1, audio_ref_clk, _, _, _, _, _, 1630 + _, _), 1631 + [121] = PINGROUP(121, audio_ext_mclk0, qup4_se3, _, _, _, _, _, _, _, _, _), 1632 + [122] = PINGROUP(122, i2s0_sck, qup2_se3, _, _, _, _, _, _, _, _, _), 1633 + [123] = PINGROUP(123, i2s0_data0, qup2_se3, _, phase_flag, _, _, _, _, _, _, _), 1634 + [124] = PINGROUP(124, i2s0_data1, qup2_se3, _, phase_flag, _, _, _, _, _, _, _), 1635 + [125] = PINGROUP(125, i2s0_ws, qup2_se3, phase_flag, _, _, _, _, _, _, _, _), 1636 + [126] = PINGROUP(126, uim0_data, qdss_gpio_tracedata, atest_char, _, _, _, _, _, _, _, _), 1637 + [127] = PINGROUP(127, uim0_clk, qdss_gpio_tracectl, atest_char, _, _, _, _, _, _, _, _), 1638 + [128] = PINGROUP(128, uim0_reset, qdss_gpio_traceclk, atest_char, _, _, _, _, _, _, _, _), 1639 + [129] = PINGROUP(129, uim0_present, qdss_gpio_tracedata, atest_usb, atest_char, _, _, _, _, 1640 + _, _, _), 1641 + [130] = PINGROUP(130, uim1_data, qup1_se2, gcc_gp1, qdss_gpio_tracedata, _, _, _, _, _, _, 1642 + _), 1643 + [131] = PINGROUP(131, uim1_clk, qup1_se2, gcc_gp2, qdss_gpio_tracedata, _, _, _, _, _, _, 1644 + _), 1645 + [132] = PINGROUP(132, uim1_reset, qup1_se2, gcc_gp3, qdss_gpio_tracedata, _, _, _, _, _, _, 1646 + _), 1647 + [133] = PINGROUP(133, uim1_present, qdss_gpio_tracedata, atest_char, _, _, _, _, _, _, _, 1648 + _), 1649 + [134] = PINGROUP(134, _, _, _, _, _, _, _, _, _, _, _), 1650 + [135] = PINGROUP(135, _, _, _, _, _, _, _, _, _, _, _), 1651 + [136] = PINGROUP(136, _, _, _, _, _, _, _, _, _, _, _), 1652 + [137] = PINGROUP(137, _, _, _, _, _, _, _, _, _, _, _), 1653 + [138] = PINGROUP(138, _, _, _, _, _, _, _, _, _, _, _), 1654 + [139] = PINGROUP(139, _, _, _, _, _, _, _, _, _, _, _), 1655 + [140] = PINGROUP(140, _, _, _, _, _, _, _, _, _, _, _), 1656 + [141] = PINGROUP(141, _, _, _, _, _, _, _, _, _, _, _), 1657 + [142] = PINGROUP(142, _, _, _, _, _, _, _, _, _, _, _), 1658 + [143] = PINGROUP(143, _, _, _, _, _, _, _, _, _, _, _), 1659 + [144] = PINGROUP(144, coex_uart1_rx, cmu_rng, _, _, _, _, _, _, _, _, _), 1660 + [145] = PINGROUP(145, coex_uart1_tx, cmu_rng, _, _, _, _, _, _, _, _, _), 1661 + [146] = PINGROUP(146, _, vfr_0, coex_uart2_rx, cmu_rng, tb_trig_sdc4, qspi_cs, _, _, _, _, 1662 + _), 1663 + [147] = PINGROUP(147, _, coex_uart2_tx, cmu_rng, sdc41, qspi1, _, _, _, _, _, _), 1664 + [148] = PINGROUP(148, nav_gpio2, _, sdc4_cmd, qspi_cs, _, _, _, _, _, _, _), 1665 + [149] = PINGROUP(149, cci_i2c_scl, _, _, _, _, _, _, _, _, _, _), 1666 + [150] = PINGROUP(150, nav_gpio0, nav_gpio3, _, _, _, _, _, _, _, _, _), 1667 + [151] = PINGROUP(151, nav_gpio1, vfr_1, _, _, _, _, _, _, _, _, _), 1668 + [152] = PINGROUP(152, qlink_little_request, _, _, _, _, _, _, _, _, _, _), 1669 + [153] = PINGROUP(153, qlink_little_enable, _, _, _, _, _, _, _, _, _, _), 1670 + [154] = PINGROUP(154, qlink_wmss, _, _, _, _, _, _, _, _, _, _), 1671 + [155] = PINGROUP(155, qlink_big_request, qdss_cti, _, _, _, _, _, _, _, _, _), 1672 + [156] = PINGROUP(156, qlink_big_enable, _, _, _, _, _, _, _, _, _, _), 1673 + [157] = PINGROUP(157, _, _, _, _, _, _, _, _, _, _, _), 1674 + [158] = PINGROUP(158, qdss_cti, gcc_gp1, _, _, _, _, _, _, _, _, _), 1675 + [159] = PINGROUP(159, cci_timer, tsense_pwm7, _, _, _, _, _, _, _, _, _), 1676 + [160] = PINGROUP(160, cci_timer, cci_i2c_scl, _, _, _, _, _, _, _, _, _), 1677 + [161] = PINGROUP(161, qup4_se4, _, _, _, _, _, _, _, _, _, _), 1678 + [162] = PINGROUP(162, qup4_se4, _, _, _, _, _, _, _, _, _, _), 1679 + [163] = PINGROUP(163, _, _, _, _, _, _, _, _, _, _, egpio), 1680 + [164] = PINGROUP(164, _, _, _, _, _, _, _, _, _, _, egpio), 1681 + [165] = PINGROUP(165, _, _, _, _, _, _, _, _, _, _, egpio), 1682 + [166] = PINGROUP(166, _, _, _, _, _, _, _, _, _, _, egpio), 1683 + [167] = PINGROUP(167, _, _, _, _, _, _, _, _, _, _, egpio), 1684 + [168] = PINGROUP(168, _, _, _, _, _, _, _, _, _, _, egpio), 1685 + [169] = PINGROUP(169, phase_flag, _, _, _, _, _, _, _, _, _, egpio), 1686 + [170] = PINGROUP(170, phase_flag, _, _, _, _, _, _, _, _, _, egpio), 1687 + [171] = PINGROUP(171, phase_flag, _, _, _, _, _, _, _, _, _, egpio), 1688 + [172] = PINGROUP(172, phase_flag, _, _, _, _, _, _, _, _, _, egpio), 1689 + [173] = PINGROUP(173, phase_flag, _, _, _, _, _, _, _, _, _, egpio), 1690 + [174] = PINGROUP(174, _, _, _, _, _, _, _, _, _, _, egpio), 1691 + [175] = PINGROUP(175, phase_flag, _, _, _, _, _, _, _, _, _, egpio), 1692 + [176] = PINGROUP(176, phase_flag, _, _, _, _, _, _, _, _, _, egpio), 1693 + [177] = PINGROUP(177, _, _, _, _, _, _, _, _, _, _, egpio), 1694 + [178] = PINGROUP(178, _, _, _, _, _, _, _, _, _, _, egpio), 1695 + [179] = PINGROUP(179, phase_flag, _, _, _, _, _, _, _, _, _, egpio), 1696 + [180] = PINGROUP(180, phase_flag, _, _, _, _, _, _, _, _, _, egpio), 1697 + [181] = PINGROUP(181, phase_flag, _, _, _, _, _, _, _, _, _, egpio), 1698 + [182] = PINGROUP(182, _, _, _, _, _, _, _, _, _, _, egpio), 1699 + [183] = PINGROUP(183, _, _, _, _, _, _, _, _, _, _, egpio), 1700 + [184] = PINGROUP(184, phase_flag, _, _, _, _, _, _, _, _, _, egpio), 1701 + [185] = PINGROUP(185, phase_flag, _, _, _, _, _, _, _, _, _, egpio), 1702 + [186] = PINGROUP(186, _, _, _, _, _, _, _, _, _, _, egpio), 1703 + [187] = PINGROUP(187, _, _, _, _, _, _, _, _, _, _, egpio), 1704 + [188] = PINGROUP(188, _, _, _, _, _, _, _, _, _, _, egpio), 1705 + [189] = PINGROUP(189, _, _, _, _, _, _, _, _, _, _, egpio), 1706 + [190] = PINGROUP(190, _, _, _, _, _, _, _, _, _, _, egpio), 1707 + [191] = PINGROUP(191, _, _, _, _, _, _, _, _, _, _, egpio), 1708 + [192] = PINGROUP(192, phase_flag, _, _, _, _, _, _, _, _, _, egpio), 1709 + [193] = PINGROUP(193, _, _, _, _, _, _, _, _, _, _, egpio), 1710 + [194] = PINGROUP(194, _, _, _, _, _, _, _, _, _, _, egpio), 1711 + [195] = PINGROUP(195, _, _, _, _, _, _, _, _, _, _, egpio), 1712 + [196] = PINGROUP(196, phase_flag, _, _, _, _, _, _, _, _, _, egpio), 1713 + [197] = PINGROUP(197, phase_flag, _, _, _, _, _, _, _, _, _, egpio), 1714 + [198] = PINGROUP(198, phase_flag, _, _, _, _, _, _, _, _, _, egpio), 1715 + [199] = PINGROUP(199, phase_flag, _, _, _, _, _, _, _, _, _, egpio), 1716 + [200] = PINGROUP(200, _, _, _, _, _, _, _, _, _, _, egpio), 1717 + [201] = PINGROUP(201, _, _, _, _, _, _, _, _, _, _, egpio), 1718 + [202] = PINGROUP(202, _, _, _, _, _, _, _, _, _, _, egpio), 1719 + [203] = PINGROUP(203, _, _, _, _, _, _, _, _, _, _, egpio), 1720 + [204] = PINGROUP(204, phase_flag, _, _, _, _, _, _, _, _, _, egpio), 1721 + [205] = PINGROUP(205, _, _, _, _, _, _, _, _, _, _, egpio), 1722 + [206] = PINGROUP(206, phase_flag, _, _, _, _, _, _, _, _, _, egpio), 1723 + [207] = PINGROUP(207, phase_flag, _, _, _, _, _, _, _, _, _, egpio), 1724 + [208] = PINGROUP(208, qup2_se4, _, phase_flag, _, _, _, _, _, _, _, egpio), 1725 + [209] = PINGROUP(209, qup2_se4, _, _, _, _, _, _, _, _, _, egpio), 1726 + [210] = PINGROUP(210, phase_flag, _, _, _, _, _, _, _, _, _, egpio), 1727 + [211] = PINGROUP(211, phase_flag, _, _, _, _, _, _, _, _, _, egpio), 1728 + [212] = PINGROUP(212, _, _, _, _, _, _, _, _, _, _, egpio), 1729 + [213] = PINGROUP(213, _, _, _, _, _, _, _, _, _, _, egpio), 1730 + [214] = PINGROUP(214, phase_flag, _, _, _, _, _, _, _, _, _, egpio), 1731 + [215] = PINGROUP(215, phase_flag, _, _, _, _, _, _, _, _, _, egpio), 1732 + [216] = PINGROUP(216, phase_flag, _, _, _, _, _, _, _, _, _, egpio), 1733 + [217] = UFS_RESET(ufs_reset, 0xe8004, 0xe9000), 1734 + [218] = SDC_QDSD_PINGROUP(sdc2_clk, 0xdd000, 14, 6), 1735 + [219] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xdd000, 11, 3), 1736 + [220] = SDC_QDSD_PINGROUP(sdc2_data, 0xdd000, 9, 0), 1737 + }; 1738 + 1739 + static const struct msm_gpio_wakeirq_map kaanapali_pdc_map[] = { 1740 + { 0, 89 }, { 3, 97 }, { 4, 90 }, { 7, 91 }, { 8, 92 }, { 11, 93 }, 1741 + { 12, 101 }, { 15, 115 }, { 17, 125 }, { 18, 127 }, { 19, 96 }, { 23, 99 }, 1742 + { 24, 100 }, { 27, 102 }, { 28, 103 }, { 31, 111 }, { 32, 109 }, { 35, 85 }, 1743 + { 36, 110 }, { 39, 112 }, { 43, 113 }, { 47, 138 }, { 48, 114 }, { 51, 98 }, 1744 + { 55, 88 }, { 57, 120 }, { 59, 121 }, { 60, 122 }, { 63, 108 }, { 64, 94 }, 1745 + { 65, 107 }, { 67, 116 }, { 68, 129 }, { 69, 130 }, { 75, 135 }, { 77, 123 }, 1746 + { 78, 119 }, { 79, 131 }, { 80, 139 }, { 81, 132 }, { 84, 118 }, { 85, 133 }, 1747 + { 86, 140 }, { 87, 141 }, { 88, 142 }, { 95, 143 }, { 96, 144 }, { 97, 117 }, 1748 + { 98, 134 }, { 99, 95 }, { 101, 145 }, { 102, 146 }, { 103, 147 }, { 104, 148 }, 1749 + { 120, 149 }, { 125, 150 }, { 129, 137 }, { 133, 84 }, { 144, 151 }, { 146, 152 }, 1750 + { 151, 153 }, { 152, 154 }, { 155, 106 }, { 158, 104 }, { 162, 126 }, { 164, 155 }, 1751 + { 167, 156 }, { 169, 157 }, { 170, 158 }, { 172, 159 }, { 174, 160 }, { 175, 161 }, 1752 + { 179, 162 }, { 180, 163 }, { 183, 164 }, { 186, 165 }, { 188, 128 }, { 189, 166 }, 1753 + { 190, 105 }, { 191, 167 }, { 194, 168 }, { 195, 169 }, { 196, 170 }, { 197, 171 }, 1754 + { 199, 136 }, { 200, 86 }, { 201, 172 }, { 202, 173 }, { 203, 174 }, { 205, 124 }, 1755 + { 209, 175 }, { 213, 87 }, { 216, 176 }, 1756 + }; 1757 + 1758 + static const struct msm_pinctrl_soc_data kaanapali_tlmm = { 1759 + .pins = kaanapali_pins, 1760 + .npins = ARRAY_SIZE(kaanapali_pins), 1761 + .functions = kaanapali_functions, 1762 + .nfunctions = ARRAY_SIZE(kaanapali_functions), 1763 + .groups = kaanapali_groups, 1764 + .ngroups = ARRAY_SIZE(kaanapali_groups), 1765 + .ngpios = 218, 1766 + .wakeirq_map = kaanapali_pdc_map, 1767 + .nwakeirq_map = ARRAY_SIZE(kaanapali_pdc_map), 1768 + .egpio_func = 11, 1769 + }; 1770 + 1771 + static int kaanapali_tlmm_probe(struct platform_device *pdev) 1772 + { 1773 + return msm_pinctrl_probe(pdev, &kaanapali_tlmm); 1774 + } 1775 + 1776 + static const struct of_device_id kaanapali_tlmm_of_match[] = { 1777 + { .compatible = "qcom,kaanapali-tlmm",}, 1778 + {}, 1779 + }; 1780 + 1781 + static struct platform_driver kaanapali_tlmm_driver = { 1782 + .driver = { 1783 + .name = "kaanapali-tlmm", 1784 + .of_match_table = kaanapali_tlmm_of_match, 1785 + }, 1786 + .probe = kaanapali_tlmm_probe, 1787 + }; 1788 + 1789 + static int __init kaanapali_tlmm_init(void) 1790 + { 1791 + return platform_driver_register(&kaanapali_tlmm_driver); 1792 + } 1793 + arch_initcall(kaanapali_tlmm_init); 1794 + 1795 + static void __exit kaanapali_tlmm_exit(void) 1796 + { 1797 + platform_driver_unregister(&kaanapali_tlmm_driver); 1798 + } 1799 + module_exit(kaanapali_tlmm_exit); 1800 + 1801 + MODULE_DESCRIPTION("QTI Kaanapali TLMM driver"); 1802 + MODULE_LICENSE("GPL"); 1803 + MODULE_DEVICE_TABLE(of, kaanapali_tlmm_of_match);