Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clocksource/drivers/vf-pit: Rework the base address usage
This change passes the base address to the clockevent and clocksource
initialization functions in order to use different base address in the
next changes.
No functional changes intended.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20250804152344.1109310-5-daniel.lezcano@linaro.org
+22
-13
+22
-13
drivers/clocksource/timer-vf-pit.c
+22
-13
drivers/clocksource/timer-vf-pit.c
···
66
66
return ~readl(clksrc_base + PITCVAL);
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}
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68
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-
static int __init pit_clocksource_init(struct pit_timer *pit, unsigned long rate)
69
+
static int __init pit_clocksource_init(struct pit_timer *pit, void __iomem *base,
70
+
unsigned long rate)
70
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{
72
+
/*
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+
* The channels 0 and 1 can be chained to build a 64-bit
74
+
* timer. Let's use the channel 2 as a clocksource and leave
75
+
* the channels 0 and 1 unused for anyone else who needs them
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+
*/
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+
pit->clksrc_base = base + PIT_CH(2);
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+
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/* set the max load value and start the clock source counter */
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writel(0, pit->clksrc_base + PITTCTRL);
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writel(~0, pit->clksrc_base + PITLDVAL);
···
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clksrc_base = pit->clksrc_base;
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sched_clock_register(pit_read_sched_clock, 32, rate);
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+
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return clocksource_mmio_init(pit->clksrc_base + PITCVAL, "vf-pit", rate,
88
-
300, 32, clocksource_mmio_readl_down);
81
+
300, 32, clocksource_mmio_readl_down);
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}
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static int pit_set_next_event(unsigned long delta, struct clock_event_device *ced)
···
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return IRQ_HANDLED;
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}
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-
static int __init pit_clockevent_init(struct pit_timer *pit, unsigned long rate, int irq)
140
+
static int __init pit_clockevent_init(struct pit_timer *pit, void __iomem *base,
141
+
unsigned long rate, int irq)
150
142
{
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+
/*
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+
* The channels 0 and 1 can be chained to build a 64-bit
145
+
* timer. Let's use the channel 3 as a clockevent and leave
146
+
* the channels 0 and 1 unused for anyone else who needs them
147
+
*/
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+
pit->clkevt_base = base + PIT_CH(3);
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+
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writel(0, pit->clkevt_base + PITTCTRL);
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151
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writel(PITTFLG_TIF, pit->clkevt_base + PITTFLG);
···
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182
return -ENXIO;
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}
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-
/*
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-
* PIT0 and PIT1 can be chained to build a 64-bit timer,
204
-
* so choose PIT2 as clocksource, PIT3 as clockevent device,
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-
* and leave PIT0 and PIT1 unused for anyone else who needs them.
206
-
*/
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-
pit_timer.clksrc_base = timer_base + PIT_CH(2);
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-
pit_timer.clkevt_base = timer_base + PIT_CH(3);
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-
210
185
irq = irq_of_parse_and_map(np, 0);
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if (irq <= 0)
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return -EINVAL;
···
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/* enable the pit module */
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writel(~PITMCR_MDIS, timer_base + PITMCR);
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210
220
-
ret = pit_clocksource_init(&pit_timer, clk_rate);
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+
ret = pit_clocksource_init(&pit_timer, timer_base, clk_rate);
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if (ret)
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return ret;
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-
return pit_clockevent_init(&pit_timer, clk_rate, irq);
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+
return pit_clockevent_init(&pit_timer, timer_base, clk_rate, irq);
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}
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TIMER_OF_DECLARE(vf610, "fsl,vf610-pit", pit_timer_init);