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MIPS: Add Mobileye EyeQ6Lplus SoC dtsi
Add the device tree include files for the EyeQ6Lplus system on chip
from Mobileye.
Those files provide the initial support of the SoC:
* The I6500 CPU and GIC interrupt controller.
* The OLB ("Other Logic Block") providing clocks, resets and pin controls.
* One UART.
* One GPIO controller.
* Two SPI controllers, one in host mode and one in target mode.
* One octoSPI flash controller.
* Two I2C controllers.
Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
authored by
Benoît Monin
and committed by
Thomas Bogendoerfer
361600d1
4eb9ed39
+254
+84
arch/mips/boot/dts/mobileye/eyeq6lplus-pins.dtsi
+84
arch/mips/boot/dts/mobileye/eyeq6lplus-pins.dtsi
···
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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&olb {
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timer0_pins: timer0-pins {
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function = "timer0";
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pins = "PA0", "PA1";
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};
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timer1_pins: timer1-pins {
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function = "timer1";
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pins = "PA2", "PA3";
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};
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uart_ssi_pins: uart-ssi-pins {
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function = "uart_ssi";
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pins = "PA4", "PA5";
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};
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spi0_pins: spi0-pins {
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function = "spi0";
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pins = "PA6", "PA7", "PA8", "PA9";
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};
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uart0_pins: uart0-pins {
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function = "uart0";
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pins = "PA11", "PA12";
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};
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timer2_pins: timer2-pins {
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function = "timer2";
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pins = "PA13", "PA14";
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};
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timer3_pins: timer3-pins {
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function = "timer3";
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pins = "PA15", "PA16";
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};
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timer_ext0_pins: timer-ext0-pins {
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function = "timer_ext0";
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pins = "PA17", "PA18", "PA19", "PA20";
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};
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timer_ext0_input_a_pins: timer-ext0-input-a-pins {
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function = "timer_ext0";
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pins = "PA17";
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};
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pps0_pins: pps0-pins {
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function = "timer_ext0";
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pins = "PA17";
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};
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timer_ext0_input_b_pins: timer-ext0-input-b-pins {
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function = "timer_ext0";
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pins = "PA18";
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};
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timer_ext0_output_pins: timer-ext0-output-pins {
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function = "timer_ext0";
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pins = "PA19", "PA20";
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};
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spi1_pins: spi1-pins {
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function = "spi1";
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pins = "PA21", "PA22", "PA23", "PA24";
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};
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spi1_reduced_pins: spi1-reduced-pins {
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function = "spi1";
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pins = "PA21", "PA22", "PA23";
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};
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timer_ext1_pins: timer-ext1-pins {
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function = "timer_ext1";
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pins = "PA26", "PA27", "PA28", "PA29";
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};
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timer_ext1_input_a_pins: timer-ext1-input-a-pins {
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function = "timer_ext1";
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pins = "PA26";
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};
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timer_ext1_input_b_pins: timer-ext1-input-b-pins {
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function = "timer_ext1";
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pins = "PA27";
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};
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timer_ext1_output_pins: timer-ext1-output-pins {
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function = "timer_ext1";
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pins = "PA28", "PA29";
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};
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ext_ref_clk_pins: ext-ref-clk-pins {
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function = "ext_ref_clk";
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pins = "PA30";
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};
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mipi_ref_clk_pins: mipi-ref-clk-pins {
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function = "mipi_ref_clk";
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pins = "PA31";
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};
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};
+170
arch/mips/boot/dts/mobileye/eyeq6lplus.dtsi
+170
arch/mips/boot/dts/mobileye/eyeq6lplus.dtsi
···
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// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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/*
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* Copyright 2025 Mobileye Vision Technologies Ltd.
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*/
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#include <dt-bindings/interrupt-controller/mips-gic.h>
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#include <dt-bindings/clock/mobileye,eyeq6lplus-clk.h>
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "img,i6500";
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reg = <0>;
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clocks = <&olb EQ6LPC_CPU_OCC>;
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};
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};
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cpu_intc: interrupt-controller {
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compatible = "mti,cpu-interrupt-controller";
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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coherency-manager {
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compatible = "mobileye,eyeq6-cm";
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};
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+
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xtal: clock-30000000 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <30000000>;
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};
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soc: soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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olb: system-controller@e8400000 {
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compatible = "mobileye,eyeq6lplus-olb", "syscon";
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reg = <0 0xe8400000 0x0 0x80000>;
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#reset-cells = <2>;
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#clock-cells = <1>;
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clocks = <&xtal>;
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clock-names = "ref";
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};
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ospi: spi@e8800000 {
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compatible = "mobileye,eyeq5-ospi", "cdns,qspi-nor";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0 0xe8800000 0x0 0x100000>,
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<0 0xb0000000 0x0 0x30000000>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 10 IRQ_TYPE_LEVEL_HIGH>;
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cdns,fifo-depth = <128>;
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cdns,fifo-width = <4>;
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cdns,trigger-address = <0x00000000>;
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clocks = <&olb EQ6LPC_PER_OSPI>;
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status = "disabled";
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};
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spi0: spi@eac0d000 {
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compatible = "snps,dw-apb-ssi";
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reg = <0 0xeac0d000 0x0 0x1000>;
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clocks = <&olb EQ6LPC_PER_SPI>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 11 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&olb 0 0>;
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reset-names = "spi";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi1: spi@eac0e000 {
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compatible = "snps,dw-apb-ssi";
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reg = <0 0xeac0e000 0x0 0x1000>;
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spi-slave;
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clocks = <&olb EQ6LPC_PER_SPI>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&olb 0 1>;
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reset-names = "spi";
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#address-cells = <0>;
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#size-cells = <0>;
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status = "disabled";
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};
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uart0: serial@eac10000 {
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compatible = "snps,dw-apb-uart";
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&olb EQ6LPC_PER_UART>;
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clock-frequency = <15625000>;
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reg = <0 0xeac10000 0x0 0x1000>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 8 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&olb 0 2>;
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status = "disabled";
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};
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i2c0: i2c@eac11000 {
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compatible = "mobileye,eyeq6lplus-i2c", "snps,designware-i2c";
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reg = <0 0xeac11000 0x0 0x1000>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <400000>;
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clocks = <&olb EQ6LPC_PER_I2C_SER>;
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resets = <&olb 0 3>;
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i2c-sda-hold-time-ns = <50>;
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status = "disabled";
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};
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i2c1: i2c@eac12000 {
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compatible = "mobileye,eyeq6lplus-i2c", "snps,designware-i2c";
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reg = <0 0xeac12000 0x0 0x1000>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 7 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <400000>;
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clocks = <&olb EQ6LPC_PER_I2C_SER>;
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resets = <&olb 0 4>;
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i2c-sda-hold-time-ns = <50>;
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status = "disabled";
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};
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gpio: gpio@eac14000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x0 0xeac14000 0x0 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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resets = <&olb 0 13>;
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porta: gpio-port@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <32>;
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gpio-ranges = <&olb 0 0 32>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 13 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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+
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gic: interrupt-controller@f0920000 {
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compatible = "mti,gic";
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reg = <0x0 0xf0920000 0x0 0x20000>;
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&cpu_intc>;
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timer {
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compatible = "mti,gic-timer";
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interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
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clocks = <&olb EQ6LPC_CPU_OCC>;
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};
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};
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};
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};
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#include "eyeq6lplus-pins.dtsi"