Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'memory-controller-drv-pl353-5.14' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into arm/drivers
Memory controller drivers for v5.14 - PL353
Bigger work around ARM Primecell PL35x SMC memory controller driver by
Miquel Raynal built on previous series from Naga Sureshkumar Relli.
This includes bindings cleanup and correction, converting these to
dtschema and several cleanyps in pl353-smc driver.
* tag 'memory-controller-drv-pl353-5.14' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl:
dt-binding: memory: pl353-smc: Convert to yaml
MAINTAINERS: Add PL353 SMC entry
memory: pl353-smc: Declare variables following a reverse christmas tree order
memory: pl353-smc: Avoid useless acronyms in descriptions
memory: pl353-smc: Let lower level controller drivers handle inits
memory: pl353-smc: Rename goto labels
memory: pl353-smc: Fix style
dt-binding: memory: pl353-smc: Fix the NAND controller node in the example
dt-binding: memory: pl353-smc: Drop unsupported nodes from the example
dt-binding: memory: pl353-smc: Fix the example syntax and style
dt-binding: memory: pl353-smc: Describe the child reg property
dt-binding: memory: pl353-smc: Drop the partitioning section
dt-binding: memory: pl353-smc: Document the range property
dt-binding: memory: pl353-smc: Rephrase the binding
Link: https://lore.kernel.org/r/20210611140659.61980-2-krzysztof.kozlowski@canonical.com
Signed-off-by: Olof Johansson <olof@lixom.net>
+149
-381
+131
Documentation/devicetree/bindings/memory-controllers/arm,pl353-smc.yaml
+131
Documentation/devicetree/bindings/memory-controllers/arm,pl353-smc.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/memory-controllers/arm,pl353-smc.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: ARM PL353 Static Memory Controller (SMC) device-tree bindings
8
+
9
+
maintainers:
10
+
- Miquel Raynal <miquel.raynal@bootlin.com>
11
+
- Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>
12
+
13
+
description:
14
+
The PL353 Static Memory Controller is a bus where you can connect two kinds
15
+
of memory interfaces, which are NAND and memory mapped interfaces (such as
16
+
SRAM or NOR).
17
+
18
+
# We need a select here so we don't match all nodes with 'arm,primecell'
19
+
select:
20
+
properties:
21
+
compatible:
22
+
contains:
23
+
const: arm,pl353-smc-r2p1
24
+
required:
25
+
- compatible
26
+
27
+
properties:
28
+
$nodename:
29
+
pattern: "^memory-controller@[0-9a-f]+$"
30
+
31
+
compatible:
32
+
items:
33
+
- const: arm,pl353-smc-r2p1
34
+
- const: arm,primecell
35
+
36
+
"#address-cells":
37
+
const: 2
38
+
39
+
"#size-cells":
40
+
const: 1
41
+
42
+
reg:
43
+
items:
44
+
- description:
45
+
Configuration registers for the host and sub-controllers.
46
+
The three chip select regions are defined in 'ranges'.
47
+
48
+
clocks:
49
+
items:
50
+
- description: clock for the memory device bus
51
+
- description: main clock of the SMC
52
+
53
+
clock-names:
54
+
items:
55
+
- const: memclk
56
+
- const: apb_pclk
57
+
58
+
ranges:
59
+
minItems: 1
60
+
maxItems: 3
61
+
description: |
62
+
Memory bus areas for interacting with the devices. Reflects
63
+
the memory layout with four integer values following:
64
+
<cs-number> 0 <offset> <size>
65
+
items:
66
+
- description: NAND bank 0
67
+
- description: NOR/SRAM bank 0
68
+
- description: NOR/SRAM bank 1
69
+
70
+
interrupts: true
71
+
72
+
patternProperties:
73
+
"@[0-3],[a-f0-9]+$":
74
+
type: object
75
+
description: |
76
+
The child device node represents the controller connected to the SMC
77
+
bus. The controller can be a NAND controller or a pair of any memory
78
+
mapped controllers such as NOR and SRAM controllers.
79
+
80
+
properties:
81
+
compatible:
82
+
description:
83
+
Compatible of memory controller.
84
+
85
+
reg:
86
+
items:
87
+
- items:
88
+
- description: |
89
+
Chip-select ID, as in the parent range property.
90
+
minimum: 0
91
+
maximum: 2
92
+
- description: |
93
+
Offset of the memory region requested by the device.
94
+
- description: |
95
+
Length of the memory region requested by the device.
96
+
97
+
required:
98
+
- compatible
99
+
- reg
100
+
101
+
required:
102
+
- compatible
103
+
- reg
104
+
- clock-names
105
+
- clocks
106
+
- "#address-cells"
107
+
- "#size-cells"
108
+
- ranges
109
+
110
+
additionalProperties: false
111
+
112
+
examples:
113
+
- |
114
+
smcc: memory-controller@e000e000 {
115
+
compatible = "arm,pl353-smc-r2p1", "arm,primecell";
116
+
reg = <0xe000e000 0x0001000>;
117
+
clock-names = "memclk", "apb_pclk";
118
+
clocks = <&clkc 11>, <&clkc 44>;
119
+
ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */
120
+
0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */
121
+
0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */
122
+
#address-cells = <2>;
123
+
#size-cells = <1>;
124
+
125
+
nfc0: nand-controller@0,0 {
126
+
compatible = "arm,pl353-nand-r2p1";
127
+
reg = <0 0 0x1000000>;
128
+
#address-cells = <1>;
129
+
#size-cells = <0>;
130
+
};
131
+
};
-47
Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt
-47
Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt
···
1
-
Device tree bindings for ARM PL353 static memory controller
2
-
3
-
PL353 static memory controller supports two kinds of memory
4
-
interfaces.i.e NAND and SRAM/NOR interfaces.
5
-
The actual devices are instantiated from the child nodes of pl353 smc node.
6
-
7
-
Required properties:
8
-
- compatible : Should be "arm,pl353-smc-r2p1", "arm,primecell".
9
-
- reg : Controller registers map and length.
10
-
- clock-names : List of input clock names - "memclk", "apb_pclk"
11
-
(See clock bindings for details).
12
-
- clocks : Clock phandles (see clock bindings for details).
13
-
- address-cells : Must be 2.
14
-
- size-cells : Must be 1.
15
-
16
-
Child nodes:
17
-
For NAND the "arm,pl353-nand-r2p1" and for NOR the "cfi-flash" drivers are
18
-
supported as child nodes.
19
-
20
-
for NAND partition information please refer the below file
21
-
Documentation/devicetree/bindings/mtd/partition.txt
22
-
23
-
Example:
24
-
smcc: memory-controller@e000e000
25
-
compatible = "arm,pl353-smc-r2p1", "arm,primecell";
26
-
clock-names = "memclk", "apb_pclk";
27
-
clocks = <&clkc 11>, <&clkc 44>;
28
-
reg = <0xe000e000 0x1000>;
29
-
#address-cells = <2>;
30
-
#size-cells = <1>;
31
-
ranges = <0x0 0x0 0xe1000000 0x1000000 //Nand CS Region
32
-
0x1 0x0 0xe2000000 0x2000000 //SRAM/NOR CS Region
33
-
0x2 0x0 0xe4000000 0x2000000>; //SRAM/NOR CS Region
34
-
nand_0: flash@e1000000 {
35
-
compatible = "arm,pl353-nand-r2p1"
36
-
reg = <0 0 0x1000000>;
37
-
(...)
38
-
};
39
-
nor0: flash@e2000000 {
40
-
compatible = "cfi-flash";
41
-
reg = <1 0 0x2000000>;
42
-
};
43
-
nor1: flash@e4000000 {
44
-
compatible = "cfi-flash";
45
-
reg = <2 0 0x2000000>;
46
-
};
47
-
};
+8
MAINTAINERS
+8
MAINTAINERS
···
1452
1452
F: drivers/amba/
1453
1453
F: include/linux/amba/bus.h
1454
1454
1455
+
ARM PRIMECELL PL35X SMC DRIVER
1456
+
M: Miquel Raynal <miquel.raynal@bootlin.com@bootlin.com>
1457
+
M: Naga Sureshkumar Relli <nagasure@xilinx.com>
1458
+
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
1459
+
S: Maintained
1460
+
F: Documentation/devicetree/bindings/mtd/arm,pl353-smc.yaml
1461
+
F: drivers/memory/pl353-smc.c
1462
+
1455
1463
ARM PRIMECELL CLCD PL110 DRIVER
1456
1464
M: Russell King <linux@armlinux.org.uk>
1457
1465
S: Odd Fixes
+10
-304
drivers/memory/pl353-smc.c
+10
-304
drivers/memory/pl353-smc.c
···
8
8
*/
9
9
10
10
#include <linux/clk.h>
11
-
#include <linux/io.h>
12
11
#include <linux/kernel.h>
13
12
#include <linux/module.h>
14
13
#include <linux/of_platform.h>
15
14
#include <linux/platform_device.h>
16
-
#include <linux/slab.h>
17
-
#include <linux/pl353-smc.h>
18
15
#include <linux/amba/bus.h>
19
16
20
-
/* Register definitions */
21
-
#define PL353_SMC_MEMC_STATUS_OFFS 0 /* Controller status reg, RO */
22
-
#define PL353_SMC_CFG_CLR_OFFS 0xC /* Clear config reg, WO */
23
-
#define PL353_SMC_DIRECT_CMD_OFFS 0x10 /* Direct command reg, WO */
24
-
#define PL353_SMC_SET_CYCLES_OFFS 0x14 /* Set cycles register, WO */
25
-
#define PL353_SMC_SET_OPMODE_OFFS 0x18 /* Set opmode register, WO */
26
-
#define PL353_SMC_ECC_STATUS_OFFS 0x400 /* ECC status register */
27
-
#define PL353_SMC_ECC_MEMCFG_OFFS 0x404 /* ECC mem config reg */
28
-
#define PL353_SMC_ECC_MEMCMD1_OFFS 0x408 /* ECC mem cmd1 reg */
29
-
#define PL353_SMC_ECC_MEMCMD2_OFFS 0x40C /* ECC mem cmd2 reg */
30
-
#define PL353_SMC_ECC_VALUE0_OFFS 0x418 /* ECC value 0 reg */
31
-
32
-
/* Controller status register specific constants */
33
-
#define PL353_SMC_MEMC_STATUS_RAW_INT_1_SHIFT 6
34
-
35
-
/* Clear configuration register specific constants */
36
-
#define PL353_SMC_CFG_CLR_INT_CLR_1 0x10
37
-
#define PL353_SMC_CFG_CLR_ECC_INT_DIS_1 0x40
38
-
#define PL353_SMC_CFG_CLR_INT_DIS_1 0x2
39
-
#define PL353_SMC_CFG_CLR_DEFAULT_MASK (PL353_SMC_CFG_CLR_INT_CLR_1 | \
40
-
PL353_SMC_CFG_CLR_ECC_INT_DIS_1 | \
41
-
PL353_SMC_CFG_CLR_INT_DIS_1)
42
-
43
-
/* Set cycles register specific constants */
44
-
#define PL353_SMC_SET_CYCLES_T0_MASK 0xF
45
-
#define PL353_SMC_SET_CYCLES_T0_SHIFT 0
46
-
#define PL353_SMC_SET_CYCLES_T1_MASK 0xF
47
-
#define PL353_SMC_SET_CYCLES_T1_SHIFT 4
48
-
#define PL353_SMC_SET_CYCLES_T2_MASK 0x7
49
-
#define PL353_SMC_SET_CYCLES_T2_SHIFT 8
50
-
#define PL353_SMC_SET_CYCLES_T3_MASK 0x7
51
-
#define PL353_SMC_SET_CYCLES_T3_SHIFT 11
52
-
#define PL353_SMC_SET_CYCLES_T4_MASK 0x7
53
-
#define PL353_SMC_SET_CYCLES_T4_SHIFT 14
54
-
#define PL353_SMC_SET_CYCLES_T5_MASK 0x7
55
-
#define PL353_SMC_SET_CYCLES_T5_SHIFT 17
56
-
#define PL353_SMC_SET_CYCLES_T6_MASK 0xF
57
-
#define PL353_SMC_SET_CYCLES_T6_SHIFT 20
58
-
59
-
/* ECC status register specific constants */
60
-
#define PL353_SMC_ECC_STATUS_BUSY BIT(6)
61
-
#define PL353_SMC_ECC_REG_SIZE_OFFS 4
62
-
63
-
/* ECC memory config register specific constants */
64
-
#define PL353_SMC_ECC_MEMCFG_MODE_MASK 0xC
65
-
#define PL353_SMC_ECC_MEMCFG_MODE_SHIFT 2
66
-
#define PL353_SMC_ECC_MEMCFG_PGSIZE_MASK 0x3
67
-
68
-
#define PL353_SMC_DC_UPT_NAND_REGS ((4 << 23) | /* CS: NAND chip */ \
69
-
(2 << 21)) /* UpdateRegs operation */
70
-
71
-
#define PL353_NAND_ECC_CMD1 ((0x80) | /* Write command */ \
72
-
(0 << 8) | /* Read command */ \
73
-
(0x30 << 16) | /* Read End command */ \
74
-
(1 << 24)) /* Read End command calid */
75
-
76
-
#define PL353_NAND_ECC_CMD2 ((0x85) | /* Write col change cmd */ \
77
-
(5 << 8) | /* Read col change cmd */ \
78
-
(0xE0 << 16) | /* Read col change end cmd */ \
79
-
(1 << 24)) /* Read col change end cmd valid */
80
-
#define PL353_NAND_ECC_BUSY_TIMEOUT (1 * HZ)
81
17
/**
82
18
* struct pl353_smc_data - Private smc driver structure
83
19
* @memclk: Pointer to the peripheral clock
84
-
* @aclk: Pointer to the APER clock
20
+
* @aclk: Pointer to the AXI peripheral clock
85
21
*/
86
22
struct pl353_smc_data {
87
23
struct clk *memclk;
88
24
struct clk *aclk;
89
25
};
90
-
91
-
/* SMC virtual register base */
92
-
static void __iomem *pl353_smc_base;
93
-
94
-
/**
95
-
* pl353_smc_set_buswidth - Set memory buswidth
96
-
* @bw: Memory buswidth (8 | 16)
97
-
* Return: 0 on success or negative errno.
98
-
*/
99
-
int pl353_smc_set_buswidth(unsigned int bw)
100
-
{
101
-
if (bw != PL353_SMC_MEM_WIDTH_8 && bw != PL353_SMC_MEM_WIDTH_16)
102
-
return -EINVAL;
103
-
104
-
writel(bw, pl353_smc_base + PL353_SMC_SET_OPMODE_OFFS);
105
-
writel(PL353_SMC_DC_UPT_NAND_REGS, pl353_smc_base +
106
-
PL353_SMC_DIRECT_CMD_OFFS);
107
-
108
-
return 0;
109
-
}
110
-
EXPORT_SYMBOL_GPL(pl353_smc_set_buswidth);
111
-
112
-
/**
113
-
* pl353_smc_set_cycles - Set memory timing parameters
114
-
* @timings: NAND controller timing parameters
115
-
*
116
-
* Sets NAND chip specific timing parameters.
117
-
*/
118
-
void pl353_smc_set_cycles(u32 timings[])
119
-
{
120
-
/*
121
-
* Set write pulse timing. This one is easy to extract:
122
-
*
123
-
* NWE_PULSE = tWP
124
-
*/
125
-
timings[0] &= PL353_SMC_SET_CYCLES_T0_MASK;
126
-
timings[1] = (timings[1] & PL353_SMC_SET_CYCLES_T1_MASK) <<
127
-
PL353_SMC_SET_CYCLES_T1_SHIFT;
128
-
timings[2] = (timings[2] & PL353_SMC_SET_CYCLES_T2_MASK) <<
129
-
PL353_SMC_SET_CYCLES_T2_SHIFT;
130
-
timings[3] = (timings[3] & PL353_SMC_SET_CYCLES_T3_MASK) <<
131
-
PL353_SMC_SET_CYCLES_T3_SHIFT;
132
-
timings[4] = (timings[4] & PL353_SMC_SET_CYCLES_T4_MASK) <<
133
-
PL353_SMC_SET_CYCLES_T4_SHIFT;
134
-
timings[5] = (timings[5] & PL353_SMC_SET_CYCLES_T5_MASK) <<
135
-
PL353_SMC_SET_CYCLES_T5_SHIFT;
136
-
timings[6] = (timings[6] & PL353_SMC_SET_CYCLES_T6_MASK) <<
137
-
PL353_SMC_SET_CYCLES_T6_SHIFT;
138
-
timings[0] |= timings[1] | timings[2] | timings[3] |
139
-
timings[4] | timings[5] | timings[6];
140
-
141
-
writel(timings[0], pl353_smc_base + PL353_SMC_SET_CYCLES_OFFS);
142
-
writel(PL353_SMC_DC_UPT_NAND_REGS, pl353_smc_base +
143
-
PL353_SMC_DIRECT_CMD_OFFS);
144
-
}
145
-
EXPORT_SYMBOL_GPL(pl353_smc_set_cycles);
146
-
147
-
/**
148
-
* pl353_smc_ecc_is_busy - Read ecc busy flag
149
-
* Return: the ecc_status bit from the ecc_status register. 1 = busy, 0 = idle
150
-
*/
151
-
bool pl353_smc_ecc_is_busy(void)
152
-
{
153
-
return ((readl(pl353_smc_base + PL353_SMC_ECC_STATUS_OFFS) &
154
-
PL353_SMC_ECC_STATUS_BUSY) == PL353_SMC_ECC_STATUS_BUSY);
155
-
}
156
-
EXPORT_SYMBOL_GPL(pl353_smc_ecc_is_busy);
157
-
158
-
/**
159
-
* pl353_smc_get_ecc_val - Read ecc_valueN registers
160
-
* @ecc_reg: Index of the ecc_value reg (0..3)
161
-
* Return: the content of the requested ecc_value register.
162
-
*
163
-
* There are four valid ecc_value registers. The argument is truncated to stay
164
-
* within this valid boundary.
165
-
*/
166
-
u32 pl353_smc_get_ecc_val(int ecc_reg)
167
-
{
168
-
u32 addr, reg;
169
-
170
-
addr = PL353_SMC_ECC_VALUE0_OFFS +
171
-
(ecc_reg * PL353_SMC_ECC_REG_SIZE_OFFS);
172
-
reg = readl(pl353_smc_base + addr);
173
-
174
-
return reg;
175
-
}
176
-
EXPORT_SYMBOL_GPL(pl353_smc_get_ecc_val);
177
-
178
-
/**
179
-
* pl353_smc_get_nand_int_status_raw - Get NAND interrupt status bit
180
-
* Return: the raw_int_status1 bit from the memc_status register
181
-
*/
182
-
int pl353_smc_get_nand_int_status_raw(void)
183
-
{
184
-
u32 reg;
185
-
186
-
reg = readl(pl353_smc_base + PL353_SMC_MEMC_STATUS_OFFS);
187
-
reg >>= PL353_SMC_MEMC_STATUS_RAW_INT_1_SHIFT;
188
-
reg &= 1;
189
-
190
-
return reg;
191
-
}
192
-
EXPORT_SYMBOL_GPL(pl353_smc_get_nand_int_status_raw);
193
-
194
-
/**
195
-
* pl353_smc_clr_nand_int - Clear NAND interrupt
196
-
*/
197
-
void pl353_smc_clr_nand_int(void)
198
-
{
199
-
writel(PL353_SMC_CFG_CLR_INT_CLR_1,
200
-
pl353_smc_base + PL353_SMC_CFG_CLR_OFFS);
201
-
}
202
-
EXPORT_SYMBOL_GPL(pl353_smc_clr_nand_int);
203
-
204
-
/**
205
-
* pl353_smc_set_ecc_mode - Set SMC ECC mode
206
-
* @mode: ECC mode (BYPASS, APB, MEM)
207
-
* Return: 0 on success or negative errno.
208
-
*/
209
-
int pl353_smc_set_ecc_mode(enum pl353_smc_ecc_mode mode)
210
-
{
211
-
u32 reg;
212
-
int ret = 0;
213
-
214
-
switch (mode) {
215
-
case PL353_SMC_ECCMODE_BYPASS:
216
-
case PL353_SMC_ECCMODE_APB:
217
-
case PL353_SMC_ECCMODE_MEM:
218
-
219
-
reg = readl(pl353_smc_base + PL353_SMC_ECC_MEMCFG_OFFS);
220
-
reg &= ~PL353_SMC_ECC_MEMCFG_MODE_MASK;
221
-
reg |= mode << PL353_SMC_ECC_MEMCFG_MODE_SHIFT;
222
-
writel(reg, pl353_smc_base + PL353_SMC_ECC_MEMCFG_OFFS);
223
-
224
-
break;
225
-
default:
226
-
ret = -EINVAL;
227
-
}
228
-
229
-
return ret;
230
-
}
231
-
EXPORT_SYMBOL_GPL(pl353_smc_set_ecc_mode);
232
-
233
-
/**
234
-
* pl353_smc_set_ecc_pg_size - Set SMC ECC page size
235
-
* @pg_sz: ECC page size
236
-
* Return: 0 on success or negative errno.
237
-
*/
238
-
int pl353_smc_set_ecc_pg_size(unsigned int pg_sz)
239
-
{
240
-
u32 reg, sz;
241
-
242
-
switch (pg_sz) {
243
-
case 0:
244
-
sz = 0;
245
-
break;
246
-
case SZ_512:
247
-
sz = 1;
248
-
break;
249
-
case SZ_1K:
250
-
sz = 2;
251
-
break;
252
-
case SZ_2K:
253
-
sz = 3;
254
-
break;
255
-
default:
256
-
return -EINVAL;
257
-
}
258
-
259
-
reg = readl(pl353_smc_base + PL353_SMC_ECC_MEMCFG_OFFS);
260
-
reg &= ~PL353_SMC_ECC_MEMCFG_PGSIZE_MASK;
261
-
reg |= sz;
262
-
writel(reg, pl353_smc_base + PL353_SMC_ECC_MEMCFG_OFFS);
263
-
264
-
return 0;
265
-
}
266
-
EXPORT_SYMBOL_GPL(pl353_smc_set_ecc_pg_size);
267
26
268
27
static int __maybe_unused pl353_smc_suspend(struct device *dev)
269
28
{
···
36
277
37
278
static int __maybe_unused pl353_smc_resume(struct device *dev)
38
279
{
39
-
int ret;
40
280
struct pl353_smc_data *pl353_smc = dev_get_drvdata(dev);
281
+
int ret;
41
282
42
283
ret = clk_enable(pl353_smc->aclk);
43
284
if (ret) {
···
55
296
return ret;
56
297
}
57
298
58
-
static struct amba_driver pl353_smc_driver;
59
-
60
299
static SIMPLE_DEV_PM_OPS(pl353_smc_dev_pm_ops, pl353_smc_suspend,
61
300
pl353_smc_resume);
62
-
63
-
/**
64
-
* pl353_smc_init_nand_interface - Initialize the NAND interface
65
-
* @adev: Pointer to the amba_device struct
66
-
* @nand_node: Pointer to the pl353_nand device_node struct
67
-
*/
68
-
static void pl353_smc_init_nand_interface(struct amba_device *adev,
69
-
struct device_node *nand_node)
70
-
{
71
-
unsigned long timeout;
72
-
73
-
pl353_smc_set_buswidth(PL353_SMC_MEM_WIDTH_8);
74
-
writel(PL353_SMC_CFG_CLR_INT_CLR_1,
75
-
pl353_smc_base + PL353_SMC_CFG_CLR_OFFS);
76
-
writel(PL353_SMC_DC_UPT_NAND_REGS, pl353_smc_base +
77
-
PL353_SMC_DIRECT_CMD_OFFS);
78
-
79
-
timeout = jiffies + PL353_NAND_ECC_BUSY_TIMEOUT;
80
-
/* Wait till the ECC operation is complete */
81
-
do {
82
-
if (pl353_smc_ecc_is_busy())
83
-
cpu_relax();
84
-
else
85
-
break;
86
-
} while (!time_after_eq(jiffies, timeout));
87
-
88
-
if (time_after_eq(jiffies, timeout))
89
-
return;
90
-
91
-
writel(PL353_NAND_ECC_CMD1,
92
-
pl353_smc_base + PL353_SMC_ECC_MEMCMD1_OFFS);
93
-
writel(PL353_NAND_ECC_CMD2,
94
-
pl353_smc_base + PL353_SMC_ECC_MEMCMD2_OFFS);
95
-
}
96
301
97
302
static const struct of_device_id pl353_smc_supported_children[] = {
98
303
{
···
64
341
},
65
342
{
66
343
.compatible = "arm,pl353-nand-r2p1",
67
-
.data = pl353_smc_init_nand_interface
68
344
},
69
345
{}
70
346
};
71
347
72
348
static int pl353_smc_probe(struct amba_device *adev, const struct amba_id *id)
73
349
{
350
+
struct device_node *of_node = adev->dev.of_node;
351
+
const struct of_device_id *match = NULL;
74
352
struct pl353_smc_data *pl353_smc;
75
353
struct device_node *child;
76
-
struct resource *res;
77
354
int err;
78
-
struct device_node *of_node = adev->dev.of_node;
79
-
static void (*init)(struct amba_device *adev,
80
-
struct device_node *nand_node);
81
-
const struct of_device_id *match = NULL;
82
355
83
356
pl353_smc = devm_kzalloc(&adev->dev, sizeof(*pl353_smc), GFP_KERNEL);
84
357
if (!pl353_smc)
85
358
return -ENOMEM;
86
-
87
-
/* Get the NAND controller virtual address */
88
-
res = &adev->res;
89
-
pl353_smc_base = devm_ioremap_resource(&adev->dev, res);
90
-
if (IS_ERR(pl353_smc_base))
91
-
return PTR_ERR(pl353_smc_base);
92
359
93
360
pl353_smc->aclk = devm_clk_get(&adev->dev, "apb_pclk");
94
361
if (IS_ERR(pl353_smc->aclk)) {
···
101
388
err = clk_prepare_enable(pl353_smc->memclk);
102
389
if (err) {
103
390
dev_err(&adev->dev, "Unable to enable memory clock.\n");
104
-
goto out_clk_dis_aper;
391
+
goto disable_axi_clk;
105
392
}
106
393
107
394
amba_set_drvdata(adev, pl353_smc);
108
-
109
-
/* clear interrupts */
110
-
writel(PL353_SMC_CFG_CLR_DEFAULT_MASK,
111
-
pl353_smc_base + PL353_SMC_CFG_CLR_OFFS);
112
395
113
396
/* Find compatible children. Only a single child is supported */
114
397
for_each_available_child_of_node(of_node, child) {
···
118
409
if (!match) {
119
410
err = -ENODEV;
120
411
dev_err(&adev->dev, "no matching children\n");
121
-
goto out_clk_disable;
412
+
goto disable_mem_clk;
122
413
}
123
414
124
-
init = match->data;
125
-
if (init)
126
-
init(adev, child);
127
415
of_platform_device_create(child, NULL, &adev->dev);
128
416
129
417
return 0;
130
418
131
-
out_clk_disable:
419
+
disable_mem_clk:
132
420
clk_disable_unprepare(pl353_smc->memclk);
133
-
out_clk_dis_aper:
421
+
disable_axi_clk:
134
422
clk_disable_unprepare(pl353_smc->aclk);
135
423
136
424
return err;
···
143
437
144
438
static const struct amba_id pl353_ids[] = {
145
439
{
146
-
.id = 0x00041353,
147
-
.mask = 0x000fffff,
440
+
.id = 0x00041353,
441
+
.mask = 0x000fffff,
148
442
},
149
443
{ 0, 0 },
150
444
};
-30
include/linux/pl353-smc.h
-30
include/linux/pl353-smc.h
···
1
-
/* SPDX-License-Identifier: GPL-2.0 */
2
-
/*
3
-
* ARM PL353 SMC Driver Header
4
-
*
5
-
* Copyright (C) 2012 - 2018 Xilinx, Inc
6
-
*/
7
-
8
-
#ifndef __LINUX_PL353_SMC_H
9
-
#define __LINUX_PL353_SMC_H
10
-
11
-
enum pl353_smc_ecc_mode {
12
-
PL353_SMC_ECCMODE_BYPASS = 0,
13
-
PL353_SMC_ECCMODE_APB = 1,
14
-
PL353_SMC_ECCMODE_MEM = 2
15
-
};
16
-
17
-
enum pl353_smc_mem_width {
18
-
PL353_SMC_MEM_WIDTH_8 = 0,
19
-
PL353_SMC_MEM_WIDTH_16 = 1
20
-
};
21
-
22
-
u32 pl353_smc_get_ecc_val(int ecc_reg);
23
-
bool pl353_smc_ecc_is_busy(void);
24
-
int pl353_smc_get_nand_int_status_raw(void);
25
-
void pl353_smc_clr_nand_int(void);
26
-
int pl353_smc_set_ecc_mode(enum pl353_smc_ecc_mode mode);
27
-
int pl353_smc_set_ecc_pg_size(unsigned int pg_sz);
28
-
int pl353_smc_set_buswidth(unsigned int bw);
29
-
void pl353_smc_set_cycles(u32 timings[]);
30
-
#endif