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drm: atmel-hlcdc: add support for 8-bit color lookup table mode

All layers of all supported chips support this, the only variable is the
base address of the lookup table in the register map.

Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Peter Rosin <peda@axentia.se>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1498107791-17450-3-git-send-email-peda@axentia.se

authored by

Peter Rosin and committed by
Boris Brezillon 364a7bf5 ae7c59f0

+64
+5
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
··· 430 430 .enable_vblank = atmel_hlcdc_crtc_enable_vblank, 431 431 .disable_vblank = atmel_hlcdc_crtc_disable_vblank, 432 432 .set_property = drm_atomic_helper_crtc_set_property, 433 + .gamma_set = drm_atomic_helper_legacy_gamma_set, 433 434 }; 434 435 435 436 int atmel_hlcdc_crtc_create(struct drm_device *dev) ··· 485 484 486 485 drm_crtc_helper_add(&crtc->base, &lcdc_crtc_helper_funcs); 487 486 drm_crtc_vblank_reset(&crtc->base); 487 + 488 + drm_mode_crtc_set_gamma_size(&crtc->base, ATMEL_HLCDC_CLUT_SIZE); 489 + drm_crtc_enable_color_mgmt(&crtc->base, 0, false, 490 + ATMEL_HLCDC_CLUT_SIZE); 488 491 489 492 dc->crtc = &crtc->base; 490 493
+14
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c
··· 42 42 .default_color = 3, 43 43 .general_config = 4, 44 44 }, 45 + .clut_offset = 0x400, 45 46 }, 46 47 }; 47 48 ··· 74 73 .disc_pos = 5, 75 74 .disc_size = 6, 76 75 }, 76 + .clut_offset = 0x400, 77 77 }, 78 78 { 79 79 .name = "overlay1", ··· 93 91 .chroma_key_mask = 8, 94 92 .general_config = 9, 95 93 }, 94 + .clut_offset = 0x800, 96 95 }, 97 96 { 98 97 .name = "high-end-overlay", ··· 115 112 .scaler_config = 13, 116 113 .csc = 14, 117 114 }, 115 + .clut_offset = 0x1000, 118 116 }, 119 117 { 120 118 .name = "cursor", ··· 135 131 .chroma_key_mask = 8, 136 132 .general_config = 9, 137 133 }, 134 + .clut_offset = 0x1400, 138 135 }, 139 136 }; 140 137 ··· 167 162 .disc_pos = 5, 168 163 .disc_size = 6, 169 164 }, 165 + .clut_offset = 0x600, 170 166 }, 171 167 { 172 168 .name = "overlay1", ··· 186 180 .chroma_key_mask = 8, 187 181 .general_config = 9, 188 182 }, 183 + .clut_offset = 0xa00, 189 184 }, 190 185 { 191 186 .name = "overlay2", ··· 205 198 .chroma_key_mask = 8, 206 199 .general_config = 9, 207 200 }, 201 + .clut_offset = 0xe00, 208 202 }, 209 203 { 210 204 .name = "high-end-overlay", ··· 231 223 }, 232 224 .csc = 14, 233 225 }, 226 + .clut_offset = 0x1200, 234 227 }, 235 228 { 236 229 .name = "cursor", ··· 253 244 .general_config = 9, 254 245 .scaler_config = 13, 255 246 }, 247 + .clut_offset = 0x1600, 256 248 }, 257 249 }; 258 250 ··· 285 275 .disc_pos = 5, 286 276 .disc_size = 6, 287 277 }, 278 + .clut_offset = 0x600, 288 279 }, 289 280 { 290 281 .name = "overlay1", ··· 304 293 .chroma_key_mask = 8, 305 294 .general_config = 9, 306 295 }, 296 + .clut_offset = 0xa00, 307 297 }, 308 298 { 309 299 .name = "overlay2", ··· 323 311 .chroma_key_mask = 8, 324 312 .general_config = 9, 325 313 }, 314 + .clut_offset = 0xe00, 326 315 }, 327 316 { 328 317 .name = "high-end-overlay", ··· 349 336 }, 350 337 .csc = 14, 351 338 }, 339 + .clut_offset = 0x1200, 352 340 }, 353 341 }; 354 342
+16
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h
··· 88 88 #define ATMEL_HLCDC_YUV422SWP BIT(17) 89 89 #define ATMEL_HLCDC_DSCALEOPT BIT(20) 90 90 91 + #define ATMEL_HLCDC_C1_MODE ATMEL_HLCDC_CLUT_MODE(0) 92 + #define ATMEL_HLCDC_C2_MODE ATMEL_HLCDC_CLUT_MODE(1) 93 + #define ATMEL_HLCDC_C4_MODE ATMEL_HLCDC_CLUT_MODE(2) 94 + #define ATMEL_HLCDC_C8_MODE ATMEL_HLCDC_CLUT_MODE(3) 95 + 91 96 #define ATMEL_HLCDC_XRGB4444_MODE ATMEL_HLCDC_RGB_MODE(0) 92 97 #define ATMEL_HLCDC_ARGB4444_MODE ATMEL_HLCDC_RGB_MODE(1) 93 98 #define ATMEL_HLCDC_RGBA4444_MODE ATMEL_HLCDC_RGB_MODE(2) ··· 146 141 #define ATMEL_HLCDC_DMA_CHANNEL_DSCR_LOADED BIT(1) 147 142 #define ATMEL_HLCDC_DMA_CHANNEL_DSCR_DONE BIT(2) 148 143 #define ATMEL_HLCDC_DMA_CHANNEL_DSCR_OVERRUN BIT(3) 144 + 145 + #define ATMEL_HLCDC_CLUT_SIZE 256 149 146 150 147 #define ATMEL_HLCDC_MAX_LAYERS 6 151 148 ··· 266 259 int id; 267 260 int regs_offset; 268 261 int cfgs_offset; 262 + int clut_offset; 269 263 struct atmel_hlcdc_formats *formats; 270 264 struct atmel_hlcdc_layer_cfg_layout layout; 271 265 int max_width; ··· 420 412 return atmel_hlcdc_layer_read_reg(layer, 421 413 layer->desc->cfgs_offset + 422 414 (cfgid * sizeof(u32))); 415 + } 416 + 417 + static inline void atmel_hlcdc_layer_write_clut(struct atmel_hlcdc_layer *layer, 418 + unsigned int c, u32 val) 419 + { 420 + regmap_write(layer->regmap, 421 + layer->desc->clut_offset + c * sizeof(u32), 422 + val); 423 423 } 424 424 425 425 static inline void atmel_hlcdc_layer_init(struct atmel_hlcdc_layer *layer,
+29
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c
··· 83 83 #define SUBPIXEL_MASK 0xffff 84 84 85 85 static uint32_t rgb_formats[] = { 86 + DRM_FORMAT_C8, 86 87 DRM_FORMAT_XRGB4444, 87 88 DRM_FORMAT_ARGB4444, 88 89 DRM_FORMAT_RGBA4444, ··· 101 100 }; 102 101 103 102 static uint32_t rgb_and_yuv_formats[] = { 103 + DRM_FORMAT_C8, 104 104 DRM_FORMAT_XRGB4444, 105 105 DRM_FORMAT_ARGB4444, 106 106 DRM_FORMAT_RGBA4444, ··· 130 128 static int atmel_hlcdc_format_to_plane_mode(u32 format, u32 *mode) 131 129 { 132 130 switch (format) { 131 + case DRM_FORMAT_C8: 132 + *mode = ATMEL_HLCDC_C8_MODE; 133 + break; 133 134 case DRM_FORMAT_XRGB4444: 134 135 *mode = ATMEL_HLCDC_XRGB4444_MODE; 135 136 break; ··· 427 422 428 423 atmel_hlcdc_layer_write_cfg(&plane->layer, 429 424 ATMEL_HLCDC_LAYER_FORMAT_CFG, cfg); 425 + } 426 + 427 + static void atmel_hlcdc_plane_update_clut(struct atmel_hlcdc_plane *plane) 428 + { 429 + struct drm_crtc *crtc = plane->base.crtc; 430 + struct drm_color_lut *lut; 431 + int idx; 432 + 433 + if (!crtc || !crtc->state) 434 + return; 435 + 436 + if (!crtc->state->color_mgmt_changed || !crtc->state->gamma_lut) 437 + return; 438 + 439 + lut = (struct drm_color_lut *)crtc->state->gamma_lut->data; 440 + 441 + for (idx = 0; idx < ATMEL_HLCDC_CLUT_SIZE; idx++, lut++) { 442 + u32 val = ((lut->red << 8) & 0xff0000) | 443 + (lut->green & 0xff00) | 444 + (lut->blue >> 8); 445 + 446 + atmel_hlcdc_layer_write_clut(&plane->layer, idx, val); 447 + } 430 448 } 431 449 432 450 static void atmel_hlcdc_plane_update_buffers(struct atmel_hlcdc_plane *plane, ··· 796 768 atmel_hlcdc_plane_update_pos_and_size(plane, state); 797 769 atmel_hlcdc_plane_update_general_settings(plane, state); 798 770 atmel_hlcdc_plane_update_format(plane, state); 771 + atmel_hlcdc_plane_update_clut(plane); 799 772 atmel_hlcdc_plane_update_buffers(plane, state); 800 773 atmel_hlcdc_plane_update_disc_area(plane, state); 801 774