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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/xe/pat: Clean up PAT register definitions
Replace the deprecated "GEN" terminology in the PAT definitions.
Acked-by: Nirmoy Das <nirmoy.das@intel.com>
Link: https://lore.kernel.org/r/20230324210415.2434992-5-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
authored by
Matt Roper
and committed by
Rodrigo Vivi
366974e4
152d7f2d
+38
-35
+38
-35
drivers/gpu/drm/xe/xe_pat.c
+38
-35
drivers/gpu/drm/xe/xe_pat.c
···
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#define _PAT_INDEX(index) (0x4800 + (index) * 4)
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#define GEN8_PPAT_WB (3<<0)
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#define GEN8_PPAT_WT (2<<0)
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#define GEN8_PPAT_WC (1<<0)
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#define GEN8_PPAT_UC (0<<0)
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#define GEN12_PPAT_CLOS(x) ((x)<<2)
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#define MTL_L4_POLICY_MASK REG_GENMASK(3, 2)
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#define MTL_PAT_3_UC REG_FIELD_PREP(MTL_L4_POLICY_MASK, 3)
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#define MTL_PAT_1_WT REG_FIELD_PREP(MTL_L4_POLICY_MASK, 1)
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#define MTL_PAT_0_WB REG_FIELD_PREP(MTL_L4_POLICY_MASK, 0)
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#define MTL_INDEX_COH_MODE_MASK REG_GENMASK(1, 0)
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#define MTL_3_COH_2W REG_FIELD_PREP(MTL_INDEX_COH_MODE_MASK, 3)
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#define MTL_2_COH_1W REG_FIELD_PREP(MTL_INDEX_COH_MODE_MASK, 2)
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#define MTL_0_COH_NON REG_FIELD_PREP(MTL_INDEX_COH_MODE_MASK, 0)
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#define PVC_CLOS_LEVEL_MASK REG_GENMASK(3, 2)
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#define PVC_PAT_CLOS(x) REG_FIELD_PREP(PVC_CLOS_LEVEL_MASK, x)
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#define TGL_MEM_TYPE_MASK REG_GENMASK(1, 0)
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#define TGL_PAT_WB REG_FIELD_PREP(TGL_MEM_TYPE_MASK, 3)
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#define TGL_PAT_WT REG_FIELD_PREP(TGL_MEM_TYPE_MASK, 2)
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#define TGL_PAT_WC REG_FIELD_PREP(TGL_MEM_TYPE_MASK, 1)
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#define TGL_PAT_UC REG_FIELD_PREP(TGL_MEM_TYPE_MASK, 0)
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const u32 tgl_pat_table[] = {
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[0] = GEN8_PPAT_WB,
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[1] = GEN8_PPAT_WC,
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[2] = GEN8_PPAT_WT,
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[3] = GEN8_PPAT_UC,
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[4] = GEN8_PPAT_WB,
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[5] = GEN8_PPAT_WB,
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[6] = GEN8_PPAT_WB,
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[7] = GEN8_PPAT_WB,
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[0] = TGL_PAT_WB,
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[1] = TGL_PAT_WC,
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[2] = TGL_PAT_WT,
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[3] = TGL_PAT_UC,
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[4] = TGL_PAT_WB,
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[5] = TGL_PAT_WB,
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[6] = TGL_PAT_WB,
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[7] = TGL_PAT_WB,
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};
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const u32 pvc_pat_table[] = {
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[0] = GEN8_PPAT_UC,
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[1] = GEN8_PPAT_WC,
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[2] = GEN8_PPAT_WT,
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[3] = GEN8_PPAT_WB,
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[4] = GEN12_PPAT_CLOS(1) | GEN8_PPAT_WT,
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[5] = GEN12_PPAT_CLOS(1) | GEN8_PPAT_WB,
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[6] = GEN12_PPAT_CLOS(2) | GEN8_PPAT_WT,
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[7] = GEN12_PPAT_CLOS(2) | GEN8_PPAT_WB,
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[0] = TGL_PAT_UC,
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[1] = TGL_PAT_WC,
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[2] = TGL_PAT_WT,
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[3] = TGL_PAT_WB,
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[4] = PVC_PAT_CLOS(1) | TGL_PAT_WT,
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[5] = PVC_PAT_CLOS(1) | TGL_PAT_WB,
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[6] = PVC_PAT_CLOS(2) | TGL_PAT_WT,
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[7] = PVC_PAT_CLOS(2) | TGL_PAT_WB,
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};
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#define MTL_PPAT_L4_CACHE_POLICY_MASK REG_GENMASK(3, 2)
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#define MTL_PAT_INDEX_COH_MODE_MASK REG_GENMASK(1, 0)
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#define MTL_PPAT_3_UC REG_FIELD_PREP(MTL_PPAT_L4_CACHE_POLICY_MASK, 3)
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#define MTL_PPAT_1_WT REG_FIELD_PREP(MTL_PPAT_L4_CACHE_POLICY_MASK, 1)
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#define MTL_PPAT_0_WB REG_FIELD_PREP(MTL_PPAT_L4_CACHE_POLICY_MASK, 0)
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#define MTL_3_COH_2W REG_FIELD_PREP(MTL_PAT_INDEX_COH_MODE_MASK, 3)
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#define MTL_2_COH_1W REG_FIELD_PREP(MTL_PAT_INDEX_COH_MODE_MASK, 2)
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#define MTL_0_COH_NON REG_FIELD_PREP(MTL_PAT_INDEX_COH_MODE_MASK, 0)
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const u32 mtl_pat_table[] = {
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[0] = MTL_PPAT_0_WB,
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[1] = MTL_PPAT_1_WT | MTL_2_COH_1W,
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[2] = MTL_PPAT_3_UC | MTL_2_COH_1W,
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[3] = MTL_PPAT_0_WB | MTL_2_COH_1W,
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[4] = MTL_PPAT_0_WB | MTL_3_COH_2W,
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[0] = MTL_PAT_0_WB,
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[1] = MTL_PAT_1_WT | MTL_2_COH_1W,
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[2] = MTL_PAT_3_UC | MTL_2_COH_1W,
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[3] = MTL_PAT_0_WB | MTL_2_COH_1W,
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[4] = MTL_PAT_0_WB | MTL_3_COH_2W,
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};
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#define PROGRAM_PAT_UNICAST(gt, table) do { \