+64

Documentation/devicetree/bindings/clock/rockchip,rk3528-cru.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/clock/rockchip,rk3528-cru.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: Rockchip RK3528 Clock and Reset Controller 8 8 + 9 9 + maintainers: 10 10 + - Yao Zi <ziyao@disroot.org> 11 11 + 12 12 + description: | 13 13 + The RK3528 clock controller generates the clock and also implements a reset 14 14 + controller for SoC peripherals. For example, it provides SCLK_UART0 and 15 15 + PCLK_UART0 as well as SRST_P_UART0 and SRST_S_UART0 for the first UART 16 16 + module. 17 17 + Each clock is assigned an identifier, consumer nodes can use it to specify 18 18 + the clock. All available clock and reset IDs are defined in dt-binding 19 19 + headers. 20 20 + 21 21 + properties: 22 22 + compatible: 23 23 + const: rockchip,rk3528-cru 24 24 + 25 25 + reg: 26 26 + maxItems: 1 27 27 + 28 28 + clocks: 29 29 + items: 30 30 + - description: External 24MHz oscillator clock 31 31 + - description: > 32 32 + 50MHz clock generated by PHY module, for generating GMAC0 clocks only. 33 33 + 34 34 + clock-names: 35 35 + items: 36 36 + - const: xin24m 37 37 + - const: gmac0 38 38 + 39 39 + "#clock-cells": 40 40 + const: 1 41 41 + 42 42 + "#reset-cells": 43 43 + const: 1 44 44 + 45 45 + required: 46 46 + - compatible 47 47 + - reg 48 48 + - clocks 49 49 + - clock-names 50 50 + - "#clock-cells" 51 51 + - "#reset-cells" 52 52 + 53 53 + additionalProperties: false 54 54 + 55 55 + examples: 56 56 + - | 57 57 + clock-controller@ff4a0000 { 58 58 + compatible = "rockchip,rk3528-cru"; 59 59 + reg = <0xff4a0000 0x30000>; 60 60 + clocks = <&xin24m>, <&gmac0_clk>; 61 61 + clock-names = "xin24m", "gmac0"; 62 62 + #clock-cells = <1>; 63 63 + #reset-cells = <1>; 64 64 + };

+453

include/dt-bindings/clock/rockchip,rk3528-cru.h

reviewed

··· 1 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ 2 2 + /* 3 3 + * Copyright (c) 2022 Rockchip Electronics Co. Ltd. 4 4 + * Copyright (c) 2024 Yao Zi <ziyao@disroot.org> 5 5 + * Author: Joseph Chen <chenjh@rock-chips.com> 6 6 + */ 7 7 + 8 8 + #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H 9 9 + #define _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H 10 10 + 11 11 + /* cru-clocks indices */ 12 12 + #define PLL_APLL 0 13 13 + #define PLL_CPLL 1 14 14 + #define PLL_GPLL 2 15 15 + #define PLL_PPLL 3 16 16 + #define PLL_DPLL 4 17 17 + #define ARMCLK 5 18 18 + #define XIN_OSC0_HALF 6 19 19 + #define CLK_MATRIX_50M_SRC 7 20 20 + #define CLK_MATRIX_100M_SRC 8 21 21 + #define CLK_MATRIX_150M_SRC 9 22 22 + #define CLK_MATRIX_200M_SRC 10 23 23 + #define CLK_MATRIX_250M_SRC 11 24 24 + #define CLK_MATRIX_300M_SRC 12 25 25 + #define CLK_MATRIX_339M_SRC 13 26 26 + #define CLK_MATRIX_400M_SRC 14 27 27 + #define CLK_MATRIX_500M_SRC 15 28 28 + #define CLK_MATRIX_600M_SRC 16 29 29 + #define CLK_UART0_SRC 17 30 30 + #define CLK_UART0_FRAC 18 31 31 + #define SCLK_UART0 19 32 32 + #define CLK_UART1_SRC 20 33 33 + #define CLK_UART1_FRAC 21 34 34 + #define SCLK_UART1 22 35 35 + #define CLK_UART2_SRC 23 36 36 + #define CLK_UART2_FRAC 24 37 37 + #define SCLK_UART2 25 38 38 + #define CLK_UART3_SRC 26 39 39 + #define CLK_UART3_FRAC 27 40 40 + #define SCLK_UART3 28 41 41 + #define CLK_UART4_SRC 29 42 42 + #define CLK_UART4_FRAC 30 43 43 + #define SCLK_UART4 31 44 44 + #define CLK_UART5_SRC 32 45 45 + #define CLK_UART5_FRAC 33 46 46 + #define SCLK_UART5 34 47 47 + #define CLK_UART6_SRC 35 48 48 + #define CLK_UART6_FRAC 36 49 49 + #define SCLK_UART6 37 50 50 + #define CLK_UART7_SRC 38 51 51 + #define CLK_UART7_FRAC 39 52 52 + #define SCLK_UART7 40 53 53 + #define CLK_I2S0_2CH_SRC 41 54 54 + #define CLK_I2S0_2CH_FRAC 42 55 55 + #define MCLK_I2S0_2CH_SAI_SRC 43 56 56 + #define CLK_I2S3_8CH_SRC 44 57 57 + #define CLK_I2S3_8CH_FRAC 45 58 58 + #define MCLK_I2S3_8CH_SAI_SRC 46 59 59 + #define CLK_I2S1_8CH_SRC 47 60 60 + #define CLK_I2S1_8CH_FRAC 48 61 61 + #define MCLK_I2S1_8CH_SAI_SRC 49 62 62 + #define CLK_I2S2_2CH_SRC 50 63 63 + #define CLK_I2S2_2CH_FRAC 51 64 64 + #define MCLK_I2S2_2CH_SAI_SRC 52 65 65 + #define CLK_SPDIF_SRC 53 66 66 + #define CLK_SPDIF_FRAC 54 67 67 + #define MCLK_SPDIF_SRC 55 68 68 + #define DCLK_VOP_SRC0 56 69 69 + #define DCLK_VOP_SRC1 57 70 70 + #define CLK_HSM 58 71 71 + #define CLK_CORE_SRC_ACS 59 72 72 + #define CLK_CORE_SRC_PVTMUX 60 73 73 + #define CLK_CORE_SRC 61 74 74 + #define CLK_CORE 62 75 75 + #define ACLK_M_CORE_BIU 63 76 76 + #define CLK_CORE_PVTPLL_SRC 64 77 77 + #define PCLK_DBG 65 78 78 + #define SWCLKTCK 66 79 79 + #define CLK_SCANHS_CORE 67 80 80 + #define CLK_SCANHS_ACLKM_CORE 68 81 81 + #define CLK_SCANHS_PCLK_DBG 69 82 82 + #define CLK_SCANHS_PCLK_CPU_BIU 70 83 83 + #define PCLK_CPU_ROOT 71 84 84 + #define PCLK_CORE_GRF 72 85 85 + #define PCLK_DAPLITE_BIU 73 86 86 + #define PCLK_CPU_BIU 74 87 87 + #define CLK_REF_PVTPLL_CORE 75 88 88 + #define ACLK_BUS_VOPGL_ROOT 76 89 89 + #define ACLK_BUS_VOPGL_BIU 77 90 90 + #define ACLK_BUS_H_ROOT 78 91 91 + #define ACLK_BUS_H_BIU 79 92 92 + #define ACLK_BUS_ROOT 80 93 93 + #define HCLK_BUS_ROOT 81 94 94 + #define PCLK_BUS_ROOT 82 95 95 + #define ACLK_BUS_M_ROOT 83 96 96 + #define ACLK_SYSMEM_BIU 84 97 97 + #define CLK_TIMER_ROOT 85 98 98 + #define ACLK_BUS_BIU 86 99 99 + #define HCLK_BUS_BIU 87 100 100 + #define PCLK_BUS_BIU 88 101 101 + #define PCLK_DFT2APB 89 102 102 + #define PCLK_BUS_GRF 90 103 103 + #define ACLK_BUS_M_BIU 91 104 104 + #define ACLK_GIC 92 105 105 + #define ACLK_SPINLOCK 93 106 106 + #define ACLK_DMAC 94 107 107 + #define PCLK_TIMER 95 108 108 + #define CLK_TIMER0 96 109 109 + #define CLK_TIMER1 97 110 110 + #define CLK_TIMER2 98 111 111 + #define CLK_TIMER3 99 112 112 + #define CLK_TIMER4 100 113 113 + #define CLK_TIMER5 101 114 114 + #define PCLK_JDBCK_DAP 102 115 115 + #define CLK_JDBCK_DAP 103 116 116 + #define PCLK_WDT_NS 104 117 117 + #define TCLK_WDT_NS 105 118 118 + #define HCLK_TRNG_NS 106 119 119 + #define PCLK_UART0 107 120 120 + #define PCLK_DMA2DDR 108 121 121 + #define ACLK_DMA2DDR 109 122 122 + #define PCLK_PWM0 110 123 123 + #define CLK_PWM0 111 124 124 + #define CLK_CAPTURE_PWM0 112 125 125 + #define PCLK_PWM1 113 126 126 + #define CLK_PWM1 114 127 127 + #define CLK_CAPTURE_PWM1 115 128 128 + #define PCLK_SCR 116 129 129 + #define ACLK_DCF 117 130 130 + #define PCLK_INTMUX 118 131 131 + #define CLK_PPLL_I 119 132 132 + #define CLK_PPLL_MUX 120 133 133 + #define CLK_PPLL_100M_MATRIX 121 134 134 + #define CLK_PPLL_50M_MATRIX 122 135 135 + #define CLK_REF_PCIE_INNER_PHY 123 136 136 + #define CLK_REF_PCIE_100M_PHY 124 137 137 + #define ACLK_VPU_L_ROOT 125 138 138 + #define CLK_GMAC1_VPU_25M 126 139 139 + #define CLK_PPLL_125M_MATRIX 127 140 140 + #define ACLK_VPU_ROOT 128 141 141 + #define HCLK_VPU_ROOT 129 142 142 + #define PCLK_VPU_ROOT 130 143 143 + #define ACLK_VPU_BIU 131 144 144 + #define HCLK_VPU_BIU 132 145 145 + #define PCLK_VPU_BIU 133 146 146 + #define ACLK_VPU 134 147 147 + #define HCLK_VPU 135 148 148 + #define PCLK_CRU_PCIE 136 149 149 + #define PCLK_VPU_GRF 137 150 150 + #define HCLK_SFC 138 151 151 + #define SCLK_SFC 139 152 152 + #define CCLK_SRC_EMMC 140 153 153 + #define HCLK_EMMC 141 154 154 + #define ACLK_EMMC 142 155 155 + #define BCLK_EMMC 143 156 156 + #define TCLK_EMMC 144 157 157 + #define PCLK_GPIO1 145 158 158 + #define DBCLK_GPIO1 146 159 159 + #define ACLK_VPU_L_BIU 147 160 160 + #define PCLK_VPU_IOC 148 161 161 + #define HCLK_SAI_I2S0 149 162 162 + #define MCLK_SAI_I2S0 150 163 163 + #define HCLK_SAI_I2S2 151 164 164 + #define MCLK_SAI_I2S2 152 165 165 + #define PCLK_ACODEC 153 166 166 + #define MCLK_ACODEC_TX 154 167 167 + #define PCLK_GPIO3 155 168 168 + #define DBCLK_GPIO3 156 169 169 + #define PCLK_SPI1 157 170 170 + #define CLK_SPI1 158 171 171 + #define SCLK_IN_SPI1 159 172 172 + #define PCLK_UART2 160 173 173 + #define PCLK_UART5 161 174 174 + #define PCLK_UART6 162 175 175 + #define PCLK_UART7 163 176 176 + #define PCLK_I2C3 164 177 177 + #define CLK_I2C3 165 178 178 + #define PCLK_I2C5 166 179 179 + #define CLK_I2C5 167 180 180 + #define PCLK_I2C6 168 181 181 + #define CLK_I2C6 169 182 182 + #define ACLK_MAC_VPU 170 183 183 + #define PCLK_MAC_VPU 171 184 184 + #define CLK_GMAC1_RMII_VPU 172 185 185 + #define CLK_GMAC1_SRC_VPU 173 186 186 + #define PCLK_PCIE 174 187 187 + #define CLK_PCIE_AUX 175 188 188 + #define ACLK_PCIE 176 189 189 + #define HCLK_PCIE_SLV 177 190 190 + #define HCLK_PCIE_DBI 178 191 191 + #define PCLK_PCIE_PHY 179 192 192 + #define PCLK_PIPE_GRF 180 193 193 + #define CLK_PIPE_USB3OTG_COMBO 181 194 194 + #define CLK_UTMI_USB3OTG 182 195 195 + #define CLK_PCIE_PIPE_PHY 183 196 196 + #define CCLK_SRC_SDIO0 184 197 197 + #define HCLK_SDIO0 185 198 198 + #define CCLK_SRC_SDIO1 186 199 199 + #define HCLK_SDIO1 187 200 200 + #define CLK_TS_0 188 201 201 + #define CLK_TS_1 189 202 202 + #define PCLK_CAN2 190 203 203 + #define CLK_CAN2 191 204 204 + #define PCLK_CAN3 192 205 205 + #define CLK_CAN3 193 206 206 + #define PCLK_SARADC 194 207 207 + #define CLK_SARADC 195 208 208 + #define PCLK_TSADC 196 209 209 + #define CLK_TSADC 197 210 210 + #define CLK_TSADC_TSEN 198 211 211 + #define ACLK_USB3OTG 199 212 212 + #define CLK_REF_USB3OTG 200 213 213 + #define CLK_SUSPEND_USB3OTG 201 214 214 + #define ACLK_GPU_ROOT 202 215 215 + #define PCLK_GPU_ROOT 203 216 216 + #define ACLK_GPU_BIU 204 217 217 + #define PCLK_GPU_BIU 205 218 218 + #define ACLK_GPU 206 219 219 + #define CLK_GPU_PVTPLL_SRC 207 220 220 + #define ACLK_GPU_MALI 208 221 221 + #define HCLK_RKVENC_ROOT 209 222 222 + #define ACLK_RKVENC_ROOT 210 223 223 + #define PCLK_RKVENC_ROOT 211 224 224 + #define HCLK_RKVENC_BIU 212 225 225 + #define ACLK_RKVENC_BIU 213 226 226 + #define PCLK_RKVENC_BIU 214 227 227 + #define HCLK_RKVENC 215 228 228 + #define ACLK_RKVENC 216 229 229 + #define CLK_CORE_RKVENC 217 230 230 + #define HCLK_SAI_I2S1 218 231 231 + #define MCLK_SAI_I2S1 219 232 232 + #define PCLK_I2C1 220 233 233 + #define CLK_I2C1 221 234 234 + #define PCLK_I2C0 222 235 235 + #define CLK_I2C0 223 236 236 + #define CLK_UART_JTAG 224 237 237 + #define PCLK_SPI0 225 238 238 + #define CLK_SPI0 226 239 239 + #define SCLK_IN_SPI0 227 240 240 + #define PCLK_GPIO4 228 241 241 + #define DBCLK_GPIO4 229 242 242 + #define PCLK_RKVENC_IOC 230 243 243 + #define HCLK_SPDIF 231 244 244 + #define MCLK_SPDIF 232 245 245 + #define HCLK_PDM 233 246 246 + #define MCLK_PDM 234 247 247 + #define PCLK_UART1 235 248 248 + #define PCLK_UART3 236 249 249 + #define PCLK_RKVENC_GRF 237 250 250 + #define PCLK_CAN0 238 251 251 + #define CLK_CAN0 239 252 252 + #define PCLK_CAN1 240 253 253 + #define CLK_CAN1 241 254 254 + #define ACLK_VO_ROOT 242 255 255 + #define HCLK_VO_ROOT 243 256 256 + #define PCLK_VO_ROOT 244 257 257 + #define ACLK_VO_BIU 245 258 258 + #define HCLK_VO_BIU 246 259 259 + #define PCLK_VO_BIU 247 260 260 + #define HCLK_RGA2E 248 261 261 + #define ACLK_RGA2E 249 262 262 + #define CLK_CORE_RGA2E 250 263 263 + #define HCLK_VDPP 251 264 264 + #define ACLK_VDPP 252 265 265 + #define CLK_CORE_VDPP 253 266 266 + #define PCLK_VO_GRF 254 267 267 + #define PCLK_CRU 255 268 268 + #define ACLK_VOP_ROOT 256 269 269 + #define ACLK_VOP_BIU 257 270 270 + #define HCLK_VOP 258 271 271 + #define DCLK_VOP0 259 272 272 + #define DCLK_VOP1 260 273 273 + #define ACLK_VOP 261 274 274 + #define PCLK_HDMI 262 275 275 + #define CLK_SFR_HDMI 263 276 276 + #define CLK_CEC_HDMI 264 277 277 + #define CLK_SPDIF_HDMI 265 278 278 + #define CLK_HDMIPHY_TMDSSRC 266 279 279 + #define CLK_HDMIPHY_PREP 267 280 280 + #define PCLK_HDMIPHY 268 281 281 + #define HCLK_HDCP_KEY 269 282 282 + #define ACLK_HDCP 270 283 283 + #define HCLK_HDCP 271 284 284 + #define PCLK_HDCP 272 285 285 + #define HCLK_CVBS 273 286 286 + #define DCLK_CVBS 274 287 287 + #define DCLK_4X_CVBS 275 288 288 + #define ACLK_JPEG_DECODER 276 289 289 + #define HCLK_JPEG_DECODER 277 290 290 + #define ACLK_VO_L_ROOT 278 291 291 + #define ACLK_VO_L_BIU 279 292 292 + #define ACLK_MAC_VO 280 293 293 + #define PCLK_MAC_VO 281 294 294 + #define CLK_GMAC0_SRC 282 295 295 + #define CLK_GMAC0_RMII_50M 283 296 296 + #define CLK_GMAC0_TX 284 297 297 + #define CLK_GMAC0_RX 285 298 298 + #define ACLK_JPEG_ROOT 286 299 299 + #define ACLK_JPEG_BIU 287 300 300 + #define HCLK_SAI_I2S3 288 301 301 + #define MCLK_SAI_I2S3 289 302 302 + #define CLK_MACPHY 290 303 303 + #define PCLK_VCDCPHY 291 304 304 + #define PCLK_GPIO2 292 305 305 + #define DBCLK_GPIO2 293 306 306 + #define PCLK_VO_IOC 294 307 307 + #define CCLK_SRC_SDMMC0 295 308 308 + #define HCLK_SDMMC0 296 309 309 + #define PCLK_OTPC_NS 297 310 310 + #define CLK_SBPI_OTPC_NS 298 311 311 + #define CLK_USER_OTPC_NS 299 312 312 + #define CLK_HDMIHDP0 300 313 313 + #define HCLK_USBHOST 301 314 314 + #define HCLK_USBHOST_ARB 302 315 315 + #define CLK_USBHOST_OHCI 303 316 316 + #define CLK_USBHOST_UTMI 304 317 317 + #define PCLK_UART4 305 318 318 + #define PCLK_I2C4 306 319 319 + #define CLK_I2C4 307 320 320 + #define PCLK_I2C7 308 321 321 + #define CLK_I2C7 309 322 322 + #define PCLK_USBPHY 310 323 323 + #define CLK_REF_USBPHY 311 324 324 + #define HCLK_RKVDEC_ROOT 312 325 325 + #define ACLK_RKVDEC_ROOT_NDFT 313 326 326 + #define PCLK_DDRPHY_CRU 314 327 327 + #define HCLK_RKVDEC_BIU 315 328 328 + #define ACLK_RKVDEC_BIU 316 329 329 + #define ACLK_RKVDEC 317 330 330 + #define HCLK_RKVDEC 318 331 331 + #define CLK_HEVC_CA_RKVDEC 319 332 332 + #define ACLK_RKVDEC_PVTMUX_ROOT 320 333 333 + #define CLK_RKVDEC_PVTPLL_SRC 321 334 334 + #define PCLK_DDR_ROOT 322 335 335 + #define PCLK_DDR_BIU 323 336 336 + #define PCLK_DDRC 324 337 337 + #define PCLK_DDRMON 325 338 338 + #define CLK_TIMER_DDRMON 326 339 339 + #define PCLK_MSCH_BIU 327 340 340 + #define PCLK_DDR_GRF 328 341 341 + #define PCLK_DDR_HWLP 329 342 342 + #define PCLK_DDRPHY 330 343 343 + #define CLK_MSCH_BIU 331 344 344 + #define ACLK_DDR_UPCTL 332 345 345 + #define CLK_DDR_UPCTL 333 346 346 + #define CLK_DDRMON 334 347 347 + #define ACLK_DDR_SCRAMBLE 335 348 348 + #define ACLK_SPLIT 336 349 349 + #define CLK_DDRC_SRC 337 350 350 + #define CLK_DDR_PHY 338 351 351 + #define PCLK_OTPC_S 339 352 352 + #define CLK_SBPI_OTPC_S 340 353 353 + #define CLK_USER_OTPC_S 341 354 354 + #define PCLK_KEYREADER 342 355 355 + #define PCLK_BUS_SGRF 343 356 356 + #define PCLK_STIMER 344 357 357 + #define CLK_STIMER0 345 358 358 + #define CLK_STIMER1 346 359 359 + #define PCLK_WDT_S 347 360 360 + #define TCLK_WDT_S 348 361 361 + #define HCLK_TRNG_S 349 362 362 + #define HCLK_BOOTROM 350 363 363 + #define PCLK_DCF 351 364 364 + #define ACLK_SYSMEM 352 365 365 + #define HCLK_TSP 353 366 366 + #define ACLK_TSP 354 367 367 + #define CLK_CORE_TSP 355 368 368 + #define CLK_OTPC_ARB 356 369 369 + #define PCLK_OTP_MASK 357 370 370 + #define CLK_PMC_OTP 358 371 371 + #define PCLK_PMU_ROOT 359 372 372 + #define HCLK_PMU_ROOT 360 373 373 + #define PCLK_I2C2 361 374 374 + #define CLK_I2C2 362 375 375 + #define HCLK_PMU_BIU 363 376 376 + #define PCLK_PMU_BIU 364 377 377 + #define FCLK_MCU 365 378 378 + #define RTC_CLK_MCU 366 379 379 + #define PCLK_OSCCHK 367 380 380 + #define CLK_PMU_MCU_JTAG 368 381 381 + #define PCLK_PMU 369 382 382 + #define PCLK_GPIO0 370 383 383 + #define DBCLK_GPIO0 371 384 384 + #define XIN_OSC0_DIV 372 385 385 + #define CLK_DEEPSLOW 373 386 386 + #define CLK_DDR_FAIL_SAFE 374 387 387 + #define PCLK_PMU_HP_TIMER 375 388 388 + #define CLK_PMU_HP_TIMER 376 389 389 + #define CLK_PMU_32K_HP_TIMER 377 390 390 + #define PCLK_PMU_IOC 378 391 391 + #define PCLK_PMU_CRU 379 392 392 + #define PCLK_PMU_GRF 380 393 393 + #define PCLK_PMU_WDT 381 394 394 + #define TCLK_PMU_WDT 382 395 395 + #define PCLK_PMU_MAILBOX 383 396 396 + #define PCLK_SCRKEYGEN 384 397 397 + #define CLK_SCRKEYGEN 385 398 398 + #define CLK_PVTM_OSCCHK 386 399 399 + #define CLK_REFOUT 387 400 400 + #define CLK_PVTM_PMU 388 401 401 + #define PCLK_PVTM_PMU 389 402 402 + #define PCLK_PMU_SGRF 390 403 403 + #define HCLK_PMU_SRAM 391 404 404 + #define CLK_UART0 392 405 405 + #define CLK_UART1 393 406 406 + #define CLK_UART2 394 407 407 + #define CLK_UART3 395 408 408 + #define CLK_UART4 396 409 409 + #define CLK_UART5 397 410 410 + #define CLK_UART6 398 411 411 + #define CLK_UART7 399 412 412 + #define MCLK_I2S0_2CH_SAI_SRC_PRE 400 413 413 + #define MCLK_I2S1_8CH_SAI_SRC_PRE 401 414 414 + #define MCLK_I2S2_2CH_SAI_SRC_PRE 402 415 415 + #define MCLK_I2S3_8CH_SAI_SRC_PRE 403 416 416 + #define MCLK_SDPDIF_SRC_PRE 404 417 417 + 418 418 + /* scmi-clocks indices */ 419 419 + #define SCMI_PCLK_KEYREADER 0 420 420 + #define SCMI_HCLK_KLAD 1 421 421 + #define SCMI_PCLK_KLAD 2 422 422 + #define SCMI_HCLK_TRNG_S 3 423 423 + #define SCMI_HCLK_CRYPTO_S 4 424 424 + #define SCMI_PCLK_WDT_S 5 425 425 + #define SCMI_TCLK_WDT_S 6 426 426 + #define SCMI_PCLK_STIMER 7 427 427 + #define SCMI_CLK_STIMER0 8 428 428 + #define SCMI_CLK_STIMER1 9 429 429 + #define SCMI_PCLK_OTP_MASK 10 430 430 + #define SCMI_PCLK_OTPC_S 11 431 431 + #define SCMI_CLK_SBPI_OTPC_S 12 432 432 + #define SCMI_CLK_USER_OTPC_S 13 433 433 + #define SCMI_CLK_PMC_OTP 14 434 434 + #define SCMI_CLK_OTPC_ARB 15 435 435 + #define SCMI_CLK_CORE_TSP 16 436 436 + #define SCMI_ACLK_TSP 17 437 437 + #define SCMI_HCLK_TSP 18 438 438 + #define SCMI_PCLK_DCF 19 439 439 + #define SCMI_CLK_DDR 20 440 440 + #define SCMI_CLK_CPU 21 441 441 + #define SCMI_CLK_GPU 22 442 442 + #define SCMI_CORE_CRYPTO 23 443 443 + #define SCMI_ACLK_CRYPTO 24 444 444 + #define SCMI_PKA_CRYPTO 25 445 445 + #define SCMI_HCLK_CRYPTO 26 446 446 + #define SCMI_CORE_CRYPTO_S 27 447 447 + #define SCMI_ACLK_CRYPTO_S 28 448 448 + #define SCMI_PKA_CRYPTO_S 29 449 449 + #define SCMI_CORE_KLAD 30 450 450 + #define SCMI_ACLK_KLAD 31 451 451 + #define SCMI_HCLK_TRNG 32 452 452 + 453 453 + #endif // _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H

+241

include/dt-bindings/reset/rockchip,rk3528-cru.h

reviewed

··· 1 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ 2 2 + /* 3 3 + * Copyright (c) 2022 Rockchip Electronics Co. Ltd. 4 4 + * Copyright (c) 2024 Yao Zi <ziyao@disroot.org> 5 5 + * Author: Joseph Chen <chenjh@rock-chips.com> 6 6 + */ 7 7 + 8 8 + #ifndef _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H 9 9 + #define _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H 10 10 + 11 11 + #define SRST_CORE0_PO 0 12 12 + #define SRST_CORE1_PO 1 13 13 + #define SRST_CORE2_PO 2 14 14 + #define SRST_CORE3_PO 3 15 15 + #define SRST_CORE0 4 16 16 + #define SRST_CORE1 5 17 17 + #define SRST_CORE2 6 18 18 + #define SRST_CORE3 7 19 19 + #define SRST_NL2 8 20 20 + #define SRST_CORE_BIU 9 21 21 + #define SRST_CORE_CRYPTO 10 22 22 + #define SRST_P_DBG 11 23 23 + #define SRST_POT_DBG 12 24 24 + #define SRST_NT_DBG 13 25 25 + #define SRST_P_CORE_GRF 14 26 26 + #define SRST_P_DAPLITE_BIU 15 27 27 + #define SRST_P_CPU_BIU 16 28 28 + #define SRST_REF_PVTPLL_CORE 17 29 29 + #define SRST_A_BUS_VOPGL_BIU 18 30 30 + #define SRST_A_BUS_H_BIU 19 31 31 + #define SRST_A_SYSMEM_BIU 20 32 32 + #define SRST_A_BUS_BIU 21 33 33 + #define SRST_H_BUS_BIU 22 34 34 + #define SRST_P_BUS_BIU 23 35 35 + #define SRST_P_DFT2APB 24 36 36 + #define SRST_P_BUS_GRF 25 37 37 + #define SRST_A_BUS_M_BIU 26 38 38 + #define SRST_A_GIC 27 39 39 + #define SRST_A_SPINLOCK 28 40 40 + #define SRST_A_DMAC 29 41 41 + #define SRST_P_TIMER 30 42 42 + #define SRST_TIMER0 31 43 43 + #define SRST_TIMER1 32 44 44 + #define SRST_TIMER2 33 45 45 + #define SRST_TIMER3 34 46 46 + #define SRST_TIMER4 35 47 47 + #define SRST_TIMER5 36 48 48 + #define SRST_P_JDBCK_DAP 37 49 49 + #define SRST_JDBCK_DAP 38 50 50 + #define SRST_P_WDT_NS 39 51 51 + #define SRST_T_WDT_NS 40 52 52 + #define SRST_H_TRNG_NS 41 53 53 + #define SRST_P_UART0 42 54 54 + #define SRST_S_UART0 43 55 55 + #define SRST_PKA_CRYPTO 44 56 56 + #define SRST_A_CRYPTO 45 57 57 + #define SRST_H_CRYPTO 46 58 58 + #define SRST_P_DMA2DDR 47 59 59 + #define SRST_A_DMA2DDR 48 60 60 + #define SRST_P_PWM0 49 61 61 + #define SRST_PWM0 50 62 62 + #define SRST_P_PWM1 51 63 63 + #define SRST_PWM1 52 64 64 + #define SRST_P_SCR 53 65 65 + #define SRST_A_DCF 54 66 66 + #define SRST_P_INTMUX 55 67 67 + #define SRST_A_VPU_BIU 56 68 68 + #define SRST_H_VPU_BIU 57 69 69 + #define SRST_P_VPU_BIU 58 70 70 + #define SRST_A_VPU 59 71 71 + #define SRST_H_VPU 60 72 72 + #define SRST_P_CRU_PCIE 61 73 73 + #define SRST_P_VPU_GRF 62 74 74 + #define SRST_H_SFC 63 75 75 + #define SRST_S_SFC 64 76 76 + #define SRST_C_EMMC 65 77 77 + #define SRST_H_EMMC 66 78 78 + #define SRST_A_EMMC 67 79 79 + #define SRST_B_EMMC 68 80 80 + #define SRST_T_EMMC 69 81 81 + #define SRST_P_GPIO1 70 82 82 + #define SRST_DB_GPIO1 71 83 83 + #define SRST_A_VPU_L_BIU 72 84 84 + #define SRST_P_VPU_IOC 73 85 85 + #define SRST_H_SAI_I2S0 74 86 86 + #define SRST_M_SAI_I2S0 75 87 87 + #define SRST_H_SAI_I2S2 76 88 88 + #define SRST_M_SAI_I2S2 77 89 89 + #define SRST_P_ACODEC 78 90 90 + #define SRST_P_GPIO3 79 91 91 + #define SRST_DB_GPIO3 80 92 92 + #define SRST_P_SPI1 81 93 93 + #define SRST_SPI1 82 94 94 + #define SRST_P_UART2 83 95 95 + #define SRST_S_UART2 84 96 96 + #define SRST_P_UART5 85 97 97 + #define SRST_S_UART5 86 98 98 + #define SRST_P_UART6 87 99 99 + #define SRST_S_UART6 88 100 100 + #define SRST_P_UART7 89 101 101 + #define SRST_S_UART7 90 102 102 + #define SRST_P_I2C3 91 103 103 + #define SRST_I2C3 92 104 104 + #define SRST_P_I2C5 93 105 105 + #define SRST_I2C5 94 106 106 + #define SRST_P_I2C6 95 107 107 + #define SRST_I2C6 96 108 108 + #define SRST_A_MAC 97 109 109 + #define SRST_P_PCIE 98 110 110 + #define SRST_PCIE_PIPE_PHY 99 111 111 + #define SRST_PCIE_POWER_UP 100 112 112 + #define SRST_P_PCIE_PHY 101 113 113 + #define SRST_P_PIPE_GRF 102 114 114 + #define SRST_H_SDIO0 103 115 115 + #define SRST_H_SDIO1 104 116 116 + #define SRST_TS_0 105 117 117 + #define SRST_TS_1 106 118 118 + #define SRST_P_CAN2 107 119 119 + #define SRST_CAN2 108 120 120 + #define SRST_P_CAN3 109 121 121 + #define SRST_CAN3 110 122 122 + #define SRST_P_SARADC 111 123 123 + #define SRST_SARADC 112 124 124 + #define SRST_SARADC_PHY 113 125 125 + #define SRST_P_TSADC 114 126 126 + #define SRST_TSADC 115 127 127 + #define SRST_A_USB3OTG 116 128 128 + #define SRST_A_GPU_BIU 117 129 129 + #define SRST_P_GPU_BIU 118 130 130 + #define SRST_A_GPU 119 131 131 + #define SRST_REF_PVTPLL_GPU 120 132 132 + #define SRST_H_RKVENC_BIU 121 133 133 + #define SRST_A_RKVENC_BIU 122 134 134 + #define SRST_P_RKVENC_BIU 123 135 135 + #define SRST_H_RKVENC 124 136 136 + #define SRST_A_RKVENC 125 137 137 + #define SRST_CORE_RKVENC 126 138 138 + #define SRST_H_SAI_I2S1 127 139 139 + #define SRST_M_SAI_I2S1 128 140 140 + #define SRST_P_I2C1 129 141 141 + #define SRST_I2C1 130 142 142 + #define SRST_P_I2C0 131 143 143 + #define SRST_I2C0 132 144 144 + #define SRST_P_SPI0 133 145 145 + #define SRST_SPI0 134 146 146 + #define SRST_P_GPIO4 135 147 147 + #define SRST_DB_GPIO4 136 148 148 + #define SRST_P_RKVENC_IOC 137 149 149 + #define SRST_H_SPDIF 138 150 150 + #define SRST_M_SPDIF 139 151 151 + #define SRST_H_PDM 140 152 152 + #define SRST_M_PDM 141 153 153 + #define SRST_P_UART1 142 154 154 + #define SRST_S_UART1 143 155 155 + #define SRST_P_UART3 144 156 156 + #define SRST_S_UART3 145 157 157 + #define SRST_P_RKVENC_GRF 146 158 158 + #define SRST_P_CAN0 147 159 159 + #define SRST_CAN0 148 160 160 + #define SRST_P_CAN1 149 161 161 + #define SRST_CAN1 150 162 162 + #define SRST_A_VO_BIU 151 163 163 + #define SRST_H_VO_BIU 152 164 164 + #define SRST_P_VO_BIU 153 165 165 + #define SRST_H_RGA2E 154 166 166 + #define SRST_A_RGA2E 155 167 167 + #define SRST_CORE_RGA2E 156 168 168 + #define SRST_H_VDPP 157 169 169 + #define SRST_A_VDPP 158 170 170 + #define SRST_CORE_VDPP 159 171 171 + #define SRST_P_VO_GRF 160 172 172 + #define SRST_P_CRU 161 173 173 + #define SRST_A_VOP_BIU 162 174 174 + #define SRST_H_VOP 163 175 175 + #define SRST_D_VOP0 164 176 176 + #define SRST_D_VOP1 165 177 177 + #define SRST_A_VOP 166 178 178 + #define SRST_P_HDMI 167 179 179 + #define SRST_HDMI 168 180 180 + #define SRST_P_HDMIPHY 169 181 181 + #define SRST_H_HDCP_KEY 170 182 182 + #define SRST_A_HDCP 171 183 183 + #define SRST_H_HDCP 172 184 184 + #define SRST_P_HDCP 173 185 185 + #define SRST_H_CVBS 174 186 186 + #define SRST_D_CVBS_VOP 175 187 187 + #define SRST_D_4X_CVBS_VOP 176 188 188 + #define SRST_A_JPEG_DECODER 177 189 189 + #define SRST_H_JPEG_DECODER 178 190 190 + #define SRST_A_VO_L_BIU 179 191 191 + #define SRST_A_MAC_VO 180 192 192 + #define SRST_A_JPEG_BIU 181 193 193 + #define SRST_H_SAI_I2S3 182 194 194 + #define SRST_M_SAI_I2S3 183 195 195 + #define SRST_MACPHY 184 196 196 + #define SRST_P_VCDCPHY 185 197 197 + #define SRST_P_GPIO2 186 198 198 + #define SRST_DB_GPIO2 187 199 199 + #define SRST_P_VO_IOC 188 200 200 + #define SRST_H_SDMMC0 189 201 201 + #define SRST_P_OTPC_NS 190 202 202 + #define SRST_SBPI_OTPC_NS 191 203 203 + #define SRST_USER_OTPC_NS 192 204 204 + #define SRST_HDMIHDP0 193 205 205 + #define SRST_H_USBHOST 194 206 206 + #define SRST_H_USBHOST_ARB 195 207 207 + #define SRST_HOST_UTMI 196 208 208 + #define SRST_P_UART4 197 209 209 + #define SRST_S_UART4 198 210 210 + #define SRST_P_I2C4 199 211 211 + #define SRST_I2C4 200 212 212 + #define SRST_P_I2C7 201 213 213 + #define SRST_I2C7 202 214 214 + #define SRST_P_USBPHY 203 215 215 + #define SRST_USBPHY_POR 204 216 216 + #define SRST_USBPHY_OTG 205 217 217 + #define SRST_USBPHY_HOST 206 218 218 + #define SRST_P_DDRPHY_CRU 207 219 219 + #define SRST_H_RKVDEC_BIU 208 220 220 + #define SRST_A_RKVDEC_BIU 209 221 221 + #define SRST_A_RKVDEC 210 222 222 + #define SRST_H_RKVDEC 211 223 223 + #define SRST_HEVC_CA_RKVDEC 212 224 224 + #define SRST_REF_PVTPLL_RKVDEC 213 225 225 + #define SRST_P_DDR_BIU 214 226 226 + #define SRST_P_DDRC 215 227 227 + #define SRST_P_DDRMON 216 228 228 + #define SRST_TIMER_DDRMON 217 229 229 + #define SRST_P_MSCH_BIU 218 230 230 + #define SRST_P_DDR_GRF 219 231 231 + #define SRST_P_DDR_HWLP 220 232 232 + #define SRST_P_DDRPHY 221 233 233 + #define SRST_MSCH_BIU 222 234 234 + #define SRST_A_DDR_UPCTL 223 235 235 + #define SRST_DDR_UPCTL 224 236 236 + #define SRST_DDRMON 225 237 237 + #define SRST_A_DDR_SCRAMBLE 226 238 238 + #define SRST_A_SPLIT 227 239 239 + #define SRST_DDR_PHY 228 240 240 + 241 241 + #endif // _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H