tools headers: Sync x86 headers with kernel sources

To pick up changes from:

54de197c9a5e8f52 ("Merge tag 'x86_sgx_for_6.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip")
679fcce0028bf101 ("Merge tag 'kvm-x86-svm-6.19' of https://github.com/kvm-x86/linux into HEAD")
3767def18f4cc394 ("x86/cpufeatures: Add support for L3 Smart Data Cache Injection Allocation Enforcement")
f6106d41ec84e552 ("x86/bugs: Use an x86 feature to track the MMIO Stale Data mitigation")
7baadd463e147fdc ("x86/cpufeatures: Enumerate the LASS feature bits")
47955b58cf9b97fe ("x86/cpufeatures: Correct LKGS feature flag description")
5d0316e25defee47 ("x86/cpufeatures: Add X86_FEATURE_X2AVIC_EXT")
6ffdb49101f02313 ("x86/cpufeatures: Add X86_FEATURE_SGX_EUPDATESVN feature flag")
4793f990ea152330 ("KVM: x86: Advertise EferLmsleUnsupported to userspace")
bb5f13df3c455110 ("perf/x86/intel: Add counter group support for arch-PEBS")
52448a0a739002ec ("perf/x86/intel: Setup PEBS data configuration and enable legacy groups")
d21954c8a0ffbc94 ("perf/x86/intel: Process arch-PEBS records or record fragments")
bffeb2fd0b9c99d8 ("x86/microcode/intel: Enable staging when available")
740144bc6bde9d44 ("x86/microcode/intel: Establish staging control logic")

This should address these tools/perf build warnings:

Warning: Kernel ABI header differences:
diff -u tools/arch/x86/include/asm/cpufeatures.h arch/x86/include/asm/cpufeatures.h
diff -u tools/arch/x86/include/asm/msr-index.h arch/x86/include/asm/msr-index.h

Please see tools/include/uapi/README.

Cc: x86@kernel.org
Signed-off-by: Namhyung Kim <namhyung@kernel.org>

Namhyung Kim 4 months ago 369e91bd c4829931

+41

2 changed files

expand all

tools

arch

x86

include

asm

cpufeatures.h

msr-index.h

+11

tools/arch/x86/include/asm/cpufeatures.h

··· 314 314 #define X86_FEATURE_SM4 (12*32+ 2) /* SM4 instructions */ 315 315 #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* "avx_vnni" AVX VNNI instructions */ 316 316 #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* "avx512_bf16" AVX512 BFLOAT16 instructions */ 317 + #define X86_FEATURE_LASS (12*32+ 6) /* "lass" Linear Address Space Separation */ 317 318 #define X86_FEATURE_CMPCCXADD (12*32+ 7) /* CMPccXADD instructions */ 318 319 #define X86_FEATURE_ARCH_PERFMON_EXT (12*32+ 8) /* Intel Architectural PerfMon Extension */ 319 320 #define X86_FEATURE_FZRM (12*32+10) /* Fast zero-length REP MOVSB */ ··· 339 338 #define X86_FEATURE_AMD_STIBP (13*32+15) /* Single Thread Indirect Branch Predictors */ 340 339 #define X86_FEATURE_AMD_STIBP_ALWAYS_ON (13*32+17) /* Single Thread Indirect Branch Predictors always-on preferred */ 341 340 #define X86_FEATURE_AMD_IBRS_SAME_MODE (13*32+19) /* Indirect Branch Restricted Speculation same mode protection*/ 341 + #define X86_FEATURE_EFER_LMSLE_MBZ (13*32+20) /* EFER.LMSLE must be zero */ 342 342 #define X86_FEATURE_AMD_PPIN (13*32+23) /* "amd_ppin" Protected Processor Inventory Number */ 343 343 #define X86_FEATURE_AMD_SSBD (13*32+24) /* Speculative Store Bypass Disable */ 344 344 #define X86_FEATURE_VIRT_SSBD (13*32+25) /* "virt_ssbd" Virtualized Speculative Store Bypass Disable */ ··· 504 502 #define X86_FEATURE_IBPB_EXIT_TO_USER (21*32+14) /* Use IBPB on exit-to-userspace, see VMSCAPE bug */ 505 503 #define X86_FEATURE_ABMC (21*32+15) /* Assignable Bandwidth Monitoring Counters */ 506 504 #define X86_FEATURE_MSR_IMM (21*32+16) /* MSR immediate form instructions */ 505 + #define X86_FEATURE_SGX_EUPDATESVN (21*32+17) /* Support for ENCLS[EUPDATESVN] instruction */ 506 + 507 + #define X86_FEATURE_SDCIAE (21*32+18) /* L3 Smart Data Cache Injection Allocation Enforcement */ 508 + #define X86_FEATURE_CLEAR_CPU_BUF_VM_MMIO (21*32+19) /* 509 + * Clear CPU buffers before VM-Enter if the vCPU 510 + * can access host MMIO (ignored for all intents 511 + * and purposes if CLEAR_CPU_BUF_VM is set). 512 + */ 513 + #define X86_FEATURE_X2AVIC_EXT (21*32+20) /* AMD SVM x2AVIC support for 4k vCPUs */ 507 514 508 515 /* 509 516 * BUG word(s)

+30

tools/arch/x86/include/asm/msr-index.h

··· 166 166 * Processor MMIO stale data 167 167 * vulnerabilities. 168 168 */ 169 + #define ARCH_CAP_MCU_ENUM BIT(16) /* 170 + * Indicates the presence of microcode update 171 + * feature enumeration and status information. 172 + */ 169 173 #define ARCH_CAP_FB_CLEAR BIT(17) /* 170 174 * VERW clears CPU fill buffer 171 175 * even on MDS_NO CPUs. ··· 330 326 #define PERF_CAP_PEBS_MASK (PERF_CAP_PEBS_TRAP | PERF_CAP_ARCH_REG | \ 331 327 PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE | \ 332 328 PERF_CAP_PEBS_TIMING_INFO) 329 + 330 + /* Arch PEBS */ 331 + #define MSR_IA32_PEBS_BASE 0x000003f4 332 + #define MSR_IA32_PEBS_INDEX 0x000003f5 333 + #define ARCH_PEBS_OFFSET_MASK 0x7fffff 334 + #define ARCH_PEBS_INDEX_WR_SHIFT 4 335 + 336 + #define ARCH_PEBS_RELOAD 0xffffffff 337 + #define ARCH_PEBS_CNTR_ALLOW BIT_ULL(35) 338 + #define ARCH_PEBS_CNTR_GP BIT_ULL(36) 339 + #define ARCH_PEBS_CNTR_FIXED BIT_ULL(37) 340 + #define ARCH_PEBS_CNTR_METRICS BIT_ULL(38) 341 + #define ARCH_PEBS_LBR_SHIFT 40 342 + #define ARCH_PEBS_LBR (0x3ull << ARCH_PEBS_LBR_SHIFT) 343 + #define ARCH_PEBS_VECR_XMM BIT_ULL(49) 344 + #define ARCH_PEBS_GPR BIT_ULL(61) 345 + #define ARCH_PEBS_AUX BIT_ULL(62) 346 + #define ARCH_PEBS_EN BIT_ULL(63) 347 + #define ARCH_PEBS_CNTR_MASK (ARCH_PEBS_CNTR_GP | ARCH_PEBS_CNTR_FIXED | \ 348 + ARCH_PEBS_CNTR_METRICS) 333 349 334 350 #define MSR_IA32_RTIT_CTL 0x00000570 335 351 #define RTIT_CTL_TRACEEN BIT(0) ··· 953 929 #define MSR_IA32_APICBASE_BASE (0xfffff<<12) 954 930 955 931 #define MSR_IA32_UCODE_WRITE 0x00000079 932 + 933 + #define MSR_IA32_MCU_ENUMERATION 0x0000007b 934 + #define MCU_STAGING BIT(4) 935 + 956 936 #define MSR_IA32_UCODE_REV 0x0000008b 957 937 958 938 /* Intel SGX Launch Enclave Public Key Hash MSRs */ ··· 1253 1225 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 1254 1226 #define MSR_IA32_VMX_VMFUNC 0x00000491 1255 1227 #define MSR_IA32_VMX_PROCBASED_CTLS3 0x00000492 1228 + 1229 + #define MSR_IA32_MCU_STAGING_MBOX_ADDR 0x000007a5 1256 1230 1257 1231 /* Resctrl MSRs: */ 1258 1232 /* - Intel: */

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