Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu: Use get_smn_base in aqua_vanjaram
Use get_smn_base interface to get IP die instance's base offset in
aqua_vanjaram. encode_ext_smn_addressing is not used.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Lijo Lazar
and committed by
Alex Deucher
36a02456
467ebfe6
+87
-42
+4
-3
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+4
-3
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
···
21
21
*
22
22
*
23
23
*/
24
+
#include "amdgpu_reg_access.h"
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#include <linux/debugfs.h>
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#include <linux/list.h>
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#include <linux/module.h>
···
5536
5535
* is changed. In such case, replace the aqua_vanjaram implementation
5537
5536
* with more common helper */
5538
5537
reg_addr = (mmMP0_SMN_C2PMSG_92 << 2) +
5539
-
aqua_vanjaram_encode_ext_smn_addressing(instance);
5538
+
amdgpu_reg_get_smn_base64(adev, MP0_HWIP, instance);
5540
5539
fw_status = amdgpu_device_indirect_rreg_ext(adev, reg_addr);
5541
5540
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5541
reg_addr = (mmMP0_SMN_C2PMSG_126 << 2) +
5543
-
aqua_vanjaram_encode_ext_smn_addressing(instance);
5542
+
amdgpu_reg_get_smn_base64(adev, MP0_HWIP, instance);
5544
5543
boot_error = amdgpu_device_indirect_rreg_ext(adev, reg_addr);
5545
5544
5546
5545
socket_id = AMDGPU_RAS_GPU_ERR_SOCKET_ID(boot_error);
···
5606
5605
int retry_loop;
5607
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5608
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reg_addr = (mmMP0_SMN_C2PMSG_92 << 2) +
5609
-
aqua_vanjaram_encode_ext_smn_addressing(instance);
5608
+
amdgpu_reg_get_smn_base64(adev, MP0_HWIP, instance);
5610
5609
5611
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for (retry_loop = 0; retry_loop < AMDGPU_RAS_BOOT_STATUS_POLLING_LIMIT; retry_loop++) {
5612
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reg_data = amdgpu_device_indirect_rreg_ext(adev, reg_addr);
+55
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c
+55
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c
···
283
283
adev->reg.pcie.port_wreg(adev, reg, v);
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}
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+
static int amdgpu_reg_get_smn_base_version(struct amdgpu_device *adev)
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+
{
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struct pci_dev *pdev = adev->pdev;
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int id;
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+
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if (amdgpu_sriov_vf(adev))
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+
return -EOPNOTSUPP;
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+
294
+
id = (pdev->device >> 4) & 0xFFFF;
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+
if (id == 0x74A || id == 0x74B || id == 0x75A || id == 0x75B)
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+
return 1;
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+
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+
return -EOPNOTSUPP;
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+
}
300
+
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uint64_t amdgpu_reg_get_smn_base64(struct amdgpu_device *adev,
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enum amd_hw_ip_block_type block,
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int die_inst)
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{
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if (!adev->reg.smn.get_smn_base) {
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-
dev_err_once(adev->dev, "SMN base address callback not set\n");
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+
int version = amdgpu_reg_get_smn_base_version(adev);
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+
switch (version) {
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case 1:
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return amdgpu_reg_smn_v1_0_get_base(adev, block,
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+
die_inst);
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+
default:
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dev_err_once(
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adev->dev,
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"SMN base address query not supported for this device\n");
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return 0;
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+
}
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return 0;
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}
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return adev->reg.smn.get_smn_base(adev, block, die_inst);
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+
}
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+
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uint64_t amdgpu_reg_smn_v1_0_get_base(struct amdgpu_device *adev,
323
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enum amd_hw_ip_block_type block,
324
+
int die_inst)
325
+
{
326
+
uint64_t smn_base;
327
+
328
+
if (die_inst == 0)
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+
return 0;
330
+
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+
switch (block) {
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+
case XGMI_HWIP:
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+
case NBIO_HWIP:
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+
case MP0_HWIP:
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+
case UMC_HWIP:
336
+
case DF_HWIP:
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+
smn_base = ((uint64_t)(die_inst & 0x3) << 32) | (1ULL << 34);
338
+
break;
339
+
default:
340
+
dev_warn_once(
341
+
adev->dev,
342
+
"SMN base address query not supported for this block %d\n",
343
+
block);
344
+
smn_base = 0;
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+
break;
346
+
}
347
+
348
+
return smn_base;
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}
296
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/*
+3
drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h
+3
drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h
···
122
122
uint64_t amdgpu_reg_get_smn_base64(struct amdgpu_device *adev,
123
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enum amd_hw_ip_block_type block,
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int die_inst);
125
+
uint64_t amdgpu_reg_smn_v1_0_get_base(struct amdgpu_device *adev,
126
+
enum amd_hw_ip_block_type block,
127
+
int die_inst);
125
128
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uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, uint32_t reg,
127
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uint32_t acc_flags);
+8
-4
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
+8
-4
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
···
338
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if (!(adev->aid_mask & BIT(i)))
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return U32_MAX;
340
340
341
-
addr += adev->asic_funcs->encode_ext_smn_addressing(i);
341
+
addr += amdgpu_reg_get_smn_base64(adev, XGMI_HWIP, i);
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return RREG32_PCIE_EXT(addr);
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}
···
1293
1293
1294
1294
static void __xgmi_v6_4_0_reset_error_count(struct amdgpu_device *adev, int xgmi_inst, u64 mca_base)
1295
1295
{
1296
-
WREG64_MCA(xgmi_inst, mca_base, ACA_REG_IDX_STATUS, 0ULL);
1296
+
uint64_t smn_base =
1297
+
amdgpu_reg_get_smn_base64(adev, XGMI_HWIP, xgmi_inst);
1298
+
1299
+
WREG64_MCA(smn_base, mca_base, ACA_REG_IDX_STATUS, 0ULL);
1297
1300
}
1298
1301
1299
1302
static void xgmi_v6_4_0_reset_error_count(struct amdgpu_device *adev, int xgmi_inst)
···
1506
1503
u64 mca_base, struct ras_err_data *err_data)
1507
1504
{
1508
1505
int xgmi_inst = mcm_info->die_id;
1506
+
uint64_t smn_base;
1509
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u64 status = 0;
1510
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1511
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status = RREG64_MCA(xgmi_inst, mca_base, ACA_REG_IDX_STATUS);
···
1523
1519
default:
1524
1520
break;
1525
1521
}
1526
-
1527
-
WREG64_MCA(xgmi_inst, mca_base, ACA_REG_IDX_STATUS, 0ULL);
1522
+
smn_base = amdgpu_reg_get_smn_base64(adev, XGMI_HWIP, xgmi_inst);
1523
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WREG64_MCA(smn_base, mca_base, ACA_REG_IDX_STATUS, 0ULL);
1528
1524
}
1529
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static void xgmi_v6_4_0_query_error_count(struct amdgpu_device *adev, int xgmi_inst, struct ras_err_data *err_data)
+1
-20
drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c
+1
-20
drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c
···
58
58
adev->doorbell_index.max_assignment = AMDGPU_DOORBELL_LAYOUT1_MAX_ASSIGNMENT << 1;
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}
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-
/* Fixed pattern for smn addressing on different AIDs:
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-
* bit[34]: indicate cross AID access
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-
* bit[33:32]: indicate target AID id
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* AID id range is 0 ~ 3 as maximum AID number is 4.
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*/
66
-
u64 aqua_vanjaram_encode_ext_smn_addressing(int ext_id)
67
-
{
68
-
u64 ext_offset;
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-
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-
/* local routing and bit[34:32] will be zeros */
71
-
if (ext_id == 0)
72
-
return 0;
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-
74
-
/* Initiated from host, accessing to all non-zero aids are cross traffic */
75
-
ext_offset = ((u64)(ext_id & 0x3) << 32) | (1ULL << 34);
76
-
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-
return ext_offset;
78
-
}
79
-
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static enum amdgpu_gfx_partition
81
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__aqua_vanjaram_calc_xcp_mode(struct amdgpu_xcp_mgr *xcp_mgr)
82
63
{
···
571
590
uint64_t smn_addr, int i)
572
591
{
573
592
regdata->addr =
574
-
smn_addr + adev->asic_funcs->encode_ext_smn_addressing(i);
593
+
smn_addr + amdgpu_reg_get_smn_base64(adev, XGMI_HWIP, i);
575
594
regdata->value = RREG32_PCIE_EXT(regdata->addr);
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}
577
596
+1
-1
drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
+1
-1
drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
···
166
166
bl_status_reg =
167
167
(SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_92)
168
168
<< 2) +
169
-
adev->asic_funcs->encode_ext_smn_addressing(i);
169
+
amdgpu_reg_get_smn_base64(adev, MP0_HWIP, i);
170
170
at += snprintf(bl_status_msg + at,
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PSP13_BL_STATUS_SIZE - at,
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" status(%02i): 0x%08x", i,
+1
-1
drivers/gpu/drm/amd/amdgpu/soc15.c
+1
-1
drivers/gpu/drm/amd/amdgpu/soc15.c
···
952
952
.get_pcie_replay_count = &amdgpu_nbio_get_pcie_replay_count,
953
953
.supports_baco = &soc15_supports_baco,
954
954
.query_video_codecs = &soc15_query_video_codecs,
955
-
.encode_ext_smn_addressing = &aqua_vanjaram_encode_ext_smn_addressing,
956
955
.get_reg_state = &aqua_vanjaram_get_reg_state,
957
956
};
958
957
···
1197
1198
case IP_VERSION(9, 4, 4):
1198
1199
case IP_VERSION(9, 5, 0):
1199
1200
adev->asic_funcs = &aqua_vanjaram_asic_funcs;
1201
+
adev->reg.smn.get_smn_base = &amdgpu_reg_smn_v1_0_get_base;
1200
1202
adev->cg_flags =
1201
1203
AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_CGCG |
1202
1204
AMD_CG_SUPPORT_GFX_CGLS | AMD_CG_SUPPORT_SDMA_MGCG |
-1
drivers/gpu/drm/amd/amdgpu/soc15.h
-1
drivers/gpu/drm/amd/amdgpu/soc15.h
···
118
118
int vega20_reg_base_init(struct amdgpu_device *adev);
119
119
int arct_reg_base_init(struct amdgpu_device *adev);
120
120
int aldebaran_reg_base_init(struct amdgpu_device *adev);
121
-
u64 aqua_vanjaram_encode_ext_smn_addressing(int ext_id);
122
121
int aqua_vanjaram_init_soc_config(struct amdgpu_device *adev);
123
122
ssize_t aqua_vanjaram_get_reg_state(struct amdgpu_device *adev,
124
123
enum amdgpu_reg_state reg_state, void *buf,
+14
-11
drivers/gpu/drm/amd/amdgpu/soc15_common.h
+14
-11
drivers/gpu/drm/amd/amdgpu/soc15_common.h
···
195
195
__RREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, AMDGPU_REGS_RLC, ip##_HWIP, inst)
196
196
197
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/* inst equals to ext for some IPs */
198
-
#define RREG32_SOC15_EXT(ip, inst, reg, ext) \
199
-
RREG32_PCIE_EXT((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) * 4 \
200
-
+ adev->asic_funcs->encode_ext_smn_addressing(ext)) \
198
+
#define RREG32_SOC15_EXT(ip, inst, reg, ext) \
199
+
RREG32_PCIE_EXT((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + \
200
+
reg) * 4 + \
201
+
amdgpu_reg_get_smn_base64(adev, ip##_HWIP, inst))
201
202
202
-
#define WREG32_SOC15_EXT(ip, inst, reg, ext, value) \
203
-
WREG32_PCIE_EXT((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) * 4 \
204
-
+ adev->asic_funcs->encode_ext_smn_addressing(ext), \
205
-
value) \
203
+
#define WREG32_SOC15_EXT(ip, inst, reg, ext, value) \
204
+
WREG32_PCIE_EXT( \
205
+
(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) * \
206
+
4 + \
207
+
amdgpu_reg_get_smn_base64(adev, ip##_HWIP, inst), \
208
+
value)
206
209
207
-
#define RREG64_MCA(ext, mca_base, idx) \
208
-
RREG64_PCIE_EXT(adev->asic_funcs->encode_ext_smn_addressing(ext) + mca_base + (idx * 8))
210
+
#define RREG64_MCA(smn_base, mca_base, idx) \
211
+
RREG64_PCIE_EXT(smn_base + mca_base + (idx * 8))
209
212
210
-
#define WREG64_MCA(ext, mca_base, idx, val) \
211
-
WREG64_PCIE_EXT(adev->asic_funcs->encode_ext_smn_addressing(ext) + mca_base + (idx * 8), val)
213
+
#define WREG64_MCA(smn_base, mca_base, idx, val) \
214
+
WREG64_PCIE_EXT(smn_base + mca_base + (idx * 8), val)
212
215
213
216
#endif