tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux

Pull drm fixes from Dave Airlie:
"Fixes for big 3 drivers:

nouveau: revert earlier MBP fix, put a dmi based MBP fix in its place
(fixes a regression we found on some Dell eDP panels doing some
internal testing)

radeon: revert pll fixes, real fix is too invasive, fix scratch leak

intel: 3 minor fixes, one for HDMI audio."

* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
drm/nouveau: add dmi quirk for gpio reset
drm/radeon: Prevent leak of scratch register on resume from suspend
Revert "drm/nv50-/gpio: initialise to vbios defaults during init"
Revert "drm/radeon: rework pll selection (v3)"
drm/i915: HDMI - Clear Audio Enable bit for Hot Plug
drm/i915: Reduce a pin-leak BUG into a WARN
drm/i915: enable lvds pin pairs before dpll on gen2

Linus Torvalds 36a21fe6 6551d6fe

+59 -139
+2 -1
drivers/gpu/drm/i915/i915_gem.c
··· 3242 3242 { 3243 3243 int ret; 3244 3244 3245 - BUG_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT); 3245 + if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) 3246 + return -EBUSY; 3246 3247 3247 3248 if (obj->gtt_space != NULL) { 3248 3249 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
+6 -6
drivers/gpu/drm/i915/intel_display.c
··· 4191 4191 POSTING_READ(DPLL(pipe)); 4192 4192 udelay(150); 4193 4193 4194 - I915_WRITE(DPLL(pipe), dpll); 4195 - 4196 - /* Wait for the clocks to stabilize. */ 4197 - POSTING_READ(DPLL(pipe)); 4198 - udelay(150); 4199 - 4200 4194 /* The LVDS pin pair needs to be on before the DPLLs are enabled. 4201 4195 * This is an exception to the general rule that mode_set doesn't turn 4202 4196 * things on. 4203 4197 */ 4204 4198 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) 4205 4199 intel_update_lvds(crtc, clock, adjusted_mode); 4200 + 4201 + I915_WRITE(DPLL(pipe), dpll); 4202 + 4203 + /* Wait for the clocks to stabilize. */ 4204 + POSTING_READ(DPLL(pipe)); 4205 + udelay(150); 4206 4206 4207 4207 /* The pixel multiplier can only be updated once the 4208 4208 * DPLL is enabled and the clocks are stable.
+1 -1
drivers/gpu/drm/i915/intel_hdmi.c
··· 609 609 u32 temp; 610 610 u32 enable_bits = SDVO_ENABLE; 611 611 612 - if (intel_hdmi->has_audio) 612 + if (intel_hdmi->has_audio || mode != DRM_MODE_DPMS_ON) 613 613 enable_bits |= SDVO_AUDIO_ENABLE; 614 614 615 615 temp = I915_READ(intel_hdmi->sdvox_reg);
+14 -1
drivers/gpu/drm/nouveau/nv50_gpio.c
··· 22 22 * Authors: Ben Skeggs 23 23 */ 24 24 25 + #include <linux/dmi.h> 25 26 #include "drmP.h" 26 27 #include "nouveau_drv.h" 27 28 #include "nouveau_hw.h" ··· 111 110 nv_wr32(dev, 0xe074, intr1); 112 111 } 113 112 113 + static struct dmi_system_id gpio_reset_ids[] = { 114 + { 115 + .ident = "Apple Macbook 10,1", 116 + .matches = { 117 + DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), 118 + DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro10,1"), 119 + } 120 + }, 121 + { } 122 + }; 123 + 114 124 int 115 125 nv50_gpio_init(struct drm_device *dev) 116 126 { 117 127 struct drm_nouveau_private *dev_priv = dev->dev_private; 118 128 119 129 /* initialise gpios and routing to vbios defaults */ 120 - nouveau_gpio_reset(dev); 130 + if (dmi_check_system(gpio_reset_ids)) 131 + nouveau_gpio_reset(dev); 121 132 122 133 /* disable, and ack any pending gpio interrupts */ 123 134 nv_wr32(dev, 0xe050, 0x00000000);
+34 -129
drivers/gpu/drm/radeon/atombios_crtc.c
··· 1479 1479 } 1480 1480 } 1481 1481 1482 - /** 1483 - * radeon_get_pll_use_mask - look up a mask of which pplls are in use 1484 - * 1485 - * @crtc: drm crtc 1486 - * 1487 - * Returns the mask of which PPLLs (Pixel PLLs) are in use. 1488 - */ 1489 - static u32 radeon_get_pll_use_mask(struct drm_crtc *crtc) 1490 - { 1491 - struct drm_device *dev = crtc->dev; 1492 - struct drm_crtc *test_crtc; 1493 - struct radeon_crtc *radeon_test_crtc; 1494 - u32 pll_in_use = 0; 1495 - 1496 - list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { 1497 - if (crtc == test_crtc) 1498 - continue; 1499 - 1500 - radeon_test_crtc = to_radeon_crtc(test_crtc); 1501 - if (radeon_test_crtc->pll_id != ATOM_PPLL_INVALID) 1502 - pll_in_use |= (1 << radeon_test_crtc->pll_id); 1503 - } 1504 - return pll_in_use; 1505 - } 1506 - 1507 - /** 1508 - * radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP 1509 - * 1510 - * @crtc: drm crtc 1511 - * 1512 - * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is 1513 - * also in DP mode. For DP, a single PPLL can be used for all DP 1514 - * crtcs/encoders. 1515 - */ 1516 - static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc) 1517 - { 1518 - struct drm_device *dev = crtc->dev; 1519 - struct drm_encoder *test_encoder; 1520 - struct radeon_crtc *radeon_test_crtc; 1521 - 1522 - list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { 1523 - if (test_encoder->crtc && (test_encoder->crtc != crtc)) { 1524 - if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) { 1525 - /* for DP use the same PLL for all */ 1526 - radeon_test_crtc = to_radeon_crtc(test_encoder->crtc); 1527 - if (radeon_test_crtc->pll_id != ATOM_PPLL_INVALID) 1528 - return radeon_test_crtc->pll_id; 1529 - } 1530 - } 1531 - } 1532 - return ATOM_PPLL_INVALID; 1533 - } 1534 - 1535 - /** 1536 - * radeon_atom_pick_pll - Allocate a PPLL for use by the crtc. 1537 - * 1538 - * @crtc: drm crtc 1539 - * 1540 - * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors 1541 - * a single PPLL can be used for all DP crtcs/encoders. For non-DP 1542 - * monitors a dedicated PPLL must be used. If a particular board has 1543 - * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming 1544 - * as there is no need to program the PLL itself. If we are not able to 1545 - * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to 1546 - * avoid messing up an existing monitor. 1547 - * 1548 - * Asic specific PLL information 1549 - * 1550 - * DCE 6.1 1551 - * - PPLL2 is only available to UNIPHYA (both DP and non-DP) 1552 - * - PPLL0, PPLL1 are available for UNIPHYB/C/D/E/F (both DP and non-DP) 1553 - * 1554 - * DCE 6.0 1555 - * - PPLL0 is available to all UNIPHY (DP only) 1556 - * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 1557 - * 1558 - * DCE 5.0 1559 - * - DCPLL is available to all UNIPHY (DP only) 1560 - * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 1561 - * 1562 - * DCE 3.0/4.0/4.1 1563 - * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 1564 - * 1565 - */ 1566 1482 static int radeon_atom_pick_pll(struct drm_crtc *crtc) 1567 1483 { 1568 1484 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1569 1485 struct drm_device *dev = crtc->dev; 1570 1486 struct radeon_device *rdev = dev->dev_private; 1571 1487 struct drm_encoder *test_encoder; 1572 - u32 pll_in_use; 1573 - int pll; 1488 + struct drm_crtc *test_crtc; 1489 + uint32_t pll_in_use = 0; 1574 1490 1575 1491 if (ASIC_IS_DCE61(rdev)) { 1576 1492 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { ··· 1498 1582 1499 1583 if ((test_radeon_encoder->encoder_id == 1500 1584 ENCODER_OBJECT_ID_INTERNAL_UNIPHY) && 1501 - (dig->linkb == false)) 1502 - /* UNIPHY A uses PPLL2 */ 1585 + (dig->linkb == false)) /* UNIPHY A uses PPLL2 */ 1503 1586 return ATOM_PPLL2; 1504 - else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) { 1505 - /* UNIPHY B/C/D/E/F */ 1506 - if (rdev->clock.dp_extclk) 1507 - /* skip PPLL programming if using ext clock */ 1508 - return ATOM_PPLL_INVALID; 1509 - else { 1510 - /* use the same PPLL for all DP monitors */ 1511 - pll = radeon_get_shared_dp_ppll(crtc); 1512 - if (pll != ATOM_PPLL_INVALID) 1513 - return pll; 1514 - } 1515 - } 1516 - break; 1517 1587 } 1518 1588 } 1519 1589 /* UNIPHY B/C/D/E/F */ 1520 - pll_in_use = radeon_get_pll_use_mask(crtc); 1521 - if (!(pll_in_use & (1 << ATOM_PPLL0))) 1590 + list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { 1591 + struct radeon_crtc *radeon_test_crtc; 1592 + 1593 + if (crtc == test_crtc) 1594 + continue; 1595 + 1596 + radeon_test_crtc = to_radeon_crtc(test_crtc); 1597 + if ((radeon_test_crtc->pll_id == ATOM_PPLL0) || 1598 + (radeon_test_crtc->pll_id == ATOM_PPLL1)) 1599 + pll_in_use |= (1 << radeon_test_crtc->pll_id); 1600 + } 1601 + if (!(pll_in_use & 4)) 1522 1602 return ATOM_PPLL0; 1523 - if (!(pll_in_use & (1 << ATOM_PPLL1))) 1524 - return ATOM_PPLL1; 1525 - DRM_ERROR("unable to allocate a PPLL\n"); 1526 - return ATOM_PPLL_INVALID; 1603 + return ATOM_PPLL1; 1527 1604 } else if (ASIC_IS_DCE4(rdev)) { 1528 1605 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { 1529 1606 if (test_encoder->crtc && (test_encoder->crtc == crtc)) { 1530 1607 /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock, 1531 1608 * depending on the asic: 1532 1609 * DCE4: PPLL or ext clock 1533 - * DCE5: PPLL, DCPLL, or ext clock 1534 - * DCE6: PPLL, PPLL0, or ext clock 1610 + * DCE5: DCPLL or ext clock 1535 1611 * 1536 1612 * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip 1537 1613 * PPLL/DCPLL programming and only program the DP DTO for the ··· 1531 1623 */ 1532 1624 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) { 1533 1625 if (rdev->clock.dp_extclk) 1534 - /* skip PPLL programming if using ext clock */ 1535 1626 return ATOM_PPLL_INVALID; 1536 1627 else if (ASIC_IS_DCE6(rdev)) 1537 - /* use PPLL0 for all DP */ 1538 1628 return ATOM_PPLL0; 1539 1629 else if (ASIC_IS_DCE5(rdev)) 1540 - /* use DCPLL for all DP */ 1541 1630 return ATOM_DCPLL; 1542 - else { 1543 - /* use the same PPLL for all DP monitors */ 1544 - pll = radeon_get_shared_dp_ppll(crtc); 1545 - if (pll != ATOM_PPLL_INVALID) 1546 - return pll; 1547 - } 1548 1631 } 1549 - break; 1550 1632 } 1551 1633 } 1552 - /* all other cases */ 1553 - pll_in_use = radeon_get_pll_use_mask(crtc); 1554 - if (!(pll_in_use & (1 << ATOM_PPLL2))) 1555 - return ATOM_PPLL2; 1556 - if (!(pll_in_use & (1 << ATOM_PPLL1))) 1634 + 1635 + /* otherwise, pick one of the plls */ 1636 + list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { 1637 + struct radeon_crtc *radeon_test_crtc; 1638 + 1639 + if (crtc == test_crtc) 1640 + continue; 1641 + 1642 + radeon_test_crtc = to_radeon_crtc(test_crtc); 1643 + if ((radeon_test_crtc->pll_id >= ATOM_PPLL1) && 1644 + (radeon_test_crtc->pll_id <= ATOM_PPLL2)) 1645 + pll_in_use |= (1 << radeon_test_crtc->pll_id); 1646 + } 1647 + if (!(pll_in_use & 1)) 1557 1648 return ATOM_PPLL1; 1558 - DRM_ERROR("unable to allocate a PPLL\n"); 1559 - return ATOM_PPLL_INVALID; 1649 + return ATOM_PPLL2; 1560 1650 } else 1561 - /* use PPLL1 or PPLL2 */ 1562 1651 return radeon_crtc->crtc_id; 1563 1652 1564 1653 } ··· 1697 1792 break; 1698 1793 } 1699 1794 done: 1700 - radeon_crtc->pll_id = ATOM_PPLL_INVALID; 1795 + radeon_crtc->pll_id = -1; 1701 1796 } 1702 1797 1703 1798 static const struct drm_crtc_helper_funcs atombios_helper_funcs = { ··· 1746 1841 else 1747 1842 radeon_crtc->crtc_offset = 0; 1748 1843 } 1749 - radeon_crtc->pll_id = ATOM_PPLL_INVALID; 1844 + radeon_crtc->pll_id = -1; 1750 1845 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs); 1751 1846 }
+2 -1
drivers/gpu/drm/radeon/r100.c
··· 1182 1182 ring->ready = true; 1183 1183 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); 1184 1184 1185 - if (radeon_ring_supports_scratch_reg(rdev, ring)) { 1185 + if (!ring->rptr_save_reg /* not resuming from suspend */ 1186 + && radeon_ring_supports_scratch_reg(rdev, ring)) { 1186 1187 r = radeon_scratch_get(rdev, &ring->rptr_save_reg); 1187 1188 if (r) { 1188 1189 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);