tjh.dev / kernel
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iio: accel: bma400: Reorganize and rename register and field macros

Reorganize register and field macros to improve consistency with the
datasheet and naming style:

- Move field macros next to their corresponding register macros
- Reorder register macros to follow address order from the datasheet
- Rename field macros to include the register name in the macro name
- Add a _REG suffix to register macros where missing
- Add INT_STAT register fields corresponding to used INT_CONFIG fields

No functional changes are intended.

Signed-off-by: Akshay Jindal <akshayaj.lkd@gmail.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

authored by

Akshay Jindal and committed by
Jonathan Cameron 36bf0de9 6365d2b9

+170 -159
+64 -53
drivers/iio/accel/bma400.h
··· 16 16 * Read-Only Registers 17 17 */ 18 18 19 + /* Chip ID of BMA 400 devices found in the chip ID register. */ 20 + #define BMA400_ID_REG_VAL 0x90 21 + 19 22 /* Status and ID registers */ 20 23 #define BMA400_CHIP_ID_REG 0x00 21 24 #define BMA400_ERR_REG 0x02 22 25 #define BMA400_STATUS_REG 0x03 23 26 24 27 /* Acceleration registers */ 25 - #define BMA400_X_AXIS_LSB_REG 0x04 26 - #define BMA400_X_AXIS_MSB_REG 0x05 27 - #define BMA400_Y_AXIS_LSB_REG 0x06 28 - #define BMA400_Y_AXIS_MSB_REG 0x07 29 - #define BMA400_Z_AXIS_LSB_REG 0x08 30 - #define BMA400_Z_AXIS_MSB_REG 0x09 28 + #define BMA400_ACC_X_LSB_REG 0x04 29 + #define BMA400_ACC_X_MSB_REG 0x05 30 + #define BMA400_ACC_Y_LSB_REG 0x06 31 + #define BMA400_ACC_Y_MSB_REG 0x07 32 + #define BMA400_ACC_Z_LSB_REG 0x08 33 + #define BMA400_ACC_Z_MSB_REG 0x09 31 34 32 35 /* Sensor time registers */ 33 - #define BMA400_SENSOR_TIME0 0x0a 34 - #define BMA400_SENSOR_TIME1 0x0b 35 - #define BMA400_SENSOR_TIME2 0x0c 36 + #define BMA400_SENSOR_TIME0_REG 0x0a 37 + #define BMA400_SENSOR_TIME1_REG 0x0b 38 + #define BMA400_SENSOR_TIME2_REG 0x0c 36 39 37 40 /* Event and interrupt registers */ 38 41 #define BMA400_EVENT_REG 0x0d 42 + 39 43 #define BMA400_INT_STAT0_REG 0x0e 44 + #define BMA400_INT_STAT0_GEN1_MASK BIT(2) 45 + #define BMA400_INT_STAT0_GEN2_MASK BIT(3) 46 + #define BMA400_INT_STAT0_DRDY_MASK BIT(7) 47 + 40 48 #define BMA400_INT_STAT1_REG 0x0f 49 + #define BMA400_INT_STAT1_STEP_INT_MASK GENMASK(9, 8) 50 + #define BMA400_INT_STAT1_S_TAP_MASK BIT(10) 51 + #define BMA400_INT_STAT1_D_TAP_MASK BIT(11) 52 + 41 53 #define BMA400_INT_STAT2_REG 0x10 42 - #define BMA400_INT12_MAP_REG 0x23 43 - #define BMA400_INT_ENG_OVRUN_MSK BIT(4) 54 + 55 + /* Bit present in all INT_STAT registers */ 56 + #define BMA400_INT_STAT_ENG_OVRRUN_MASK BIT(4) 44 57 45 58 /* Temperature register */ 46 59 #define BMA400_TEMP_DATA_REG 0x11 ··· 68 55 #define BMA400_STEP_CNT1_REG 0x16 69 56 #define BMA400_STEP_CNT3_REG 0x17 70 57 #define BMA400_STEP_STAT_REG 0x18 71 - #define BMA400_STEP_INT_MSK BIT(0) 72 58 #define BMA400_STEP_RAW_LEN 0x03 73 - #define BMA400_STEP_STAT_MASK GENMASK(9, 8) 74 59 75 60 /* 76 61 * Read-write configuration registers 77 62 */ 78 - #define BMA400_ACC_CONFIG0_REG 0x19 79 - #define BMA400_ACC_CONFIG1_REG 0x1a 63 + #define BMA400_ACC_CONFIG0_REG 0x19 64 + #define BMA400_ACC_CONFIG0_LP_OSR_MASK GENMASK(6, 5) 65 + #define BMA400_LP_OSR_SHIFT 5 66 + 67 + #define BMA400_ACC_CONFIG1_REG 0x1a 68 + #define BMA400_ACC_CONFIG1_ODR_MASK GENMASK(3, 0) 69 + #define BMA400_ACC_CONFIG1_ODR_MIN_RAW 0x05 70 + #define BMA400_ACC_CONFIG1_ODR_LP_RAW 0x06 71 + #define BMA400_ACC_CONFIG1_ODR_MAX_RAW 0x0b 72 + #define BMA400_ACC_CONFIG1_ODR_MAX_HZ 800 73 + #define BMA400_ACC_CONFIG1_ODR_MIN_WHOLE_HZ 25 74 + #define BMA400_ACC_CONFIG1_ODR_MIN_HZ 12 75 + #define BMA400_ACC_CONFIG1_NP_OSR_MASK GENMASK(5, 4) 76 + #define BMA400_NP_OSR_SHIFT 4 77 + #define BMA400_ACC_CONFIG1_ACC_RANGE_MASK GENMASK(7, 6) 78 + #define BMA400_ACC_RANGE_SHIFT 6 79 + 80 80 #define BMA400_ACC_CONFIG2_REG 0x1b 81 - #define BMA400_CMD_REG 0x7e 82 81 83 82 /* Interrupt registers */ 84 83 #define BMA400_INT_CONFIG0_REG 0x1f 84 + #define BMA400_INT_CONFIG0_GEN1_MASK BIT(2) 85 + #define BMA400_INT_CONFIG0_GEN2_MASK BIT(3) 86 + #define BMA400_INT_CONFIG0_DRDY_MASK BIT(7) 87 + 85 88 #define BMA400_INT_CONFIG1_REG 0x20 89 + #define BMA400_INT_CONFIG1_STEP_INT_MASK BIT(0) 90 + #define BMA400_INT_CONFIG1_S_TAP_MASK BIT(2) 91 + #define BMA400_INT_CONFIG1_D_TAP_MASK BIT(3) 92 + 86 93 #define BMA400_INT1_MAP_REG 0x21 94 + #define BMA400_INT12_MAP_REG 0x23 87 95 #define BMA400_INT_IO_CTRL_REG 0x24 88 - #define BMA400_INT_DRDY_MSK BIT(7) 89 - 90 - /* Chip ID of BMA 400 devices found in the chip ID register. */ 91 - #define BMA400_ID_REG_VAL 0x90 92 - 93 - #define BMA400_LP_OSR_SHIFT 5 94 - #define BMA400_NP_OSR_SHIFT 4 95 - #define BMA400_SCALE_SHIFT 6 96 96 97 97 #define BMA400_TWO_BITS_MASK GENMASK(1, 0) 98 - #define BMA400_LP_OSR_MASK GENMASK(6, 5) 99 - #define BMA400_NP_OSR_MASK GENMASK(5, 4) 100 - #define BMA400_ACC_ODR_MASK GENMASK(3, 0) 101 - #define BMA400_ACC_SCALE_MASK GENMASK(7, 6) 102 - 103 - #define BMA400_ACC_ODR_MIN_RAW 0x05 104 - #define BMA400_ACC_ODR_LP_RAW 0x06 105 - #define BMA400_ACC_ODR_MAX_RAW 0x0b 106 - 107 - #define BMA400_ACC_ODR_MAX_HZ 800 108 - #define BMA400_ACC_ODR_MIN_WHOLE_HZ 25 109 - #define BMA400_ACC_ODR_MIN_HZ 12 110 98 111 99 /* Generic interrupts register */ 112 - #define BMA400_GEN1INT_CONFIG0 0x3f 113 - #define BMA400_GEN2INT_CONFIG0 0x4A 100 + #define BMA400_GEN1INT_CONFIG0_REG 0x3f 101 + #define BMA400_GEN2INT_CONFIG0_REG 0x4A 102 + #define BMA400_GENINT_CONFIG0_HYST_MASK GENMASK(1, 0) 103 + 114 104 #define BMA400_GEN_CONFIG1_OFF 0x01 115 105 #define BMA400_GEN_CONFIG2_OFF 0x02 116 106 #define BMA400_GEN_CONFIG3_OFF 0x03 117 107 #define BMA400_GEN_CONFIG31_OFF 0x04 118 - #define BMA400_INT_GEN1_MSK BIT(2) 119 - #define BMA400_INT_GEN2_MSK BIT(3) 120 - #define BMA400_GEN_HYST_MSK GENMASK(1, 0) 121 108 122 109 /* TAP config registers */ 123 - #define BMA400_TAP_CONFIG 0x57 124 - #define BMA400_TAP_CONFIG1 0x58 125 - #define BMA400_S_TAP_MSK BIT(2) 126 - #define BMA400_D_TAP_MSK BIT(3) 127 - #define BMA400_INT_S_TAP_MSK BIT(10) 128 - #define BMA400_INT_D_TAP_MSK BIT(11) 129 - #define BMA400_TAP_SEN_MSK GENMASK(2, 0) 130 - #define BMA400_TAP_TICSTH_MSK GENMASK(1, 0) 131 - #define BMA400_TAP_QUIET_MSK GENMASK(3, 2) 132 - #define BMA400_TAP_QUIETDT_MSK GENMASK(5, 4) 110 + #define BMA400_TAP_CONFIG_REG 0x57 111 + #define BMA400_TAP_CONFIG_SEN_MASK GENMASK(2, 0) 112 + 113 + #define BMA400_TAP_CONFIG1_REG 0x58 114 + #define BMA400_TAP_CONFIG1_TICSTH_MASK GENMASK(1, 0) 115 + #define BMA400_TAP_CONFIG1_QUIET_MASK GENMASK(3, 2) 116 + #define BMA400_TAP_CONFIG1_QUIETDT_MASK GENMASK(5, 4) 133 117 #define BMA400_TAP_TIM_LIST_LEN 4 134 118 119 + #define BMA400_CMD_REG 0x7e 135 120 /* 136 121 * BMA400_SCALE_MIN macro value represents m/s^2 for 1 LSB before 137 122 * converting to micro values for +-2g range. ··· 149 138 * To select +-8g = 9577 << 2 = raw value to write is 2. 150 139 * To select +-16g = 9577 << 3 = raw value to write is 3. 151 140 */ 152 - #define BMA400_SCALE_MIN 9577 153 - #define BMA400_SCALE_MAX 76617 141 + #define BMA400_ACC_SCALE_MIN 9577 142 + #define BMA400_ACC_SCALE_MAX 76617 154 143 155 144 extern const struct regmap_config bma400_regmap_config; 156 145
+106 -106
drivers/iio/accel/bma400_core.c
··· 127 127 case BMA400_CHIP_ID_REG: 128 128 case BMA400_ERR_REG: 129 129 case BMA400_STATUS_REG: 130 - case BMA400_X_AXIS_LSB_REG: 131 - case BMA400_X_AXIS_MSB_REG: 132 - case BMA400_Y_AXIS_LSB_REG: 133 - case BMA400_Y_AXIS_MSB_REG: 134 - case BMA400_Z_AXIS_LSB_REG: 135 - case BMA400_Z_AXIS_MSB_REG: 136 - case BMA400_SENSOR_TIME0: 137 - case BMA400_SENSOR_TIME1: 138 - case BMA400_SENSOR_TIME2: 130 + case BMA400_ACC_X_LSB_REG: 131 + case BMA400_ACC_X_MSB_REG: 132 + case BMA400_ACC_Y_LSB_REG: 133 + case BMA400_ACC_Y_MSB_REG: 134 + case BMA400_ACC_Z_LSB_REG: 135 + case BMA400_ACC_Z_MSB_REG: 136 + case BMA400_SENSOR_TIME0_REG: 137 + case BMA400_SENSOR_TIME1_REG: 138 + case BMA400_SENSOR_TIME2_REG: 139 139 case BMA400_EVENT_REG: 140 140 case BMA400_INT_STAT0_REG: 141 141 case BMA400_INT_STAT1_REG: ··· 159 159 switch (reg) { 160 160 case BMA400_ERR_REG: 161 161 case BMA400_STATUS_REG: 162 - case BMA400_X_AXIS_LSB_REG: 163 - case BMA400_X_AXIS_MSB_REG: 164 - case BMA400_Y_AXIS_LSB_REG: 165 - case BMA400_Y_AXIS_MSB_REG: 166 - case BMA400_Z_AXIS_LSB_REG: 167 - case BMA400_Z_AXIS_MSB_REG: 168 - case BMA400_SENSOR_TIME0: 169 - case BMA400_SENSOR_TIME1: 170 - case BMA400_SENSOR_TIME2: 162 + case BMA400_ACC_X_LSB_REG: 163 + case BMA400_ACC_X_MSB_REG: 164 + case BMA400_ACC_Y_LSB_REG: 165 + case BMA400_ACC_Y_MSB_REG: 166 + case BMA400_ACC_Z_LSB_REG: 167 + case BMA400_ACC_Z_MSB_REG: 168 + case BMA400_SENSOR_TIME0_REG: 169 + case BMA400_SENSOR_TIME1_REG: 170 + case BMA400_SENSOR_TIME2_REG: 171 171 case BMA400_EVENT_REG: 172 172 case BMA400_INT_STAT0_REG: 173 173 case BMA400_INT_STAT1_REG: ··· 275 275 struct bma400_data *data = iio_priv(indio_dev); 276 276 int ret, reg_val, raw, vals[2]; 277 277 278 - ret = regmap_read(data->regmap, BMA400_TAP_CONFIG1, &reg_val); 278 + ret = regmap_read(data->regmap, BMA400_TAP_CONFIG1_REG, &reg_val); 279 279 if (ret) 280 280 return ret; 281 281 282 - raw = FIELD_GET(BMA400_TAP_TICSTH_MSK, reg_val); 282 + raw = FIELD_GET(BMA400_TAP_CONFIG1_TICSTH_MASK, reg_val); 283 283 vals[0] = 0; 284 284 vals[1] = tap_max2min_time[raw]; 285 285 ··· 302 302 if (raw < 0) 303 303 return -EINVAL; 304 304 305 - ret = regmap_update_bits(data->regmap, BMA400_TAP_CONFIG1, 306 - BMA400_TAP_TICSTH_MSK, 307 - FIELD_PREP(BMA400_TAP_TICSTH_MSK, raw)); 305 + ret = regmap_update_bits(data->regmap, BMA400_TAP_CONFIG1_REG, 306 + BMA400_TAP_CONFIG1_TICSTH_MASK, 307 + FIELD_PREP(BMA400_TAP_CONFIG1_TICSTH_MASK, raw)); 308 308 if (ret) 309 309 return ret; 310 310 ··· 449 449 450 450 switch (chan->channel2) { 451 451 case IIO_MOD_X: 452 - lsb_reg = BMA400_X_AXIS_LSB_REG; 452 + lsb_reg = BMA400_ACC_X_LSB_REG; 453 453 break; 454 454 case IIO_MOD_Y: 455 - lsb_reg = BMA400_Y_AXIS_LSB_REG; 455 + lsb_reg = BMA400_ACC_Y_LSB_REG; 456 456 break; 457 457 case IIO_MOD_Z: 458 - lsb_reg = BMA400_Z_AXIS_LSB_REG; 458 + lsb_reg = BMA400_ACC_Z_LSB_REG; 459 459 break; 460 460 default: 461 461 dev_err(data->dev, "invalid axis channel modifier\n"); ··· 475 475 static void bma400_output_data_rate_from_raw(int raw, unsigned int *val, 476 476 unsigned int *val2) 477 477 { 478 - *val = BMA400_ACC_ODR_MAX_HZ >> (BMA400_ACC_ODR_MAX_RAW - raw); 479 - if (raw > BMA400_ACC_ODR_MIN_RAW) 478 + *val = BMA400_ACC_CONFIG1_ODR_MAX_HZ >> (BMA400_ACC_CONFIG1_ODR_MAX_RAW - raw); 479 + if (raw > BMA400_ACC_CONFIG1_ODR_MIN_RAW) 480 480 *val2 = 0; 481 481 else 482 482 *val2 = 500000; ··· 494 494 * Runs at a fixed rate in low-power mode. See section 4.3 495 495 * in the datasheet. 496 496 */ 497 - bma400_output_data_rate_from_raw(BMA400_ACC_ODR_LP_RAW, 497 + bma400_output_data_rate_from_raw(BMA400_ACC_CONFIG1_ODR_LP_RAW, 498 498 &data->sample_freq.hz, 499 499 &data->sample_freq.uhz); 500 500 return 0; ··· 507 507 if (ret) 508 508 goto error; 509 509 510 - odr = val & BMA400_ACC_ODR_MASK; 511 - if (odr < BMA400_ACC_ODR_MIN_RAW || 512 - odr > BMA400_ACC_ODR_MAX_RAW) { 510 + odr = val & BMA400_ACC_CONFIG1_ODR_MASK; 511 + if (odr < BMA400_ACC_CONFIG1_ODR_MIN_RAW || 512 + odr > BMA400_ACC_CONFIG1_ODR_MAX_RAW) { 513 513 ret = -EINVAL; 514 514 goto error; 515 515 } ··· 539 539 unsigned int val; 540 540 int ret; 541 541 542 - if (hz >= BMA400_ACC_ODR_MIN_WHOLE_HZ) { 543 - if (uhz || hz > BMA400_ACC_ODR_MAX_HZ) 542 + if (hz >= BMA400_ACC_CONFIG1_ODR_MIN_WHOLE_HZ) { 543 + if (uhz || hz > BMA400_ACC_CONFIG1_ODR_MAX_HZ) 544 544 return -EINVAL; 545 545 546 546 /* Note this works because MIN_WHOLE_HZ is odd */ 547 547 idx = __ffs(hz); 548 548 549 - if (hz >> idx != BMA400_ACC_ODR_MIN_WHOLE_HZ) 549 + if (hz >> idx != BMA400_ACC_CONFIG1_ODR_MIN_WHOLE_HZ) 550 550 return -EINVAL; 551 551 552 - idx += BMA400_ACC_ODR_MIN_RAW + 1; 553 - } else if (hz == BMA400_ACC_ODR_MIN_HZ && uhz == 500000) { 554 - idx = BMA400_ACC_ODR_MIN_RAW; 552 + idx += BMA400_ACC_CONFIG1_ODR_MIN_RAW + 1; 553 + } else if (hz == BMA400_ACC_CONFIG1_ODR_MIN_HZ && uhz == 500000) { 554 + idx = BMA400_ACC_CONFIG1_ODR_MIN_RAW; 555 555 } else { 556 556 return -EINVAL; 557 557 } ··· 561 561 return ret; 562 562 563 563 /* preserve the range and normal mode osr */ 564 - odr = (~BMA400_ACC_ODR_MASK & val) | idx; 564 + odr = (~BMA400_ACC_CONFIG1_ODR_MASK & val) | idx; 565 565 566 566 ret = regmap_write(data->regmap, BMA400_ACC_CONFIG1_REG, odr); 567 567 if (ret) ··· 592 592 return ret; 593 593 } 594 594 595 - osr = (val & BMA400_LP_OSR_MASK) >> BMA400_LP_OSR_SHIFT; 595 + osr = (val & BMA400_ACC_CONFIG0_LP_OSR_MASK) >> BMA400_LP_OSR_SHIFT; 596 596 597 597 data->oversampling_ratio = osr; 598 598 return 0; ··· 603 603 return ret; 604 604 } 605 605 606 - osr = (val & BMA400_NP_OSR_MASK) >> BMA400_NP_OSR_SHIFT; 606 + osr = (val & BMA400_ACC_CONFIG1_NP_OSR_MASK) >> BMA400_NP_OSR_SHIFT; 607 607 608 608 data->oversampling_ratio = osr; 609 609 return 0; ··· 637 637 return ret; 638 638 639 639 ret = regmap_write(data->regmap, BMA400_ACC_CONFIG0_REG, 640 - (acc_config & ~BMA400_LP_OSR_MASK) | 640 + (acc_config & ~BMA400_ACC_CONFIG0_LP_OSR_MASK) | 641 641 (val << BMA400_LP_OSR_SHIFT)); 642 642 if (ret) { 643 643 dev_err(data->dev, "Failed to write out OSR\n"); ··· 653 653 return ret; 654 654 655 655 ret = regmap_write(data->regmap, BMA400_ACC_CONFIG1_REG, 656 - (acc_config & ~BMA400_NP_OSR_MASK) | 656 + (acc_config & ~BMA400_ACC_CONFIG1_NP_OSR_MASK) | 657 657 (val << BMA400_NP_OSR_SHIFT)); 658 658 if (ret) { 659 659 dev_err(data->dev, "Failed to write out OSR\n"); ··· 679 679 /* Note this works because BMA400_SCALE_MIN is odd */ 680 680 raw = __ffs(val); 681 681 682 - if (val >> raw != BMA400_SCALE_MIN) 682 + if (val >> raw != BMA400_ACC_SCALE_MIN) 683 683 return -EINVAL; 684 684 685 685 return raw; ··· 695 695 if (ret) 696 696 return ret; 697 697 698 - raw_scale = (val & BMA400_ACC_SCALE_MASK) >> BMA400_SCALE_SHIFT; 698 + raw_scale = (val & BMA400_ACC_CONFIG1_ACC_RANGE_MASK) >> BMA400_ACC_RANGE_SHIFT; 699 699 if (raw_scale > BMA400_TWO_BITS_MASK) 700 700 return -EINVAL; 701 701 702 - data->scale = BMA400_SCALE_MIN << raw_scale; 702 + data->scale = BMA400_ACC_SCALE_MIN << raw_scale; 703 703 704 704 return 0; 705 705 } ··· 719 719 return raw; 720 720 721 721 ret = regmap_write(data->regmap, BMA400_ACC_CONFIG1_REG, 722 - (acc_config & ~BMA400_ACC_SCALE_MASK) | 723 - (raw << BMA400_SCALE_SHIFT)); 722 + (acc_config & ~BMA400_ACC_CONFIG1_ACC_RANGE_MASK) | 723 + (raw << BMA400_ACC_RANGE_SHIFT)); 724 724 if (ret) 725 725 return ret; 726 726 ··· 786 786 return 0; 787 787 788 788 ret = regmap_update_bits(data->regmap, BMA400_INT_CONFIG1_REG, 789 - BMA400_STEP_INT_MSK, 790 - FIELD_PREP(BMA400_STEP_INT_MSK, val ? 1 : 0)); 789 + BMA400_INT_CONFIG1_STEP_INT_MASK, 790 + FIELD_PREP(BMA400_INT_CONFIG1_STEP_INT_MASK, val ? 1 : 0)); 791 791 if (ret) 792 792 return ret; 793 793 data->steps_enabled = val; ··· 826 826 for (i = 0; i + 1 < ARRAY_SIZE(bma400_scales); i += 2) { 827 827 raw = i / 2; 828 828 bma400_scales[i] = 0; 829 - bma400_scales[i + 1] = BMA400_SCALE_MIN << raw; 829 + bma400_scales[i + 1] = BMA400_ACC_SCALE_MIN << raw; 830 830 } 831 831 } 832 832 ··· 1063 1063 return ret; 1064 1064 case IIO_CHAN_INFO_SCALE: 1065 1065 if (val != 0 || 1066 - val2 < BMA400_SCALE_MIN || val2 > BMA400_SCALE_MAX) 1066 + val2 < BMA400_ACC_SCALE_MIN || val2 > BMA400_ACC_SCALE_MAX) 1067 1067 return -EINVAL; 1068 1068 1069 1069 mutex_lock(&data->mutex); ··· 1114 1114 case IIO_ACCEL: 1115 1115 switch (dir) { 1116 1116 case IIO_EV_DIR_RISING: 1117 - return FIELD_GET(BMA400_INT_GEN1_MSK, 1117 + return FIELD_GET(BMA400_INT_CONFIG0_GEN1_MASK, 1118 1118 data->generic_event_en); 1119 1119 case IIO_EV_DIR_FALLING: 1120 - return FIELD_GET(BMA400_INT_GEN2_MSK, 1120 + return FIELD_GET(BMA400_INT_CONFIG0_GEN2_MASK, 1121 1121 data->generic_event_en); 1122 1122 case IIO_EV_DIR_SINGLETAP: 1123 - return FIELD_GET(BMA400_S_TAP_MSK, 1123 + return FIELD_GET(BMA400_INT_CONFIG1_S_TAP_MASK, 1124 1124 data->tap_event_en_bitmask); 1125 1125 case IIO_EV_DIR_DOUBLETAP: 1126 - return FIELD_GET(BMA400_D_TAP_MSK, 1126 + return FIELD_GET(BMA400_INT_CONFIG1_D_TAP_MASK, 1127 1127 data->tap_event_en_bitmask); 1128 1128 default: 1129 1129 return -EINVAL; ··· 1146 1146 return ret; 1147 1147 1148 1148 ret = regmap_update_bits(data->regmap, BMA400_INT12_MAP_REG, 1149 - BMA400_STEP_INT_MSK, 1150 - FIELD_PREP(BMA400_STEP_INT_MSK, 1149 + BMA400_INT_CONFIG1_STEP_INT_MASK, 1150 + FIELD_PREP(BMA400_INT_CONFIG1_STEP_INT_MASK, 1151 1151 state)); 1152 1152 if (ret) 1153 1153 return ret; ··· 1164 1164 1165 1165 switch (dir) { 1166 1166 case IIO_EV_DIR_RISING: 1167 - reg = BMA400_GEN1INT_CONFIG0; 1168 - msk = BMA400_INT_GEN1_MSK; 1167 + reg = BMA400_GEN1INT_CONFIG0_REG; 1168 + msk = BMA400_INT_CONFIG0_GEN1_MASK; 1169 1169 value = 2; 1170 - set_mask_bits(&field_value, BMA400_INT_GEN1_MSK, 1171 - FIELD_PREP(BMA400_INT_GEN1_MSK, state)); 1170 + set_mask_bits(&field_value, BMA400_INT_CONFIG0_GEN1_MASK, 1171 + FIELD_PREP(BMA400_INT_CONFIG0_GEN1_MASK, state)); 1172 1172 break; 1173 1173 case IIO_EV_DIR_FALLING: 1174 - reg = BMA400_GEN2INT_CONFIG0; 1175 - msk = BMA400_INT_GEN2_MSK; 1174 + reg = BMA400_GEN2INT_CONFIG0_REG; 1175 + msk = BMA400_INT_CONFIG0_GEN2_MASK; 1176 1176 value = 0; 1177 - set_mask_bits(&field_value, BMA400_INT_GEN2_MSK, 1178 - FIELD_PREP(BMA400_INT_GEN2_MSK, state)); 1177 + set_mask_bits(&field_value, BMA400_INT_CONFIG0_GEN2_MASK, 1178 + FIELD_PREP(BMA400_INT_CONFIG0_GEN2_MASK, state)); 1179 1179 break; 1180 1180 default: 1181 1181 return -EINVAL; ··· 1240 1240 } 1241 1241 1242 1242 ret = regmap_update_bits(data->regmap, BMA400_INT12_MAP_REG, 1243 - BMA400_S_TAP_MSK, 1244 - FIELD_PREP(BMA400_S_TAP_MSK, state)); 1243 + BMA400_INT_CONFIG1_S_TAP_MASK, 1244 + FIELD_PREP(BMA400_INT_CONFIG1_S_TAP_MASK, state)); 1245 1245 if (ret) 1246 1246 return ret; 1247 1247 1248 1248 switch (dir) { 1249 1249 case IIO_EV_DIR_SINGLETAP: 1250 - mask = BMA400_S_TAP_MSK; 1251 - set_mask_bits(&field_value, BMA400_S_TAP_MSK, 1252 - FIELD_PREP(BMA400_S_TAP_MSK, state)); 1250 + mask = BMA400_INT_CONFIG1_S_TAP_MASK; 1251 + set_mask_bits(&field_value, BMA400_INT_CONFIG1_S_TAP_MASK, 1252 + FIELD_PREP(BMA400_INT_CONFIG1_S_TAP_MASK, state)); 1253 1253 break; 1254 1254 case IIO_EV_DIR_DOUBLETAP: 1255 - mask = BMA400_D_TAP_MSK; 1256 - set_mask_bits(&field_value, BMA400_D_TAP_MSK, 1257 - FIELD_PREP(BMA400_D_TAP_MSK, state)); 1255 + mask = BMA400_INT_CONFIG1_D_TAP_MASK; 1256 + set_mask_bits(&field_value, BMA400_INT_CONFIG1_D_TAP_MASK, 1257 + FIELD_PREP(BMA400_INT_CONFIG1_D_TAP_MASK, state)); 1258 1258 break; 1259 1259 default: 1260 1260 return -EINVAL; ··· 1340 1340 { 1341 1341 switch (dir) { 1342 1342 case IIO_EV_DIR_FALLING: 1343 - return BMA400_GEN2INT_CONFIG0; 1343 + return BMA400_GEN2INT_CONFIG0_REG; 1344 1344 case IIO_EV_DIR_RISING: 1345 - return BMA400_GEN1INT_CONFIG0; 1345 + return BMA400_GEN1INT_CONFIG0_REG; 1346 1346 default: 1347 1347 return -EINVAL; 1348 1348 } ··· 1393 1393 ret = regmap_read(data->regmap, reg, val); 1394 1394 if (ret) 1395 1395 return ret; 1396 - *val = FIELD_GET(BMA400_GEN_HYST_MSK, *val); 1396 + *val = FIELD_GET(BMA400_GENINT_CONFIG0_HYST_MASK, *val); 1397 1397 return IIO_VAL_INT; 1398 1398 default: 1399 1399 return -EINVAL; ··· 1401 1401 case IIO_EV_TYPE_GESTURE: 1402 1402 switch (info) { 1403 1403 case IIO_EV_INFO_VALUE: 1404 - ret = regmap_read(data->regmap, BMA400_TAP_CONFIG, 1404 + ret = regmap_read(data->regmap, BMA400_TAP_CONFIG_REG, 1405 1405 &reg_val); 1406 1406 if (ret) 1407 1407 return ret; 1408 1408 1409 - *val = FIELD_GET(BMA400_TAP_SEN_MSK, reg_val); 1409 + *val = FIELD_GET(BMA400_TAP_CONFIG_SEN_MASK, reg_val); 1410 1410 return IIO_VAL_INT; 1411 1411 case IIO_EV_INFO_RESET_TIMEOUT: 1412 - ret = regmap_read(data->regmap, BMA400_TAP_CONFIG1, 1412 + ret = regmap_read(data->regmap, BMA400_TAP_CONFIG1_REG, 1413 1413 &reg_val); 1414 1414 if (ret) 1415 1415 return ret; 1416 1416 1417 - raw = FIELD_GET(BMA400_TAP_QUIET_MSK, reg_val); 1417 + raw = FIELD_GET(BMA400_TAP_CONFIG1_QUIET_MASK, reg_val); 1418 1418 *val = 0; 1419 1419 *val2 = tap_reset_timeout[raw]; 1420 1420 return IIO_VAL_INT_PLUS_MICRO; 1421 1421 case IIO_EV_INFO_TAP2_MIN_DELAY: 1422 - ret = regmap_read(data->regmap, BMA400_TAP_CONFIG1, 1422 + ret = regmap_read(data->regmap, BMA400_TAP_CONFIG1_REG, 1423 1423 &reg_val); 1424 1424 if (ret) 1425 1425 return ret; 1426 1426 1427 - raw = FIELD_GET(BMA400_TAP_QUIETDT_MSK, reg_val); 1427 + raw = FIELD_GET(BMA400_TAP_CONFIG1_QUIETDT_MASK, reg_val); 1428 1428 *val = 0; 1429 1429 *val2 = double_tap2_min_delay[raw]; 1430 1430 return IIO_VAL_INT_PLUS_MICRO; ··· 1480 1480 return -EINVAL; 1481 1481 1482 1482 return regmap_update_bits(data->regmap, reg, 1483 - BMA400_GEN_HYST_MSK, 1484 - FIELD_PREP(BMA400_GEN_HYST_MSK, 1483 + BMA400_GENINT_CONFIG0_HYST_MASK, 1484 + FIELD_PREP(BMA400_GENINT_CONFIG0_HYST_MASK, 1485 1485 val)); 1486 1486 default: 1487 1487 return -EINVAL; ··· 1493 1493 return -EINVAL; 1494 1494 1495 1495 return regmap_update_bits(data->regmap, 1496 - BMA400_TAP_CONFIG, 1497 - BMA400_TAP_SEN_MSK, 1498 - FIELD_PREP(BMA400_TAP_SEN_MSK, 1496 + BMA400_TAP_CONFIG_REG, 1497 + BMA400_TAP_CONFIG_SEN_MASK, 1498 + FIELD_PREP(BMA400_TAP_CONFIG_SEN_MASK, 1499 1499 val)); 1500 1500 case IIO_EV_INFO_RESET_TIMEOUT: 1501 1501 raw = usec_to_tapreg_raw(val2, tap_reset_timeout); ··· 1503 1503 return -EINVAL; 1504 1504 1505 1505 return regmap_update_bits(data->regmap, 1506 - BMA400_TAP_CONFIG1, 1507 - BMA400_TAP_QUIET_MSK, 1508 - FIELD_PREP(BMA400_TAP_QUIET_MSK, 1506 + BMA400_TAP_CONFIG1_REG, 1507 + BMA400_TAP_CONFIG1_QUIET_MASK, 1508 + FIELD_PREP(BMA400_TAP_CONFIG1_QUIET_MASK, 1509 1509 raw)); 1510 1510 case IIO_EV_INFO_TAP2_MIN_DELAY: 1511 1511 raw = usec_to_tapreg_raw(val2, double_tap2_min_delay); ··· 1513 1513 return -EINVAL; 1514 1514 1515 1515 return regmap_update_bits(data->regmap, 1516 - BMA400_TAP_CONFIG1, 1517 - BMA400_TAP_QUIETDT_MSK, 1518 - FIELD_PREP(BMA400_TAP_QUIETDT_MSK, 1516 + BMA400_TAP_CONFIG1_REG, 1517 + BMA400_TAP_CONFIG1_QUIETDT_MASK, 1518 + FIELD_PREP(BMA400_TAP_CONFIG1_QUIETDT_MASK, 1519 1519 raw)); 1520 1520 default: 1521 1521 return -EINVAL; ··· 1533 1533 int ret; 1534 1534 1535 1535 ret = regmap_update_bits(data->regmap, BMA400_INT_CONFIG0_REG, 1536 - BMA400_INT_DRDY_MSK, 1537 - FIELD_PREP(BMA400_INT_DRDY_MSK, state)); 1536 + BMA400_INT_CONFIG0_DRDY_MASK, 1537 + FIELD_PREP(BMA400_INT_CONFIG0_DRDY_MASK, state)); 1538 1538 if (ret) 1539 1539 return ret; 1540 1540 1541 1541 return regmap_update_bits(data->regmap, BMA400_INT1_MAP_REG, 1542 - BMA400_INT_DRDY_MSK, 1543 - FIELD_PREP(BMA400_INT_DRDY_MSK, state)); 1542 + BMA400_INT_CONFIG0_DRDY_MASK, 1543 + FIELD_PREP(BMA400_INT_CONFIG0_DRDY_MASK, state)); 1544 1544 } 1545 1545 1546 1546 static const unsigned long bma400_avail_scan_masks[] = { ··· 1578 1578 mutex_lock(&data->mutex); 1579 1579 1580 1580 /* bulk read six registers, with the base being the LSB register */ 1581 - ret = regmap_bulk_read(data->regmap, BMA400_X_AXIS_LSB_REG, 1581 + ret = regmap_bulk_read(data->regmap, BMA400_ACC_X_LSB_REG, 1582 1582 &data->buffer.buff, sizeof(data->buffer.buff)); 1583 1583 if (ret) 1584 1584 goto unlock_err; ··· 1628 1628 * Disable all advance interrupts if interrupt engine overrun occurs. 1629 1629 * See section 4.7 "Interrupt engine overrun" in datasheet v1.2. 1630 1630 */ 1631 - if (FIELD_GET(BMA400_INT_ENG_OVRUN_MSK, le16_to_cpu(data->status))) { 1631 + if (FIELD_GET(BMA400_INT_STAT_ENG_OVRRUN_MASK, le16_to_cpu(data->status))) { 1632 1632 bma400_disable_adv_interrupt(data); 1633 1633 dev_err(data->dev, "Interrupt engine overrun\n"); 1634 1634 goto unlock_err; 1635 1635 } 1636 1636 1637 - if (FIELD_GET(BMA400_INT_S_TAP_MSK, le16_to_cpu(data->status))) 1637 + if (FIELD_GET(BMA400_INT_STAT1_S_TAP_MASK, le16_to_cpu(data->status))) 1638 1638 iio_push_event(indio_dev, 1639 1639 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, 1640 1640 IIO_MOD_X_OR_Y_OR_Z, ··· 1642 1642 IIO_EV_DIR_SINGLETAP), 1643 1643 timestamp); 1644 1644 1645 - if (FIELD_GET(BMA400_INT_D_TAP_MSK, le16_to_cpu(data->status))) 1645 + if (FIELD_GET(BMA400_INT_STAT1_D_TAP_MASK, le16_to_cpu(data->status))) 1646 1646 iio_push_event(indio_dev, 1647 1647 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, 1648 1648 IIO_MOD_X_OR_Y_OR_Z, ··· 1650 1650 IIO_EV_DIR_DOUBLETAP), 1651 1651 timestamp); 1652 1652 1653 - if (FIELD_GET(BMA400_INT_GEN1_MSK, le16_to_cpu(data->status))) 1653 + if (FIELD_GET(BMA400_INT_STAT0_GEN1_MASK, le16_to_cpu(data->status))) 1654 1654 ev_dir = IIO_EV_DIR_RISING; 1655 1655 1656 - if (FIELD_GET(BMA400_INT_GEN2_MSK, le16_to_cpu(data->status))) 1656 + if (FIELD_GET(BMA400_INT_STAT0_GEN2_MASK, le16_to_cpu(data->status))) 1657 1657 ev_dir = IIO_EV_DIR_FALLING; 1658 1658 1659 1659 if (ev_dir != IIO_EV_DIR_NONE) { ··· 1664 1664 timestamp); 1665 1665 } 1666 1666 1667 - if (FIELD_GET(BMA400_STEP_STAT_MASK, le16_to_cpu(data->status))) { 1667 + if (FIELD_GET(BMA400_INT_STAT1_STEP_INT_MASK, le16_to_cpu(data->status))) { 1668 1668 iio_push_event(indio_dev, 1669 1669 IIO_MOD_EVENT_CODE(IIO_STEPS, 0, IIO_NO_MOD, 1670 1670 IIO_EV_TYPE_CHANGE, ··· 1686 1686 } 1687 1687 } 1688 1688 1689 - if (FIELD_GET(BMA400_INT_DRDY_MSK, le16_to_cpu(data->status))) { 1689 + if (FIELD_GET(BMA400_INT_STAT0_DRDY_MASK, le16_to_cpu(data->status))) { 1690 1690 mutex_unlock(&data->mutex); 1691 1691 iio_trigger_poll_nested(data->trig); 1692 1692 return IRQ_HANDLED;