tjh.dev / kernel
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Merge tag 'irq-urgent-2022-06-19' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull irq fixes from Thomas Gleixner:
"A set of interrupt subsystem updates:

Core:

- Ensure runtime power management for chained interrupts

Drivers:

- A collection of OF node refcount fixes

- Unbreak MIPS uniprocessor builds

- Fix xilinx interrupt controller Kconfig dependencies

- Add a missing compatible string to the Uniphier driver"

* tag 'irq-urgent-2022-06-19' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
irqchip/loongson-liointc: Use architecture register to get coreid
irqchip/uniphier-aidet: Add compatible string for NX1 SoC
dt-bindings: interrupt-controller/uniphier-aidet: Add bindings for NX1 SoC
irqchip/realtek-rtl: Fix refcount leak in map_interrupts
irqchip/gic-v3: Fix refcount leak in gic_populate_ppi_partitions
irqchip/gic-v3: Fix error handling in gic_populate_ppi_partitions
irqchip/apple-aic: Fix refcount leak in aic_of_ic_init
irqchip/apple-aic: Fix refcount leak in build_fiq_affinity
irqchip/gic/realview: Fix refcount leak in realview_gic_of_init
irqchip/xilinx: Remove microblaze+zynq dependency
genirq: PM: Use runtime PM for chained interrupts

Linus Torvalds 36da9f5f bc94632c

+23 -6
+1
Documentation/devicetree/bindings/interrupt-controller/socionext,uniphier-aidet.yaml
··· 30 30 - socionext,uniphier-ld11-aidet 31 31 - socionext,uniphier-ld20-aidet 32 32 - socionext,uniphier-pxs3-aidet 33 + - socionext,uniphier-nx1-aidet 33 34 34 35 reg: 35 36 maxItems: 1
+1 -1
drivers/irqchip/Kconfig
··· 298 298 299 299 config XILINX_INTC 300 300 bool "Xilinx Interrupt Controller IP" 301 - depends on MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP 301 + depends on OF 302 302 select IRQ_DOMAIN 303 303 help 304 304 Support for the Xilinx Interrupt Controller IP core.
+2
drivers/irqchip/irq-apple-aic.c
··· 1035 1035 continue; 1036 1036 1037 1037 cpu = of_cpu_node_to_id(cpu_node); 1038 + of_node_put(cpu_node); 1038 1039 if (WARN_ON(cpu < 0)) 1039 1040 continue; 1040 1041 ··· 1144 1143 for_each_child_of_node(affs, chld) 1145 1144 build_fiq_affinity(irqc, chld); 1146 1145 } 1146 + of_node_put(affs); 1147 1147 1148 1148 set_handle_irq(aic_handle_irq); 1149 1149 set_handle_fiq(aic_handle_fiq);
+1
drivers/irqchip/irq-gic-realview.c
··· 57 57 58 58 /* The PB11MPCore GIC needs to be configured in the syscon */ 59 59 map = syscon_node_to_regmap(np); 60 + of_node_put(np); 60 61 if (!IS_ERR(map)) { 61 62 /* new irq mode with no DCC */ 62 63 regmap_write(map, REALVIEW_SYS_LOCK_OFFSET,
+5 -2
drivers/irqchip/irq-gic-v3.c
··· 1932 1932 1933 1933 gic_data.ppi_descs = kcalloc(gic_data.ppi_nr, sizeof(*gic_data.ppi_descs), GFP_KERNEL); 1934 1934 if (!gic_data.ppi_descs) 1935 - return; 1935 + goto out_put_node; 1936 1936 1937 1937 nr_parts = of_get_child_count(parts_node); 1938 1938 ··· 1973 1973 continue; 1974 1974 1975 1975 cpu = of_cpu_node_to_id(cpu_node); 1976 - if (WARN_ON(cpu < 0)) 1976 + if (WARN_ON(cpu < 0)) { 1977 + of_node_put(cpu_node); 1977 1978 continue; 1979 + } 1978 1980 1979 1981 pr_cont("%pOF[%d] ", cpu_node, cpu); 1980 1982 1981 1983 cpumask_set_cpu(cpu, &part->mask); 1984 + of_node_put(cpu_node); 1982 1985 } 1983 1986 1984 1987 pr_cont("}\n");
+7 -1
drivers/irqchip/irq-loongson-liointc.c
··· 39 39 40 40 #define LIOINTC_ERRATA_IRQ 10 41 41 42 + #if defined(CONFIG_MIPS) 43 + #define liointc_core_id get_ebase_cpunum() 44 + #else 45 + #define liointc_core_id get_csr_cpuid() 46 + #endif 47 + 42 48 struct liointc_handler_data { 43 49 struct liointc_priv *priv; 44 50 u32 parent_int_map; ··· 63 57 struct liointc_handler_data *handler = irq_desc_get_handler_data(desc); 64 58 struct irq_chip *chip = irq_desc_get_chip(desc); 65 59 struct irq_chip_generic *gc = handler->priv->gc; 66 - int core = cpu_logical_map(smp_processor_id()) % LIOINTC_NUM_CORES; 60 + int core = liointc_core_id % LIOINTC_NUM_CORES; 67 61 u32 pending; 68 62 69 63 chained_irq_enter(chip, desc);
+1 -1
drivers/irqchip/irq-realtek-rtl.c
··· 134 134 if (!cpu_ictl) 135 135 return -EINVAL; 136 136 ret = of_property_read_u32(cpu_ictl, "#interrupt-cells", &tmp); 137 + of_node_put(cpu_ictl); 137 138 if (ret || tmp != 1) 138 139 return -EINVAL; 139 - of_node_put(cpu_ictl); 140 140 141 141 cpu_int = be32_to_cpup(imap + 2); 142 142 if (cpu_int > 7 || cpu_int < 2)
+1
drivers/irqchip/irq-uniphier-aidet.c
··· 237 237 { .compatible = "socionext,uniphier-ld11-aidet" }, 238 238 { .compatible = "socionext,uniphier-ld20-aidet" }, 239 239 { .compatible = "socionext,uniphier-pxs3-aidet" }, 240 + { .compatible = "socionext,uniphier-nx1-aidet" }, 240 241 { /* sentinel */ } 241 242 }; 242 243
+4 -1
kernel/irq/chip.c
··· 1006 1006 if (desc->irq_data.chip != &no_irq_chip) 1007 1007 mask_ack_irq(desc); 1008 1008 irq_state_set_disabled(desc); 1009 - if (is_chained) 1009 + if (is_chained) { 1010 1010 desc->action = NULL; 1011 + WARN_ON(irq_chip_pm_put(irq_desc_get_irq_data(desc))); 1012 + } 1011 1013 desc->depth = 1; 1012 1014 } 1013 1015 desc->handle_irq = handle; ··· 1035 1033 irq_settings_set_norequest(desc); 1036 1034 irq_settings_set_nothread(desc); 1037 1035 desc->action = &chained_action; 1036 + WARN_ON(irq_chip_pm_get(irq_desc_get_irq_data(desc))); 1038 1037 irq_activate_and_startup(desc, IRQ_RESEND); 1039 1038 } 1040 1039 }