tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux

Pull arm64 fixes from Will Deacon:
"Small crop of relatively boring arm64 fixes for -rc3.

That's not to say we don't have any juicy bugs, however, it's just
that fixes for those are likely to come via -mm and -tip for a hugetlb
and an atomics issue respectively. I get left with the
documentation...

- Fix detection of "ClearBHB" and "Hinted Conditional Branch" features

- Fix broken wildcarding for Arm PMU MAINTAINERS entry

- Add missing documentation for userspace-visible ID register fields"

* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
arm64: Document missing userspace visible fields in ID_AA64ISAR2_EL1
arm64/hbc: Document HWCAP2_HBC
arm64/sme: Include ID_AA64PFR1_EL1.SME in cpu-feature-registers.rst
arm64: cpufeature: Fix CLRBHB and BC detection
MAINTAINERS: Use wildcard pattern for ARM PMU headers

Linus Torvalds 36fcf381 b61ec8d0

+24 -4
+12
Documentation/arch/arm64/cpu-feature-registers.rst
··· 175 175 +------------------------------+---------+---------+ 176 176 | Name | bits | visible | 177 177 +------------------------------+---------+---------+ 178 + | SME | [27-24] | y | 179 + +------------------------------+---------+---------+ 178 180 | MTE | [11-8] | y | 179 181 +------------------------------+---------+---------+ 180 182 | SSBS | [7-4] | y | ··· 290 288 +------------------------------+---------+---------+ 291 289 | Name | bits | visible | 292 290 +------------------------------+---------+---------+ 291 + | CSSC | [55-52] | y | 292 + +------------------------------+---------+---------+ 293 + | RPRFM | [51-48] | y | 294 + +------------------------------+---------+---------+ 295 + | BC | [23-20] | y | 296 + +------------------------------+---------+---------+ 293 297 | MOPS | [19-16] | y | 298 + +------------------------------+---------+---------+ 299 + | APA3 | [15-12] | y | 300 + +------------------------------+---------+---------+ 301 + | GPA3 | [11-8] | y | 294 302 +------------------------------+---------+---------+ 295 303 | RPRES | [7-4] | y | 296 304 +------------------------------+---------+---------+
+3
Documentation/arch/arm64/elf_hwcaps.rst
··· 305 305 HWCAP2_MOPS 306 306 Functionality implied by ID_AA64ISAR2_EL1.MOPS == 0b0001. 307 307 308 + HWCAP2_HBC 309 + Functionality implied by ID_AA64ISAR2_EL1.BC == 0b0001. 310 + 308 311 4. Unused AT_HWCAP bits 309 312 ----------------------- 310 313
+1 -1
MAINTAINERS
··· 1662 1662 F: arch/arm*/kernel/hw_breakpoint.c 1663 1663 F: arch/arm*/kernel/perf_* 1664 1664 F: drivers/perf/ 1665 - F: include/linux/perf/arm_pmu.h 1665 + F: include/linux/perf/arm_pmu*.h 1666 1666 1667 1667 ARM PORT 1668 1668 M: Russell King <linux@armlinux.org.uk>
+1 -1
arch/arm64/include/asm/cpufeature.h
··· 663 663 isar2 = read_sanitised_ftr_reg(SYS_ID_AA64ISAR2_EL1); 664 664 665 665 return cpuid_feature_extract_unsigned_field(isar2, 666 - ID_AA64ISAR2_EL1_BC_SHIFT); 666 + ID_AA64ISAR2_EL1_CLRBHB_SHIFT); 667 667 } 668 668 669 669 const struct cpumask *system_32bit_el0_cpumask(void);
+2 -1
arch/arm64/kernel/cpufeature.c
··· 222 222 static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { 223 223 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, 0), 224 224 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, 0), 225 - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0), 225 + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CLRBHB_SHIFT, 4, 0), 226 + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0), 226 227 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_MOPS_SHIFT, 4, 0), 227 228 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 228 229 FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0),
+5 -1
arch/arm64/tools/sysreg
··· 1347 1347 0b0000 NI 1348 1348 0b0001 IMP 1349 1349 EndEnum 1350 - Res0 47:28 1350 + Res0 47:32 1351 + UnsignedEnum 31:28 CLRBHB 1352 + 0b0000 NI 1353 + 0b0001 IMP 1354 + EndEnum 1351 1355 UnsignedEnum 27:24 PAC_frac 1352 1356 0b0000 NI 1353 1357 0b0001 IMP