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drm/i915/cx0: Fix port to PLL ID mapping on BMG

The intel_port_to_tc() call in mtl_port_to_pll_id() assumed that all
TypeC DDI ports are connected to a TypeC PHY. This is not true on BMG
where all the ports - including the PORT_TC1..4 TypeC DDI ports - are
connected to a non-TypeC PHY. For these ports intel_port_to_tc()
returns TC_PORT_NONE, which results in an incorrect port -> PLL ID
mapping. Fix this up by using the expected PORT_TC1..4 port ->
TC_PORT_1..4 tc_port mapping on BMG as well.

Fixes: ca1eda5cd476c ("drm/i915/cx0: Add MTL+ .get_dplls hook")
Cc: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patch.msgid.link/20251120172358.1282765-1-imre.deak@intel.com

Imre Deak 370f45b1 a5f0cc8e

+9 -7
+4 -3
drivers/gpu/drm/i915/display/intel_ddi.c
··· 4294 4294 } 4295 4295 4296 4296 /* 4297 - * Get the configuration for either a port using a C10 PHY PLL, or in the case of 4298 - * the PTL port B eDP on TypeC PHY case the configuration of a port using a C20 4299 - * PHY PLL. 4297 + * Get the configuration for either a port using a C10 PHY PLL, or a port using a 4298 + * C20 PHY PLL in the cases of: 4299 + * - BMG port A/B 4300 + * - PTL port B eDP over TypeC PHY 4300 4301 */ 4301 4302 static void mtl_ddi_non_tc_phy_get_config(struct intel_encoder *encoder, 4302 4303 struct intel_crtc_state *crtc_state)
+5 -4
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
··· 206 206 enum intel_dpll_id mtl_port_to_pll_id(struct intel_display *display, enum port port) 207 207 { 208 208 if (port >= PORT_TC1) 209 - return icl_tc_port_to_pll_id(intel_port_to_tc(display, port)); 209 + return icl_tc_port_to_pll_id(port - PORT_TC1 + TC_PORT_1); 210 210 211 211 switch (port) { 212 212 case PORT_A: ··· 3507 3507 } 3508 3508 3509 3509 /* 3510 - * Get the PLL for either a port using a C10 PHY PLL, or in the 3511 - * PTL port B eDP over TypeC PHY case, the PLL for a port using 3512 - * a C20 PHY PLL. 3510 + * Get the PLL for either a port using a C10 PHY PLL, or for a port using a 3511 + * C20 PHY PLL in the cases of: 3512 + * - BMG port A/B 3513 + * - PTL port B eDP over TypeC PHY 3513 3514 */ 3514 3515 static int mtl_get_non_tc_phy_dpll(struct intel_atomic_state *state, 3515 3516 struct intel_crtc *crtc,