Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'riscv/for-v5.5-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

Pull RISC-V fixes from Paul Walmsley:
"Two fixes for RISC-V:

- Clear FP registers during boot when FP support is present, rather
than when they aren't present

- Move the header files associated with the SiFive L2 cache
controller to drivers/soc (where the code was recently moved)"

* tag 'riscv/for-v5.5-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
riscv: Fixup obvious bug for fp-regs reset
riscv: move sifive_l2_cache.h to include/soc

+6 -6
+3 -3
arch/riscv/include/asm/sifive_l2_cache.h include/soc/sifive/sifive_l2_cache.h
··· 4 4 * 5 5 */ 6 6 7 - #ifndef _ASM_RISCV_SIFIVE_L2_CACHE_H 8 - #define _ASM_RISCV_SIFIVE_L2_CACHE_H 7 + #ifndef __SOC_SIFIVE_L2_CACHE_H 8 + #define __SOC_SIFIVE_L2_CACHE_H 9 9 10 10 extern int register_sifive_l2_error_notifier(struct notifier_block *nb); 11 11 extern int unregister_sifive_l2_error_notifier(struct notifier_block *nb); ··· 13 13 #define SIFIVE_L2_ERR_TYPE_CE 0 14 14 #define SIFIVE_L2_ERR_TYPE_UE 1 15 15 16 - #endif /* _ASM_RISCV_SIFIVE_L2_CACHE_H */ 16 + #endif /* __SOC_SIFIVE_L2_CACHE_H */
+1 -1
arch/riscv/kernel/head.S
··· 251 251 #ifdef CONFIG_FPU 252 252 csrr t0, CSR_MISA 253 253 andi t0, t0, (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D) 254 - bnez t0, .Lreset_regs_done 254 + beqz t0, .Lreset_regs_done 255 255 256 256 li t1, SR_FS 257 257 csrs CSR_STATUS, t1
+1 -1
drivers/edac/sifive_edac.c
··· 10 10 #include <linux/edac.h> 11 11 #include <linux/platform_device.h> 12 12 #include "edac_module.h" 13 - #include <asm/sifive_l2_cache.h> 13 + #include <soc/sifive/sifive_l2_cache.h> 14 14 15 15 #define DRVNAME "sifive_edac" 16 16
+1 -1
drivers/soc/sifive/sifive_l2_cache.c
··· 9 9 #include <linux/interrupt.h> 10 10 #include <linux/of_irq.h> 11 11 #include <linux/of_address.h> 12 - #include <asm/sifive_l2_cache.h> 12 + #include <soc/sifive/sifive_l2_cache.h> 13 13 14 14 #define SIFIVE_L2_DIRECCFIX_LOW 0x100 15 15 #define SIFIVE_L2_DIRECCFIX_HIGH 0x104