Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu: add ACA support for vcn v4.0.3
v1:
Add ACA support for vcn v4.0.3.
v2:
- split VCN ACA(v1) to 2 parts: vcn and jpeg.
- move mmSMNAID_AID0_MCA_SMU to amdgpu_aca.h file.
v3:
- split JPEG ACA to another patch.
Signed-off-by: Yang Wang <kevinyang.wang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Yang Wang
and committed by
Alex Deucher
3748c439
abfcf956
+85
+85
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
+85
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
···
1915
1915
.reset_ras_error_count = vcn_v4_0_3_reset_ras_error_count,
1916
1916
};
1917
1917
1918
+
static int vcn_v4_0_3_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank,
1919
+
enum aca_smu_type type, void *data)
1920
+
{
1921
+
struct aca_bank_info info;
1922
+
u64 misc0;
1923
+
int ret;
1924
+
1925
+
ret = aca_bank_info_decode(bank, &info);
1926
+
if (ret)
1927
+
return ret;
1928
+
1929
+
misc0 = bank->regs[ACA_REG_IDX_MISC0];
1930
+
switch (type) {
1931
+
case ACA_SMU_TYPE_UE:
1932
+
ret = aca_error_cache_log_bank_error(handle, &info, ACA_ERROR_TYPE_UE,
1933
+
1ULL);
1934
+
break;
1935
+
case ACA_SMU_TYPE_CE:
1936
+
ret = aca_error_cache_log_bank_error(handle, &info, ACA_ERROR_TYPE_CE,
1937
+
ACA_REG__MISC0__ERRCNT(misc0));
1938
+
break;
1939
+
default:
1940
+
return -EINVAL;
1941
+
}
1942
+
1943
+
return ret;
1944
+
}
1945
+
1946
+
/* reference to smu driver if header file */
1947
+
static int vcn_v4_0_3_err_codes[] = {
1948
+
14, 15, /* VCN */
1949
+
};
1950
+
1951
+
static bool vcn_v4_0_3_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank,
1952
+
enum aca_smu_type type, void *data)
1953
+
{
1954
+
u32 instlo;
1955
+
1956
+
instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]);
1957
+
instlo &= GENMASK(31, 1);
1958
+
1959
+
if (instlo != mmSMNAID_AID0_MCA_SMU)
1960
+
return false;
1961
+
1962
+
if (aca_bank_check_error_codes(handle->adev, bank,
1963
+
vcn_v4_0_3_err_codes,
1964
+
ARRAY_SIZE(vcn_v4_0_3_err_codes)))
1965
+
return false;
1966
+
1967
+
return true;
1968
+
}
1969
+
1970
+
static const struct aca_bank_ops vcn_v4_0_3_aca_bank_ops = {
1971
+
.aca_bank_parser = vcn_v4_0_3_aca_bank_parser,
1972
+
.aca_bank_is_valid = vcn_v4_0_3_aca_bank_is_valid,
1973
+
};
1974
+
1975
+
static const struct aca_info vcn_v4_0_3_aca_info = {
1976
+
.hwip = ACA_HWIP_TYPE_SMU,
1977
+
.mask = ACA_ERROR_UE_MASK,
1978
+
.bank_ops = &vcn_v4_0_3_aca_bank_ops,
1979
+
};
1980
+
1981
+
static int vcn_v4_0_3_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
1982
+
{
1983
+
int r;
1984
+
1985
+
r = amdgpu_ras_block_late_init(adev, ras_block);
1986
+
if (r)
1987
+
return r;
1988
+
1989
+
r = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__VCN,
1990
+
&vcn_v4_0_3_aca_info, NULL);
1991
+
if (r)
1992
+
goto late_fini;
1993
+
1994
+
return 0;
1995
+
1996
+
late_fini:
1997
+
amdgpu_ras_block_late_fini(adev, ras_block);
1998
+
1999
+
return r;
2000
+
}
2001
+
1918
2002
static struct amdgpu_vcn_ras vcn_v4_0_3_ras = {
1919
2003
.ras_block = {
1920
2004
.hw_ops = &vcn_v4_0_3_ras_hw_ops,
2005
+
.ras_late_init = vcn_v4_0_3_ras_late_init,
1921
2006
},
1922
2007
};
1923
2008