phy: renesas: phy-rcar-gen3-usb2: Add USB2.0 PHY support for RZ/V2H(P)

Add USB2.0 PHY support for RZ/V2H(P) SoC.

On the RZ/V2H(P) SoC we need to configure the UTMI to a specific value
as compared to other SoCs (which doesn't need configuring it).

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20250414145729.343133-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Lad Prabhakar and committed by

Vinod Koul 1 year ago 3767474d 9414ceb3

+30

1 changed file

expand all

drivers

phy

renesas

phy-rcar-gen3-usb2.c

+30

drivers/phy/renesas/phy-rcar-gen3-usb2.c

··· 28 28 #define USB2_INT_ENABLE 0x000 29 29 #define USB2_AHB_BUS_CTR 0x008 30 30 #define USB2_USBCTR 0x00c 31 + #define USB2_REGEN_CG_CTRL 0x104 /* RZ/V2H(P) only */ 31 32 #define USB2_SPD_RSM_TIMSET 0x10c 32 33 #define USB2_OC_TIMSET 0x110 34 + #define USB2_UTMI_CTRL 0x118 /* RZ/V2H(P) only */ 33 35 #define USB2_COMMCTRL 0x600 34 36 #define USB2_OBINTSTA 0x604 35 37 #define USB2_OBINTEN 0x608 ··· 52 50 #define USB2_USBCTR_DIRPD BIT(2) 53 51 #define USB2_USBCTR_PLL_RST BIT(1) 54 52 53 + /* REGEN_CG_CTRL*/ 54 + #define USB2_REGEN_CG_CTRL_UPHY_WEN BIT(0) 55 + 55 56 /* SPD_RSM_TIMSET */ 56 57 #define USB2_SPD_RSM_TIMSET_INIT 0x014e029b 57 58 58 59 /* OC_TIMSET */ 59 60 #define USB2_OC_TIMSET_INIT 0x000209ab 61 + 62 + /* UTMI_CTRL */ 63 + #define USB2_UTMI_CTRL_INIT 0x8000018f 60 64 61 65 /* COMMCTRL */ 62 66 #define USB2_COMMCTRL_OTG_PERI BIT(31) /* 1 = Peripheral mode */ ··· 135 127 bool is_otg_channel; 136 128 bool uses_otg_pins; 137 129 bool soc_no_adp_ctrl; 130 + bool utmi_ctrl; 138 131 }; 139 132 140 133 struct rcar_gen3_phy_drv_data { 141 134 const struct phy_ops *phy_usb2_ops; 142 135 bool no_adp_ctrl; 143 136 bool init_bus; 137 + bool utmi_ctrl; 144 138 }; 145 139 146 140 /* ··· 482 472 rphy->otg_initialized = true; 483 473 } 484 474 475 + if (channel->utmi_ctrl) { 476 + val = readl(usb2_base + USB2_REGEN_CG_CTRL) | USB2_REGEN_CG_CTRL_UPHY_WEN; 477 + writel(val, usb2_base + USB2_REGEN_CG_CTRL); 478 + 479 + writel(USB2_UTMI_CTRL_INIT, usb2_base + USB2_UTMI_CTRL); 480 + writel(val & ~USB2_REGEN_CG_CTRL_UPHY_WEN, usb2_base + USB2_REGEN_CG_CTRL); 481 + } 482 + 485 483 rphy->initialized = true; 486 484 487 485 return 0; ··· 607 589 .init_bus = true, 608 590 }; 609 591 592 + static const struct rcar_gen3_phy_drv_data rz_v2h_phy_usb2_data = { 593 + .phy_usb2_ops = &rcar_gen3_phy_usb2_ops, 594 + .no_adp_ctrl = true, 595 + .utmi_ctrl = true, 596 + }; 597 + 610 598 static const struct of_device_id rcar_gen3_phy_usb2_match_table[] = { 611 599 { 612 600 .compatible = "renesas,usb2-phy-r8a77470", ··· 633 609 { 634 610 .compatible = "renesas,usb2-phy-r9a08g045", 635 611 .data = &rz_g3s_phy_usb2_data, 612 + }, 613 + { 614 + .compatible = "renesas,usb2-phy-r9a09g057", 615 + .data = &rz_v2h_phy_usb2_data, 636 616 }, 637 617 { 638 618 .compatible = "renesas,rzg2l-usb2-phy", ··· 790 762 channel->soc_no_adp_ctrl = phy_data->no_adp_ctrl; 791 763 if (phy_data->no_adp_ctrl) 792 764 channel->obint_enable_bits = USB2_OBINT_IDCHG_EN; 765 + 766 + channel->utmi_ctrl = phy_data->utmi_ctrl; 793 767 794 768 mutex_init(&channel->lock); 795 769 for (i = 0; i < NUM_OF_PHYS; i++) {

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