Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/msm/a6xx: Split out gpucc register block
Some GPUs have different memory map for GPUCC block. So split out the
gpucc range from a6xx_gmu_cx_registers to a separate block to
accommodate those GPUs.
Signed-off-by: Jie Zhang <quic_jiezh@quicinc.com>
Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/640052/
Signed-off-by: Rob Clark <robdclark@chromium.org>
+10
-3
+5
-3
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
+5
-3
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
···
1214
1214
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1215
1215
1216
1216
a6xx_state->gmu_registers = state_kcalloc(a6xx_state,
1217
-
3, sizeof(*a6xx_state->gmu_registers));
1217
+
4, sizeof(*a6xx_state->gmu_registers));
1218
1218
1219
1219
if (!a6xx_state->gmu_registers)
1220
1220
return;
1221
1221
1222
-
a6xx_state->nr_gmu_registers = 3;
1222
+
a6xx_state->nr_gmu_registers = 4;
1223
1223
1224
1224
/* Get the CX GMU registers from AHB */
1225
1225
_a6xx_get_gmu_registers(gpu, a6xx_state, &a6xx_gmu_reglist[0],
1226
1226
&a6xx_state->gmu_registers[0], false);
1227
1227
_a6xx_get_gmu_registers(gpu, a6xx_state, &a6xx_gmu_reglist[1],
1228
1228
&a6xx_state->gmu_registers[1], true);
1229
+
_a6xx_get_gmu_registers(gpu, a6xx_state, &a6xx_gpucc_reg,
1230
+
&a6xx_state->gmu_registers[2], false);
1229
1231
1230
1232
if (!a6xx_gmu_gx_is_on(&a6xx_gpu->gmu))
1231
1233
return;
···
1236
1234
gpu_write(gpu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0);
1237
1235
1238
1236
_a6xx_get_gmu_registers(gpu, a6xx_state, &a6xx_gmu_reglist[2],
1239
-
&a6xx_state->gmu_registers[2], false);
1237
+
&a6xx_state->gmu_registers[3], false);
1240
1238
}
1241
1239
1242
1240
static struct msm_gpu_state_bo *a6xx_snapshot_gmu_bo(
+5
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h
+5
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h
···
363
363
0x51e0, 0x51e2, 0x51f0, 0x51f0, 0x5200, 0x5201,
364
364
/* GMU AO */
365
365
0x9300, 0x9316, 0x9400, 0x9400,
366
+
};
367
+
368
+
static const u32 a6xx_gmu_gpucc_registers[] = {
366
369
/* GPU CC */
367
370
0x9800, 0x9812, 0x9840, 0x9852, 0x9c00, 0x9c04, 0x9c07, 0x9c0b,
368
371
0x9c15, 0x9c1c, 0x9c1e, 0x9c2d, 0x9c3c, 0x9c3d, 0x9c3f, 0x9c40,
···
388
385
REGS(a6xx_gmu_cx_rscc_registers, 0, 0),
389
386
REGS(a6xx_gmu_gx_registers, 0, 0),
390
387
};
388
+
389
+
static const struct a6xx_registers a6xx_gpucc_reg = REGS(a6xx_gmu_gpucc_registers, 0, 0);
391
390
392
391
static u32 a6xx_get_cp_roq_size(struct msm_gpu *gpu);
393
392
static u32 a7xx_get_cp_roq_size(struct msm_gpu *gpu);