drm/amdgpu: add UMA allocation setting helpers

+7

drivers/gpu/drm/amd/amdgpu/amdgpu.h

··· 1603 1603 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1604 1604 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1605 1605 bool amdgpu_acpi_is_power_shift_control_supported(void); 1606 + bool amdgpu_acpi_is_set_uma_allocation_size_supported(void); 1606 1607 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1607 1608 u8 perf_req, bool advertise); 1608 1609 int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1609 1610 u8 dev_state, bool drv_state); 1610 1611 int amdgpu_acpi_smart_shift_update(struct amdgpu_device *adev, 1611 1612 enum amdgpu_ss ss_state); 1613 + int amdgpu_acpi_set_uma_allocation_size(struct amdgpu_device *adev, u8 index, u8 type); 1612 1614 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1613 1615 int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, u64 *tmr_offset, 1614 1616 u64 *tmr_size); ··· 1639 1637 static inline void amdgpu_acpi_detect(void) { } 1640 1638 static inline void amdgpu_acpi_release(void) { } 1641 1639 static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; } 1640 + static inline bool amdgpu_acpi_is_set_uma_allocation_size_supported(void) { return false; } 1642 1641 static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1643 1642 u8 dev_state, bool drv_state) { return 0; } 1644 1643 static inline int amdgpu_acpi_smart_shift_update(struct amdgpu_device *adev, 1645 1644 enum amdgpu_ss ss_state) 1646 1645 { 1647 1646 return 0; 1647 + } 1648 + static inline int amdgpu_acpi_set_uma_allocation_size(struct amdgpu_device *adev, u8 index, u8 type) 1649 + { 1650 + return -EINVAL; 1648 1651 } 1649 1652 static inline void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps) { } 1650 1653 #endif

+43

drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c

··· 672 672 return amdgpu_acpi_priv.atcs.functions.power_shift_control; 673 673 } 674 674 675 + bool amdgpu_acpi_is_set_uma_allocation_size_supported(void) 676 + { 677 + return amdgpu_acpi_priv.atcs.functions.set_uma_allocation_size; 678 + } 679 + 675 680 /** 676 681 * amdgpu_acpi_pcie_notify_device_ready 677 682 * ··· 917 912 return numa_info; 918 913 } 919 914 #endif 915 + 916 + /** 917 + * amdgpu_acpi_set_uma_allocation_size - Set Unified Memory Architecture allocation size via ACPI 918 + * @adev: Pointer to the amdgpu_device structure 919 + * @index: Index specifying the UMA allocation 920 + * @type: Type of UMA allocation 921 + * 922 + * This function configures the UMA allocation size for the specified device 923 + * using ACPI methods. The allocation is determined by the provided index and type. 924 + * Returns 0 on success or a negative error code on failure. 925 + */ 926 + int amdgpu_acpi_set_uma_allocation_size(struct amdgpu_device *adev, u8 index, u8 type) 927 + { 928 + struct atcs_set_uma_allocation_size_input atcs_input; 929 + struct amdgpu_atcs *atcs = &amdgpu_acpi_priv.atcs; 930 + struct acpi_buffer params; 931 + union acpi_object *info; 932 + 933 + if (!amdgpu_acpi_is_set_uma_allocation_size_supported()) 934 + return -EINVAL; 935 + 936 + atcs_input.size = sizeof(struct atcs_set_uma_allocation_size_input); 937 + atcs_input.uma_size_index = index; 938 + atcs_input.uma_size_type = type; 939 + 940 + params.length = sizeof(struct atcs_set_uma_allocation_size_input); 941 + params.pointer = &atcs_input; 942 + 943 + info = amdgpu_atcs_call(atcs, ATCS_FUNCTION_SET_UMA_ALLOCATION_SIZE, &params); 944 + if (!info) { 945 + drm_err(adev_to_drm(adev), "ATCS UMA allocation size update failed\n"); 946 + return -EIO; 947 + } 948 + 949 + kfree(info); 950 + 951 + return 0; 952 + } 920 953 921 954 /** 922 955 * amdgpu_acpi_get_node_id - obtain the NUMA node id for corresponding amdgpu

+30

drivers/gpu/drm/amd/include/amd_acpi.h

··· 24 24 #ifndef AMD_ACPI_H 25 25 #define AMD_ACPI_H 26 26 27 + #include <linux/types.h> 28 + 27 29 #define ACPI_AC_CLASS "ac_adapter" 28 30 29 31 struct atif_verify_interface { ··· 112 110 u16 dgpu_id; /* client id (bit 2-0: func num, 7-3: dev num, 15-8: bus num) */ 113 111 u8 dev_acpi_state; /* D0 = 0, D3 hot = 3 */ 114 112 u8 drv_state; /* 0 = operational, 1 = not operational */ 113 + } __packed; 114 + 115 + struct atcs_get_uma_size_output { 116 + u16 size; /* structure size in bytes (includes size field) */ 117 + u32 uma_size_mb; /* allocated UMA size in MB */ 118 + } __packed; 119 + 120 + struct atcs_set_uma_allocation_size_input { 121 + u16 size; /* structure size in bytes (includes size field) */ 122 + u8 uma_size_index; /* UMA size index */ 123 + u8 uma_size_type; /* UMA size type */ 115 124 } __packed; 116 125 117 126 /* AMD hw uses four ACPI control methods: ··· 504 491 * WORD - dGPU id (bit 2-0: func num, 7-3: dev num, 15-8: bus num) 505 492 * BYTE - Device ACPI state 506 493 * BYTE - Driver state 494 + * OUTPUT: none 495 + */ 496 + 497 + #define ATCS_FUNCTION_GET_UMA_SIZE 0x6 498 + /* ARG0: ATCS_FUNCTION_GET_UMA_SIZE 499 + * ARG1: none 500 + * OUTPUT: 501 + * WORD - structure size in bytes (includes size field) 502 + * DWORD - allocated UMA size in MB 503 + */ 504 + 505 + #define ATCS_FUNCTION_SET_UMA_ALLOCATION_SIZE 0xA 506 + /* ARG0: ATCS_FUNCTION_SET_UMA_ALLOCATION_SIZE 507 + * ARG1: 508 + * WORD - structure size in bytes (includes size field) 509 + * BYTE - UMA size index 510 + * BYTE - UMA size type 507 511 * OUTPUT: none 508 512 */ 509 513

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