Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-2019-11-15' of git://anongit.freedesktop.org/drm/drm
Pull drm fixes from Dave Airlie:
"Here is this weeks non-intel hw vuln fixes pull. Three drivers, all
small fixes.
i915:
- MOCS table fixes for EHL and TGL
- Update Display's rawclock on resume
- GVT's dmabuf reference drop fix
amdgpu:
- Fix a potential crash in firmware parsing
sun4i:
- One fix to the dotclock dividers range for sun4i"
* tag 'drm-fixes-2019-11-15' of git://anongit.freedesktop.org/drm/drm:
drm/amdgpu: fix null pointer deref in firmware header printing
drm/i915/tgl: MOCS table update
Revert "drm/i915/ehl: Update MOCS table for EHL"
drm/sun4i: tcon: Set min division of TCON0_DCLK to 1.
drm/i915: update rawclk also on resume
drm/i915/gvt: fix dropping obj reference twice
+23
-37
+16
-22
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+16
-22
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
···
950
950
struct amdgpu_firmware_info *ucode)
951
951
{
952
952
struct amdgpu_device *adev = psp->adev;
953
-
const struct sdma_firmware_header_v1_0 *sdma_hdr =
954
-
(const struct sdma_firmware_header_v1_0 *)
955
-
adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data;
956
-
const struct gfx_firmware_header_v1_0 *ce_hdr =
957
-
(const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
958
-
const struct gfx_firmware_header_v1_0 *pfp_hdr =
959
-
(const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
960
-
const struct gfx_firmware_header_v1_0 *me_hdr =
961
-
(const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
962
-
const struct gfx_firmware_header_v1_0 *mec_hdr =
963
-
(const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
964
-
const struct rlc_firmware_header_v2_0 *rlc_hdr =
965
-
(const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
966
-
const struct smc_firmware_header_v1_0 *smc_hdr =
967
-
(const struct smc_firmware_header_v1_0 *)adev->pm.fw->data;
953
+
struct common_firmware_header *hdr;
968
954
969
955
switch (ucode->ucode_id) {
970
956
case AMDGPU_UCODE_ID_SDMA0:
···
961
975
case AMDGPU_UCODE_ID_SDMA5:
962
976
case AMDGPU_UCODE_ID_SDMA6:
963
977
case AMDGPU_UCODE_ID_SDMA7:
964
-
amdgpu_ucode_print_sdma_hdr(&sdma_hdr->header);
978
+
hdr = (struct common_firmware_header *)
979
+
adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data;
980
+
amdgpu_ucode_print_sdma_hdr(hdr);
965
981
break;
966
982
case AMDGPU_UCODE_ID_CP_CE:
967
-
amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
983
+
hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data;
984
+
amdgpu_ucode_print_gfx_hdr(hdr);
968
985
break;
969
986
case AMDGPU_UCODE_ID_CP_PFP:
970
-
amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
987
+
hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data;
988
+
amdgpu_ucode_print_gfx_hdr(hdr);
971
989
break;
972
990
case AMDGPU_UCODE_ID_CP_ME:
973
-
amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
991
+
hdr = (struct common_firmware_header *)adev->gfx.me_fw->data;
992
+
amdgpu_ucode_print_gfx_hdr(hdr);
974
993
break;
975
994
case AMDGPU_UCODE_ID_CP_MEC1:
976
-
amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
995
+
hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data;
996
+
amdgpu_ucode_print_gfx_hdr(hdr);
977
997
break;
978
998
case AMDGPU_UCODE_ID_RLC_G:
979
-
amdgpu_ucode_print_rlc_hdr(&rlc_hdr->header);
999
+
hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data;
1000
+
amdgpu_ucode_print_rlc_hdr(hdr);
980
1001
break;
981
1002
case AMDGPU_UCODE_ID_SMC:
982
-
amdgpu_ucode_print_smc_hdr(&smc_hdr->header);
1003
+
hdr = (struct common_firmware_header *)adev->pm.fw->data;
1004
+
amdgpu_ucode_print_smc_hdr(hdr);
983
1005
break;
984
1006
default:
985
1007
break;
+3
drivers/gpu/drm/i915/display/intel_display_power.c
+3
drivers/gpu/drm/i915/display/intel_display_power.c
···
4896
4896
4897
4897
power_domains->initializing = true;
4898
4898
4899
+
/* Must happen before power domain init on VLV/CHV */
4900
+
intel_update_rawclk(i915);
4901
+
4899
4902
if (INTEL_GEN(i915) >= 11) {
4900
4903
icl_display_core_init(i915, resume);
4901
4904
} else if (IS_CANNONLAKE(i915)) {
+1
-9
drivers/gpu/drm/i915/gt/intel_mocs.c
+1
-9
drivers/gpu/drm/i915/gt/intel_mocs.c
···
199
199
MOCS_ENTRY(15, \
200
200
LE_3_WB | LE_TC_1_LLC | LE_LRUM(2) | LE_AOM(1), \
201
201
L3_3_WB), \
202
-
/* Bypass LLC - Uncached (EHL+) */ \
203
-
MOCS_ENTRY(16, \
204
-
LE_1_UC | LE_TC_1_LLC | LE_SCF(1), \
205
-
L3_1_UC), \
206
-
/* Bypass LLC - L3 (Read-Only) (EHL+) */ \
207
-
MOCS_ENTRY(17, \
208
-
LE_1_UC | LE_TC_1_LLC | LE_SCF(1), \
209
-
L3_3_WB), \
210
202
/* Self-Snoop - L3 + LLC */ \
211
203
MOCS_ENTRY(18, \
212
204
LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SSE(3), \
···
262
270
L3_1_UC),
263
271
/* HW Special Case (Displayable) */
264
272
MOCS_ENTRY(61,
265
-
LE_1_UC | LE_TC_1_LLC | LE_SCF(1),
273
+
LE_1_UC | LE_TC_1_LLC,
266
274
L3_3_WB),
267
275
};
268
276
+2
-2
drivers/gpu/drm/i915/gvt/dmabuf.c
+2
-2
drivers/gpu/drm/i915/gvt/dmabuf.c
···
498
498
goto out_free_gem;
499
499
}
500
500
501
-
i915_gem_object_put(obj);
502
-
503
501
ret = dma_buf_fd(dmabuf, DRM_CLOEXEC | DRM_RDWR);
504
502
if (ret < 0) {
505
503
gvt_vgpu_err("create dma-buf fd failed ret:%d\n", ret);
···
521
523
dmabuf_fd,
522
524
file_count(dmabuf->file),
523
525
kref_read(&obj->base.refcount));
526
+
527
+
i915_gem_object_put(obj);
524
528
525
529
return dmabuf_fd;
526
530
-3
drivers/gpu/drm/i915/i915_drv.c
-3
drivers/gpu/drm/i915/i915_drv.c