tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'tty-4.9-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty

Pull tty/serial driver fixes from Greg KH:
"Here are a number of small tty and serial driver fixes for reported
issues for 4.9-rc3. Nothing major, but they do resolve a bunch of
problems with the tty core changes that are in 4.9-rc1, and finally
the atmel serial driver is back working properly.

All have been in linux-next with no reported issues"

* tag 'tty-4.9-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty:
tty: serial_core: fix NULL struct tty pointer access in uart_write_wakeup
tty: serial_core: Fix serial console crash on port shutdown
tty/serial: at91: fix hardware handshake on Atmel platforms
vt: clear selection before resizing
sc16is7xx: always write state when configuring GPIO as an output
sh-sci: document R8A7743/5 support
tty: serial: 8250: 8250_core: NXP SC16C2552 workaround
tty: limit terminal size to 4M chars
tty: serial: fsl_lpuart: Fix Tx DMA edge case
serial: 8250_lpss: enable MSI for sure
serial: core: fix console problems on uart_close
serial: 8250_uniphier: fix clearing divisor latch access bit
serial: 8250_uniphier: fix more unterminated string
serial: pch_uart: add terminate entry for dmi_system_id tables
devicetree: bindings: uart: Add new compatible string for ZynqMP
serial: xuartps: Add new compatible string for ZynqMP
serial: SERIAL_STM32 should depend on HAS_DMA
serial: stm32: Fix comparisons with undefined register
tty: vt, fix bogus division in csi_J

Linus Torvalds 37cc6bb8 9af6f26a

+60 -19
+3 -1
Documentation/devicetree/bindings/serial/cdns,uart.txt
··· 1 1 Binding for Cadence UART Controller 2 2 3 3 Required properties: 4 - - compatible : should be "cdns,uart-r1p8", or "xlnx,xuartps" 4 + - compatible : 5 + Use "xlnx,xuartps","cdns,uart-r1p8" for Zynq-7xxx SoC. 6 + Use "xlnx,zynqmp-uart","cdns,uart-r1p12" for Zynq Ultrascale+ MPSoC. 5 7 - reg: Should contain UART controller registers location and length. 6 8 - interrupts: Should contain UART controller interrupts. 7 9 - clocks: Must contain phandles to the UART clocks
+8
Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
··· 9 9 - "renesas,scifb-r8a73a4" for R8A73A4 (R-Mobile APE6) SCIFB compatible UART. 10 10 - "renesas,scifa-r8a7740" for R8A7740 (R-Mobile A1) SCIFA compatible UART. 11 11 - "renesas,scifb-r8a7740" for R8A7740 (R-Mobile A1) SCIFB compatible UART. 12 + - "renesas,scif-r8a7743" for R8A7743 (RZ/G1M) SCIF compatible UART. 13 + - "renesas,scifa-r8a7743" for R8A7743 (RZ/G1M) SCIFA compatible UART. 14 + - "renesas,scifb-r8a7743" for R8A7743 (RZ/G1M) SCIFB compatible UART. 15 + - "renesas,hscif-r8a7743" for R8A7743 (RZ/G1M) HSCIF compatible UART. 16 + - "renesas,scif-r8a7745" for R8A7745 (RZ/G1E) SCIF compatible UART. 17 + - "renesas,scifa-r8a7745" for R8A7745 (RZ/G1E) SCIFA compatible UART. 18 + - "renesas,scifb-r8a7745" for R8A7745 (RZ/G1E) SCIFB compatible UART. 19 + - "renesas,hscif-r8a7745" for R8A7745 (RZ/G1E) HSCIF compatible UART. 12 20 - "renesas,scif-r8a7778" for R8A7778 (R-Car M1) SCIF compatible UART. 13 21 - "renesas,scif-r8a7779" for R8A7779 (R-Car H1) SCIF compatible UART. 14 22 - "renesas,scif-r8a7790" for R8A7790 (R-Car H2) SCIF compatible UART.
+1 -1
drivers/tty/serial/8250/8250_lpss.c
··· 213 213 struct pci_dev *pdev = to_pci_dev(port->dev); 214 214 int ret; 215 215 216 - ret = pci_alloc_irq_vectors(pdev, 1, 1, 0); 216 + ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 217 217 if (ret < 0) 218 218 return ret; 219 219
+2 -1
drivers/tty/serial/8250/8250_port.c
··· 83 83 .name = "16550A", 84 84 .fifo_size = 16, 85 85 .tx_loadsz = 16, 86 - .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 86 + .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 | 87 + UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT, 87 88 .rxtrig_bytes = {1, 4, 8, 14}, 88 89 .flags = UART_CAP_FIFO, 89 90 },
+2 -2
drivers/tty/serial/8250/8250_uniphier.c
··· 99 99 case UART_LCR: 100 100 valshift = UNIPHIER_UART_LCR_SHIFT; 101 101 /* Divisor latch access bit does not exist. */ 102 - value &= ~(UART_LCR_DLAB << valshift); 102 + value &= ~UART_LCR_DLAB; 103 103 /* fall through */ 104 104 case UART_MCR: 105 105 offset = UNIPHIER_UART_LCR_MCR; ··· 199 199 200 200 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 201 201 if (!regs) { 202 - dev_err(dev, "failed to get memory resource"); 202 + dev_err(dev, "failed to get memory resource\n"); 203 203 return -EINVAL; 204 204 } 205 205
+1
drivers/tty/serial/Kconfig
··· 1625 1625 config SERIAL_STM32 1626 1626 tristate "STMicroelectronics STM32 serial port support" 1627 1627 select SERIAL_CORE 1628 + depends on HAS_DMA 1628 1629 depends on ARM || COMPILE_TEST 1629 1630 help 1630 1631 This driver is for the on-chip Serial Controller on
+22 -4
drivers/tty/serial/atmel_serial.c
··· 2132 2132 mode |= ATMEL_US_USMODE_RS485; 2133 2133 } else if (termios->c_cflag & CRTSCTS) { 2134 2134 /* RS232 with hardware handshake (RTS/CTS) */ 2135 - if (atmel_use_dma_rx(port) && !atmel_use_fifo(port)) { 2136 - dev_info(port->dev, "not enabling hardware flow control because DMA is used"); 2137 - termios->c_cflag &= ~CRTSCTS; 2138 - } else { 2135 + if (atmel_use_fifo(port) && 2136 + !mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) { 2137 + /* 2138 + * with ATMEL_US_USMODE_HWHS set, the controller will 2139 + * be able to drive the RTS pin high/low when the RX 2140 + * FIFO is above RXFTHRES/below RXFTHRES2. 2141 + * It will also disable the transmitter when the CTS 2142 + * pin is high. 2143 + * This mode is not activated if CTS pin is a GPIO 2144 + * because in this case, the transmitter is always 2145 + * disabled (there must be an internal pull-up 2146 + * responsible for this behaviour). 2147 + * If the RTS pin is a GPIO, the controller won't be 2148 + * able to drive it according to the FIFO thresholds, 2149 + * but it will be handled by the driver. 2150 + */ 2139 2151 mode |= ATMEL_US_USMODE_HWHS; 2152 + } else { 2153 + /* 2154 + * For platforms without FIFO, the flow control is 2155 + * handled by the driver. 2156 + */ 2157 + mode |= ATMEL_US_USMODE_NORMAL; 2140 2158 } 2141 2159 } else { 2142 2160 /* RS232 without hadware handshake */
+1 -2
drivers/tty/serial/fsl_lpuart.c
··· 328 328 329 329 sport->dma_tx_bytes = uart_circ_chars_pending(xmit); 330 330 331 - if (xmit->tail < xmit->head) { 331 + if (xmit->tail < xmit->head || xmit->head == 0) { 332 332 sport->dma_tx_nents = 1; 333 333 sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes); 334 334 } else { ··· 359 359 sport->dma_tx_in_progress = true; 360 360 sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc); 361 361 dma_async_issue_pending(sport->dma_tx_chan); 362 - 363 362 } 364 363 365 364 static void lpuart_dma_tx_complete(void *arg)
+1
drivers/tty/serial/pch_uart.c
··· 419 419 }, 420 420 (void *)MINNOW_UARTCLK, 421 421 }, 422 + { } 422 423 }; 423 424 424 425 /* Return UART clock, checking for board specific clocks. */
+6 -2
drivers/tty/serial/sc16is7xx.c
··· 1130 1130 { 1131 1131 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1132 1132 struct uart_port *port = &s->p[0].port; 1133 + u8 state = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG); 1133 1134 1134 - sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset), 1135 - val ? BIT(offset) : 0); 1135 + if (val) 1136 + state |= BIT(offset); 1137 + else 1138 + state &= ~BIT(offset); 1139 + sc16is7xx_port_write(port, SC16IS7XX_IOSTATE_REG, state); 1136 1140 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 1137 1141 BIT(offset)); 1138 1142
+4 -4
drivers/tty/serial/serial_core.c
··· 111 111 * closed. No cookie for you. 112 112 */ 113 113 BUG_ON(!state); 114 - tty_wakeup(state->port.tty); 114 + tty_port_tty_wakeup(&state->port); 115 115 } 116 116 117 117 static void uart_stop(struct tty_struct *tty) ··· 632 632 if (port->ops->flush_buffer) 633 633 port->ops->flush_buffer(port); 634 634 uart_port_unlock(port, flags); 635 - tty_wakeup(tty); 635 + tty_port_tty_wakeup(&state->port); 636 636 } 637 637 638 638 /* ··· 2746 2746 uport->cons = drv->cons; 2747 2747 uport->minor = drv->tty_driver->minor_start + uport->line; 2748 2748 2749 - port->console = uart_console(uport); 2750 - 2751 2749 /* 2752 2750 * If this port is a console, then the spinlock is already 2753 2751 * initialised. ··· 2758 2760 of_console_check(uport->dev->of_node, uport->cons->name, uport->line); 2759 2761 2760 2762 uart_configure_port(drv, state, uport); 2763 + 2764 + port->console = uart_console(uport); 2761 2765 2762 2766 num_groups = 2; 2763 2767 if (uport->attr_group)
+1 -1
drivers/tty/serial/stm32-usart.h
··· 31 31 struct stm32_usart_config cfg; 32 32 }; 33 33 34 - #define UNDEF_REG ~0 34 + #define UNDEF_REG 0xff 35 35 36 36 /* Register offsets */ 37 37 struct stm32_usart_info stm32f4_info = {
+2
drivers/tty/serial/xilinx_uartps.c
··· 1200 1200 OF_EARLYCON_DECLARE(cdns, "xlnx,xuartps", cdns_early_console_setup); 1201 1201 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p8", cdns_early_console_setup); 1202 1202 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p12", cdns_early_console_setup); 1203 + OF_EARLYCON_DECLARE(cdns, "xlnx,zynqmp-uart", cdns_early_console_setup); 1203 1204 1204 1205 /** 1205 1206 * cdns_uart_console_write - perform write operation ··· 1439 1438 { .compatible = "xlnx,xuartps", }, 1440 1439 { .compatible = "cdns,uart-r1p8", }, 1441 1440 { .compatible = "cdns,uart-r1p12", .data = &zynqmp_uart_def }, 1441 + { .compatible = "xlnx,zynqmp-uart", .data = &zynqmp_uart_def }, 1442 1442 {} 1443 1443 }; 1444 1444 MODULE_DEVICE_TABLE(of, cdns_uart_of_match);
+6 -1
drivers/tty/vt/vt.c
··· 870 870 if (new_cols == vc->vc_cols && new_rows == vc->vc_rows) 871 871 return 0; 872 872 873 + if (new_screen_size > (4 << 20)) 874 + return -EINVAL; 873 875 newscreen = kmalloc(new_screen_size, GFP_USER); 874 876 if (!newscreen) 875 877 return -ENOMEM; 878 + 879 + if (vc == sel_cons) 880 + clear_selection(); 876 881 877 882 old_rows = vc->vc_rows; 878 883 old_row_size = vc->vc_size_row; ··· 1181 1176 break; 1182 1177 case 3: /* erase scroll-back buffer (and whole display) */ 1183 1178 scr_memsetw(vc->vc_screenbuf, vc->vc_video_erase_char, 1184 - vc->vc_screenbuf_size >> 1); 1179 + vc->vc_screenbuf_size); 1185 1180 set_origin(vc); 1186 1181 if (con_is_visible(vc)) 1187 1182 update_screen(vc);